fa_lru.hh revision 12746:0d0c266663d4 
1/*
2 * Copyright (c) 2012-2013,2016,2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 *          Nikos Nikoleris
42 */
43
44/**
45 * @file
46 * Declaration of a fully associative LRU tag store.
47 */
48
49#ifndef __MEM_CACHE_TAGS_FA_LRU_HH__
50#define __MEM_CACHE_TAGS_FA_LRU_HH__
51
52#include <cstdint>
53#include <functional>
54#include <string>
55#include <unordered_map>
56
57#include "base/bitfield.hh"
58#include "base/intmath.hh"
59#include "base/logging.hh"
60#include "base/statistics.hh"
61#include "base/types.hh"
62#include "mem/cache/blk.hh"
63#include "mem/cache/tags/base.hh"
64#include "mem/packet.hh"
65#include "params/FALRU.hh"
66
67// Uncomment to enable sanity checks for the FALRU cache and the
68// TrackedCaches class
69//#define FALRU_DEBUG
70
71// A bitmask of the caches we are keeping track of. Currently the
72// lowest bit is the smallest cache we are tracking, as it is
73// specified by the corresponding parameter. The rest of the bits are
74// for exponentially growing cache sizes.
75typedef uint32_t CachesMask;
76
77/**
78 * A fully associative cache block.
79 */
80class FALRUBlk : public CacheBlk
81{
82  public:
83    /** The previous block in LRU order. */
84    FALRUBlk *prev;
85    /** The next block in LRU order. */
86    FALRUBlk *next;
87
88    /** A bit mask of the caches that fit this block. */
89    CachesMask inCachesMask;
90};
91
92/**
93 * A fully associative LRU cache. Keeps statistics for accesses to a number of
94 * cache sizes at once.
95 */
96class FALRU : public BaseTags
97{
98  public:
99    /** Typedef the block type used in this class. */
100    typedef FALRUBlk BlkType;
101
102  protected:
103    /** The cache blocks. */
104    FALRUBlk *blks;
105
106    /** The MRU block. */
107    FALRUBlk *head;
108    /** The LRU block. */
109    FALRUBlk *tail;
110
111    /** Hash table type mapping addresses to cache block pointers. */
112    typedef std::unordered_map<Addr, FALRUBlk *, std::hash<Addr> > hash_t;
113    /** Iterator into the address hash table. */
114    typedef hash_t::const_iterator tagIterator;
115
116    /** The address hash table. */
117    hash_t tagHash;
118
119    /**
120     * Find the cache block for the given address.
121     * @param addr The address to find.
122     * @return The cache block of the address, if any.
123     */
124    FALRUBlk * hashLookup(Addr addr) const;
125
126    /**
127     * Move a cache block to the MRU position.
128     *
129     * @param blk The block to promote.
130     */
131    void moveToHead(FALRUBlk *blk);
132
133    /**
134     * Move a cache block to the LRU position.
135     *
136     * @param blk The block to demote.
137     */
138    void moveToTail(FALRUBlk *blk);
139
140  public:
141    typedef FALRUParams Params;
142
143    /**
144     * Construct and initialize this cache tagstore.
145     */
146    FALRU(const Params *p);
147    ~FALRU();
148
149    /**
150     * Register the stats for this object.
151     */
152    void regStats() override;
153
154    /**
155     * Invalidate a cache block.
156     * @param blk The block to invalidate.
157     */
158    void invalidate(CacheBlk *blk) override;
159
160    /**
161     * Access block and update replacement data.  May not succeed, in which
162     * case nullptr pointer is returned.  This has all the implications of a
163     * cache access and should only be used as such.
164     * Returns the access latency and inCachesMask flags as a side effect.
165     * @param addr The address to look for.
166     * @param is_secure True if the target memory space is secure.
167     * @param lat The latency of the access.
168     * @param in_cache_mask Mask indicating the caches in which the blk fits.
169     * @return Pointer to the cache block.
170     */
171    CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat,
172                          CachesMask *in_cache_mask);
173
174    /**
175     * Just a wrapper of above function to conform with the base interface.
176     */
177    CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override;
178
179    /**
180     * Find the block in the cache, do not update the replacement data.
181     * @param addr The address to look for.
182     * @param is_secure True if the target memory space is secure.
183     * @param asid The address space ID.
184     * @return Pointer to the cache block.
185     */
186    CacheBlk* findBlock(Addr addr, bool is_secure) const override;
187
188    /**
189     * Find a block given set and way.
190     *
191     * @param set The set of the block.
192     * @param way The way of the block.
193     * @return The block.
194     */
195    ReplaceableEntry* findBlockBySetAndWay(int set, int way) const override;
196
197    /**
198     * Find replacement victim based on address. The list of evicted blocks
199     * only contains the victim.
200     *
201     * @param addr Address to find a victim for.
202     * @param is_secure True if the target memory space is secure.
203     * @param evict_blks Cache blocks to be evicted.
204     * @return Cache block to be replaced.
205     */
206    CacheBlk* findVictim(Addr addr, const bool is_secure,
207                         std::vector<CacheBlk*>& evict_blks) const override;
208
209    /**
210     * Insert the new block into the cache and update replacement data.
211     *
212     * @param pkt Packet holding the address to update
213     * @param blk The block to update.
214     */
215    void insertBlock(PacketPtr pkt, CacheBlk *blk) override;
216
217    /**
218     * Generate the tag from the addres. For fully associative this is just the
219     * block address.
220     * @param addr The address to get the tag from.
221     * @return The tag.
222     */
223    Addr extractTag(Addr addr) const override
224    {
225        return blkAlign(addr);
226    }
227
228    /**
229     * Regenerate the block address from the tag.
230     *
231     * @param block The block.
232     * @return the block address.
233     */
234    Addr regenerateBlkAddr(const CacheBlk* blk) const override
235    {
236        return blk->tag;
237    }
238
239    void forEachBlk(std::function<void(CacheBlk &)> visitor) override {
240        for (int i = 0; i < numBlocks; i++) {
241            visitor(blks[i]);
242        }
243    }
244
245    bool anyBlk(std::function<bool(CacheBlk &)> visitor) override {
246        for (int i = 0; i < numBlocks; i++) {
247            if (visitor(blks[i])) {
248                return true;
249            }
250        }
251        return false;
252    }
253
254  private:
255    /**
256     * Mechanism that allows us to simultaneously collect miss
257     * statistics for multiple caches. Currently, we keep track of
258     * caches from a set minimum size of interest up to the actual
259     * cache size.
260     */
261    class CacheTracking
262    {
263      public:
264        CacheTracking(unsigned min_size, unsigned max_size,
265                      unsigned block_size)
266            : blkSize(block_size),
267              minTrackedSize(min_size),
268              numTrackedCaches(max_size > min_size ?
269                               floorLog2(max_size) - floorLog2(min_size) : 0),
270              inAllCachesMask(mask(numTrackedCaches)),
271              boundaries(new FALRUBlk *[numTrackedCaches])
272        {
273            fatal_if(numTrackedCaches > sizeof(CachesMask) * 8,
274                     "Not enough bits (%s) in type CachesMask type to keep "
275                     "track of %d caches\n", sizeof(CachesMask),
276                     numTrackedCaches);
277        }
278
279        ~CacheTracking()
280        {
281            delete[] boundaries;
282        }
283
284        /**
285         * Initialiaze cache blocks and the tracking mechanism
286         *
287         * All blocks in the cache need to be initialized once.
288         *
289         * @param blk the MRU block
290         * @param blk the LRU block
291         */
292        void init(FALRUBlk *head, FALRUBlk *tail);
293
294        /**
295         * Update boundaries as a block will be moved to the MRU.
296         *
297         * For all caches that didn't fit the block before moving it,
298         * we move their boundaries one block closer to the MRU. We
299         * also update InCacheMasks as neccessary.
300         *
301         * @param blk the block that will be moved to the head
302         */
303        void moveBlockToHead(FALRUBlk *blk);
304
305        /**
306         * Update boundaries as a block will be moved to the LRU.
307         *
308         * For all caches that fitted the block before moving it, we
309         * move their boundaries one block closer to the LRU. We
310         * also update InCacheMasks as neccessary.
311         *
312         * @param blk the block that will be moved to the head
313         */
314        void moveBlockToTail(FALRUBlk *blk);
315
316        /**
317         * Notify of a block access.
318         *
319         * This should be called every time a block is accessed and it
320         * updates statistics. If the input block is nullptr then we
321         * treat the access as a miss. The block's InCacheMask
322         * determines the caches in which the block fits.
323         *
324         * @param blk the block to record the access for
325         */
326        void recordAccess(FALRUBlk *blk);
327
328        /**
329         * Check that the tracking mechanism is in consistent state.
330         *
331         * Iterate from the head (MRU) to the tail (LRU) of the list
332         * of blocks and assert the inCachesMask and the boundaries
333         * are in consistent state.
334         *
335         * @param head the MRU block of the actual cache
336         * @param head the LRU block of the actual cache
337         */
338        void check(FALRUBlk *head, FALRUBlk *tail);
339
340        /**
341         * Register the stats for this object.
342         */
343        void regStats(std::string name);
344
345      private:
346        /** The size of the cache block */
347        const unsigned blkSize;
348        /** The smallest cache we are tracking */
349        const unsigned minTrackedSize;
350        /** The number of different size caches being tracked. */
351        const int numTrackedCaches;
352        /** A mask for all cache being tracked. */
353        const CachesMask inAllCachesMask;
354        /** Array of pointers to blocks at the cache boundaries. */
355        FALRUBlk** boundaries;
356
357      protected:
358        /**
359         * @defgroup FALRUStats Fully Associative LRU specific statistics
360         * The FA lru stack lets us track multiple cache sizes at once. These
361         * statistics track the hits and misses for different cache sizes.
362         * @{
363         */
364
365        /** Hits in each cache */
366        Stats::Vector hits;
367        /** Misses in each cache */
368        Stats::Vector misses;
369        /** Total number of accesses */
370        Stats::Scalar accesses;
371
372        /**
373         * @}
374         */
375    };
376    CacheTracking cacheTracking;
377};
378
379#endif // __MEM_CACHE_TAGS_FA_LRU_HH__
380