fa_lru.hh revision 12600:e670dd17c8cf
1/* 2 * Copyright (c) 2012-2013,2016 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 */ 42 43/** 44 * @file 45 * Declaration of a fully associative LRU tag store. 46 */ 47 48#ifndef __MEM_CACHE_TAGS_FA_LRU_HH__ 49#define __MEM_CACHE_TAGS_FA_LRU_HH__ 50 51#include <list> 52#include <unordered_map> 53 54#include "mem/cache/base.hh" 55#include "mem/cache/blk.hh" 56#include "mem/cache/tags/base.hh" 57#include "mem/packet.hh" 58#include "params/FALRU.hh" 59 60/** 61 * A fully associative cache block. 62 */ 63class FALRUBlk : public CacheBlk 64{ 65public: 66 /** The previous block in LRU order. */ 67 FALRUBlk *prev; 68 /** The next block in LRU order. */ 69 FALRUBlk *next; 70 71 /** 72 * A bit mask of the sizes of cache that this block is resident in. 73 * Each bit represents a power of 2 in MB size cache. 74 * If bit 0 is set, this block is in a 1MB cache 75 * If bit 2 is set, this block is in a 4MB cache, etc. 76 * There is one bit for each cache smaller than the full size (default 77 * 16MB). 78 */ 79 int inCache; 80}; 81 82/** 83 * A fully associative LRU cache. Keeps statistics for accesses to a number of 84 * cache sizes at once. 85 */ 86class FALRU : public BaseTags 87{ 88 public: 89 /** Typedef the block type used in this class. */ 90 typedef FALRUBlk BlkType; 91 92 protected: 93 /** Array of pointers to blocks at the cache size boundaries. */ 94 FALRUBlk **cacheBoundaries; 95 /** A mask for the FALRUBlk::inCache bits. */ 96 int cacheMask; 97 /** The number of different size caches being tracked. */ 98 unsigned numCaches; 99 100 /** The cache blocks. */ 101 FALRUBlk *blks; 102 103 /** The MRU block. */ 104 FALRUBlk *head; 105 /** The LRU block. */ 106 FALRUBlk *tail; 107 108 /** Hash table type mapping addresses to cache block pointers. */ 109 typedef std::unordered_map<Addr, FALRUBlk *, std::hash<Addr> > hash_t; 110 /** Iterator into the address hash table. */ 111 typedef hash_t::const_iterator tagIterator; 112 113 /** The address hash table. */ 114 hash_t tagHash; 115 116 /** 117 * Find the cache block for the given address. 118 * @param addr The address to find. 119 * @return The cache block of the address, if any. 120 */ 121 FALRUBlk * hashLookup(Addr addr) const; 122 123 /** 124 * Move a cache block to the MRU position. 125 * @param blk The block to promote. 126 */ 127 void moveToHead(FALRUBlk *blk); 128 129 /** 130 * Check to make sure all the cache boundaries are still where they should 131 * be. Used for debugging. 132 * @return True if everything is correct. 133 */ 134 bool check(); 135 136 /** 137 * @defgroup FALRUStats Fully Associative LRU specific statistics 138 * The FA lru stack lets us track multiple cache sizes at once. These 139 * statistics track the hits and misses for different cache sizes. 140 * @{ 141 */ 142 143 /** Hits in each cache size >= 128K. */ 144 Stats::Vector hits; 145 /** Misses in each cache size >= 128K. */ 146 Stats::Vector misses; 147 /** Total number of accesses. */ 148 Stats::Scalar accesses; 149 150 /** 151 * @} 152 */ 153 154public: 155 156 typedef FALRUParams Params; 157 158 /** 159 * Construct and initialize this cache tagstore. 160 */ 161 FALRU(const Params *p); 162 ~FALRU(); 163 164 /** 165 * Register the stats for this object. 166 * @param name The name to prepend to the stats name. 167 */ 168 void regStats() override; 169 170 /** 171 * Invalidate a cache block. 172 * @param blk The block to invalidate. 173 */ 174 void invalidate(CacheBlk *blk) override; 175 176 /** 177 * Access block and update replacement data. May not succeed, in which 178 * case nullptr pointer is returned. This has all the implications of a 179 * cache access and should only be used as such. 180 * Returns the access latency and inCache flags as a side effect. 181 * @param addr The address to look for. 182 * @param is_secure True if the target memory space is secure. 183 * @param lat The latency of the access. 184 * @param inCache The FALRUBlk::inCache flags. 185 * @return Pointer to the cache block. 186 */ 187 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat, 188 int *inCache); 189 190 /** 191 * Just a wrapper of above function to conform with the base interface. 192 */ 193 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override; 194 195 /** 196 * Find the block in the cache, do not update the replacement data. 197 * @param addr The address to look for. 198 * @param is_secure True if the target memory space is secure. 199 * @param asid The address space ID. 200 * @return Pointer to the cache block. 201 */ 202 CacheBlk* findBlock(Addr addr, bool is_secure) const override; 203 204 /** 205 * Find replacement victim based on address. 206 * 207 * @param addr Address to find a victim for. 208 * @return Cache block to be replaced. 209 */ 210 CacheBlk* findVictim(Addr addr) override; 211 212 void insertBlock(PacketPtr pkt, CacheBlk *blk) override; 213 214 /** 215 * Find the cache block given set and way 216 * @param set The set of the block. 217 * @param way The way of the block. 218 * @return The cache block. 219 */ 220 CacheBlk* findBlockBySetAndWay(int set, int way) const override; 221 222 /** 223 * Generate the tag from the addres. For fully associative this is just the 224 * block address. 225 * @param addr The address to get the tag from. 226 * @return The tag. 227 */ 228 Addr extractTag(Addr addr) const override 229 { 230 return blkAlign(addr); 231 } 232 233 /** 234 * Return the set of an address. Only one set in a fully associative cache. 235 * @param addr The address to get the set from. 236 * @return 0. 237 */ 238 int extractSet(Addr addr) const override 239 { 240 return 0; 241 } 242 243 /** 244 * Regenerate the block address from the tag. 245 * 246 * @param block The block. 247 * @return the block address. 248 */ 249 Addr regenerateBlkAddr(const CacheBlk* blk) const override 250 { 251 return blk->tag; 252 } 253 254 /** 255 * @todo Implement as in lru. Currently not used 256 */ 257 virtual std::string print() const override { return ""; } 258 259 /** 260 * Visit each block in the tag store and apply a visitor to the 261 * block. 262 * 263 * The visitor should be a function (or object that behaves like a 264 * function) that takes a cache block reference as its parameter 265 * and returns a bool. A visitor can request the traversal to be 266 * stopped by returning false, returning true causes it to be 267 * called for the next block in the tag store. 268 * 269 * \param visitor Visitor to call on each block. 270 */ 271 void forEachBlk(CacheBlkVisitor &visitor) override { 272 for (int i = 0; i < numBlocks; i++) { 273 if (!visitor(blks[i])) 274 return; 275 } 276 } 277 278}; 279 280#endif // __MEM_CACHE_TAGS_FA_LRU_HH__ 281