fa_lru.hh revision 12743
12810Srdreslin@umich.edu/* 212665Snikos.nikoleris@arm.com * Copyright (c) 2012-2013,2016,2018 ARM Limited 39347SAndreas.Sandberg@arm.com * All rights reserved. 49347SAndreas.Sandberg@arm.com * 59347SAndreas.Sandberg@arm.com * The license below extends only to copyright in the software and shall 69347SAndreas.Sandberg@arm.com * not be construed as granting a license to any other intellectual 79347SAndreas.Sandberg@arm.com * property including but not limited to intellectual property relating 89347SAndreas.Sandberg@arm.com * to a hardware implementation of the functionality of the software 99347SAndreas.Sandberg@arm.com * licensed hereunder. You may use the software subject to the license 109347SAndreas.Sandberg@arm.com * terms below provided that you ensure that this notice is replicated 119347SAndreas.Sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 129347SAndreas.Sandberg@arm.com * modified or unmodified, in source code or in binary form. 139347SAndreas.Sandberg@arm.com * 142810Srdreslin@umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810Srdreslin@umich.edu * All rights reserved. 162810Srdreslin@umich.edu * 172810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 182810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 192810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 202810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 212810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 222810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 232810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 242810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 252810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 262810Srdreslin@umich.edu * this software without specific prior written permission. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810Srdreslin@umich.edu * 402810Srdreslin@umich.edu * Authors: Erik Hallnor 4112665Snikos.nikoleris@arm.com * Nikos Nikoleris 422810Srdreslin@umich.edu */ 432810Srdreslin@umich.edu 442810Srdreslin@umich.edu/** 452810Srdreslin@umich.edu * @file 462810Srdreslin@umich.edu * Declaration of a fully associative LRU tag store. 472810Srdreslin@umich.edu */ 482810Srdreslin@umich.edu 496216Snate@binkert.org#ifndef __MEM_CACHE_TAGS_FA_LRU_HH__ 506216Snate@binkert.org#define __MEM_CACHE_TAGS_FA_LRU_HH__ 512810Srdreslin@umich.edu 5212727Snikos.nikoleris@arm.com#include <cstdint> 5312728Snikos.nikoleris@arm.com#include <functional> 5412727Snikos.nikoleris@arm.com#include <string> 5511168Sandreas.hansson@arm.com#include <unordered_map> 562810Srdreslin@umich.edu 5712727Snikos.nikoleris@arm.com#include "base/bitfield.hh" 5812665Snikos.nikoleris@arm.com#include "base/intmath.hh" 5912727Snikos.nikoleris@arm.com#include "base/logging.hh" 6012727Snikos.nikoleris@arm.com#include "base/statistics.hh" 6112727Snikos.nikoleris@arm.com#include "base/types.hh" 6211486Snikos.nikoleris@arm.com#include "mem/cache/blk.hh" 638229Snate@binkert.org#include "mem/cache/tags/base.hh" 642810Srdreslin@umich.edu#include "mem/packet.hh" 659796Sprakash.ramrakhyani@arm.com#include "params/FALRU.hh" 662810Srdreslin@umich.edu 6712665Snikos.nikoleris@arm.com// Uncomment to enable sanity checks for the FALRU cache and the 6812665Snikos.nikoleris@arm.com// TrackedCaches class 6912665Snikos.nikoleris@arm.com//#define FALRU_DEBUG 7012665Snikos.nikoleris@arm.com 7112665Snikos.nikoleris@arm.com// A bitmask of the caches we are keeping track of. Currently the 7212665Snikos.nikoleris@arm.com// lowest bit is the smallest cache we are tracking, as it is 7312665Snikos.nikoleris@arm.com// specified by the corresponding parameter. The rest of the bits are 7412665Snikos.nikoleris@arm.com// for exponentially growing cache sizes. 7512665Snikos.nikoleris@arm.comtypedef uint32_t CachesMask; 7612665Snikos.nikoleris@arm.com 772810Srdreslin@umich.edu/** 782810Srdreslin@umich.edu * A fully associative cache block. 792810Srdreslin@umich.edu */ 802810Srdreslin@umich.educlass FALRUBlk : public CacheBlk 812810Srdreslin@umich.edu{ 8212636Sodanrc@yahoo.com.br public: 832810Srdreslin@umich.edu /** The previous block in LRU order. */ 842810Srdreslin@umich.edu FALRUBlk *prev; 852810Srdreslin@umich.edu /** The next block in LRU order. */ 862810Srdreslin@umich.edu FALRUBlk *next; 872810Srdreslin@umich.edu 8812665Snikos.nikoleris@arm.com /** A bit mask of the caches that fit this block. */ 8912665Snikos.nikoleris@arm.com CachesMask inCachesMask; 902810Srdreslin@umich.edu}; 912810Srdreslin@umich.edu 922810Srdreslin@umich.edu/** 932810Srdreslin@umich.edu * A fully associative LRU cache. Keeps statistics for accesses to a number of 942810Srdreslin@umich.edu * cache sizes at once. 952810Srdreslin@umich.edu */ 962810Srdreslin@umich.educlass FALRU : public BaseTags 972810Srdreslin@umich.edu{ 982810Srdreslin@umich.edu public: 992810Srdreslin@umich.edu /** Typedef the block type used in this class. */ 1002810Srdreslin@umich.edu typedef FALRUBlk BlkType; 1016227Snate@binkert.org 1022810Srdreslin@umich.edu protected: 1032810Srdreslin@umich.edu /** The cache blocks. */ 1042810Srdreslin@umich.edu FALRUBlk *blks; 1052810Srdreslin@umich.edu 1062810Srdreslin@umich.edu /** The MRU block. */ 1072810Srdreslin@umich.edu FALRUBlk *head; 1082810Srdreslin@umich.edu /** The LRU block. */ 1092810Srdreslin@umich.edu FALRUBlk *tail; 1102810Srdreslin@umich.edu 1112810Srdreslin@umich.edu /** Hash table type mapping addresses to cache block pointers. */ 11211168Sandreas.hansson@arm.com typedef std::unordered_map<Addr, FALRUBlk *, std::hash<Addr> > hash_t; 1132810Srdreslin@umich.edu /** Iterator into the address hash table. */ 1142810Srdreslin@umich.edu typedef hash_t::const_iterator tagIterator; 1152810Srdreslin@umich.edu 1162810Srdreslin@umich.edu /** The address hash table. */ 1172810Srdreslin@umich.edu hash_t tagHash; 1182810Srdreslin@umich.edu 1192810Srdreslin@umich.edu /** 1202810Srdreslin@umich.edu * Find the cache block for the given address. 1212810Srdreslin@umich.edu * @param addr The address to find. 1222810Srdreslin@umich.edu * @return The cache block of the address, if any. 1232810Srdreslin@umich.edu */ 1242810Srdreslin@umich.edu FALRUBlk * hashLookup(Addr addr) const; 1252810Srdreslin@umich.edu 1262810Srdreslin@umich.edu /** 1272810Srdreslin@umich.edu * Move a cache block to the MRU position. 12812648Sodanrc@yahoo.com.br * 1292810Srdreslin@umich.edu * @param blk The block to promote. 1302810Srdreslin@umich.edu */ 1312810Srdreslin@umich.edu void moveToHead(FALRUBlk *blk); 1322810Srdreslin@umich.edu 1332810Srdreslin@umich.edu /** 13412648Sodanrc@yahoo.com.br * Move a cache block to the LRU position. 13512648Sodanrc@yahoo.com.br * 13612648Sodanrc@yahoo.com.br * @param blk The block to demote. 13712648Sodanrc@yahoo.com.br */ 13812648Sodanrc@yahoo.com.br void moveToTail(FALRUBlk *blk); 13912648Sodanrc@yahoo.com.br 14012636Sodanrc@yahoo.com.br public: 1419796Sprakash.ramrakhyani@arm.com typedef FALRUParams Params; 1429796Sprakash.ramrakhyani@arm.com 1432810Srdreslin@umich.edu /** 1442810Srdreslin@umich.edu * Construct and initialize this cache tagstore. 1452810Srdreslin@umich.edu */ 1469796Sprakash.ramrakhyani@arm.com FALRU(const Params *p); 1479086Sandreas.hansson@arm.com ~FALRU(); 1482810Srdreslin@umich.edu 1492810Srdreslin@umich.edu /** 1502810Srdreslin@umich.edu * Register the stats for this object. 1512810Srdreslin@umich.edu */ 15211169Sandreas.hansson@arm.com void regStats() override; 1532810Srdreslin@umich.edu 1542810Srdreslin@umich.edu /** 1553862Sstever@eecs.umich.edu * Invalidate a cache block. 1563862Sstever@eecs.umich.edu * @param blk The block to invalidate. 1572810Srdreslin@umich.edu */ 15811169Sandreas.hansson@arm.com void invalidate(CacheBlk *blk) override; 1592810Srdreslin@umich.edu 1602810Srdreslin@umich.edu /** 16111483Snikos.nikoleris@arm.com * Access block and update replacement data. May not succeed, in which 16211484Snikos.nikoleris@arm.com * case nullptr pointer is returned. This has all the implications of a 16311484Snikos.nikoleris@arm.com * cache access and should only be used as such. 16412665Snikos.nikoleris@arm.com * Returns the access latency and inCachesMask flags as a side effect. 1652810Srdreslin@umich.edu * @param addr The address to look for. 16610028SGiacomo.Gabrielli@arm.com * @param is_secure True if the target memory space is secure. 1672810Srdreslin@umich.edu * @param lat The latency of the access. 16812665Snikos.nikoleris@arm.com * @param in_cache_mask Mask indicating the caches in which the blk fits. 1692810Srdreslin@umich.edu * @return Pointer to the cache block. 1702810Srdreslin@umich.edu */ 17110815Sdavid.guillen@arm.com CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat, 17212665Snikos.nikoleris@arm.com CachesMask *in_cache_mask); 17310815Sdavid.guillen@arm.com 17410815Sdavid.guillen@arm.com /** 17510815Sdavid.guillen@arm.com * Just a wrapper of above function to conform with the base interface. 17610815Sdavid.guillen@arm.com */ 17711870Snikos.nikoleris@arm.com CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override; 1782810Srdreslin@umich.edu 1792810Srdreslin@umich.edu /** 1802810Srdreslin@umich.edu * Find the block in the cache, do not update the replacement data. 1812810Srdreslin@umich.edu * @param addr The address to look for. 18210028SGiacomo.Gabrielli@arm.com * @param is_secure True if the target memory space is secure. 1832810Srdreslin@umich.edu * @param asid The address space ID. 1842810Srdreslin@umich.edu * @return Pointer to the cache block. 1852810Srdreslin@umich.edu */ 18611169Sandreas.hansson@arm.com CacheBlk* findBlock(Addr addr, bool is_secure) const override; 1872810Srdreslin@umich.edu 1882810Srdreslin@umich.edu /** 18912743Sodanrc@yahoo.com.br * Find a block given set and way. 19012743Sodanrc@yahoo.com.br * 19112743Sodanrc@yahoo.com.br * @param set The set of the block. 19212743Sodanrc@yahoo.com.br * @param way The way of the block. 19312743Sodanrc@yahoo.com.br * @return The block. 19412743Sodanrc@yahoo.com.br */ 19512743Sodanrc@yahoo.com.br ReplaceableEntry* findBlockBySetAndWay(int set, int way) const override; 19612743Sodanrc@yahoo.com.br 19712743Sodanrc@yahoo.com.br /** 19812600Sodanrc@yahoo.com.br * Find replacement victim based on address. 19912600Sodanrc@yahoo.com.br * 20012600Sodanrc@yahoo.com.br * @param addr Address to find a victim for. 20112600Sodanrc@yahoo.com.br * @return Cache block to be replaced. 2022810Srdreslin@umich.edu */ 20311169Sandreas.hansson@arm.com CacheBlk* findVictim(Addr addr) override; 2045717Shsul@eecs.umich.edu 20512636Sodanrc@yahoo.com.br /** 20612636Sodanrc@yahoo.com.br * Insert the new block into the cache and update replacement data. 20712636Sodanrc@yahoo.com.br * 20812636Sodanrc@yahoo.com.br * @param pkt Packet holding the address to update 20912636Sodanrc@yahoo.com.br * @param blk The block to update. 21012636Sodanrc@yahoo.com.br */ 21111169Sandreas.hansson@arm.com void insertBlock(PacketPtr pkt, CacheBlk *blk) override; 2122810Srdreslin@umich.edu 2132810Srdreslin@umich.edu /** 2142810Srdreslin@umich.edu * Generate the tag from the addres. For fully associative this is just the 2152810Srdreslin@umich.edu * block address. 2162810Srdreslin@umich.edu * @param addr The address to get the tag from. 2172810Srdreslin@umich.edu * @return The tag. 2182810Srdreslin@umich.edu */ 21911169Sandreas.hansson@arm.com Addr extractTag(Addr addr) const override 2202810Srdreslin@umich.edu { 2212810Srdreslin@umich.edu return blkAlign(addr); 2222810Srdreslin@umich.edu } 2232810Srdreslin@umich.edu 2242810Srdreslin@umich.edu /** 22512574Sodanrc@yahoo.com.br * Regenerate the block address from the tag. 22612574Sodanrc@yahoo.com.br * 22712574Sodanrc@yahoo.com.br * @param block The block. 2282810Srdreslin@umich.edu * @return the block address. 2292810Srdreslin@umich.edu */ 23012574Sodanrc@yahoo.com.br Addr regenerateBlkAddr(const CacheBlk* blk) const override 2312810Srdreslin@umich.edu { 23212574Sodanrc@yahoo.com.br return blk->tag; 2332810Srdreslin@umich.edu } 2347612SGene.Wu@arm.com 23512728Snikos.nikoleris@arm.com void forEachBlk(std::function<void(CacheBlk &)> visitor) override { 23612728Snikos.nikoleris@arm.com for (int i = 0; i < numBlocks; i++) { 23712728Snikos.nikoleris@arm.com visitor(blks[i]); 23812728Snikos.nikoleris@arm.com } 23912728Snikos.nikoleris@arm.com } 2409663Suri.wiener@arm.com 24112728Snikos.nikoleris@arm.com bool anyBlk(std::function<bool(CacheBlk &)> visitor) override { 2429347SAndreas.Sandberg@arm.com for (int i = 0; i < numBlocks; i++) { 24312728Snikos.nikoleris@arm.com if (visitor(blks[i])) { 24412728Snikos.nikoleris@arm.com return true; 24512728Snikos.nikoleris@arm.com } 2469347SAndreas.Sandberg@arm.com } 24712728Snikos.nikoleris@arm.com return false; 2489347SAndreas.Sandberg@arm.com } 24912665Snikos.nikoleris@arm.com 25012665Snikos.nikoleris@arm.com private: 25112665Snikos.nikoleris@arm.com /** 25212665Snikos.nikoleris@arm.com * Mechanism that allows us to simultaneously collect miss 25312665Snikos.nikoleris@arm.com * statistics for multiple caches. Currently, we keep track of 25412665Snikos.nikoleris@arm.com * caches from a set minimum size of interest up to the actual 25512665Snikos.nikoleris@arm.com * cache size. 25612665Snikos.nikoleris@arm.com */ 25712665Snikos.nikoleris@arm.com class CacheTracking 25812665Snikos.nikoleris@arm.com { 25912665Snikos.nikoleris@arm.com public: 26012665Snikos.nikoleris@arm.com CacheTracking(unsigned min_size, unsigned max_size, 26112665Snikos.nikoleris@arm.com unsigned block_size) 26212665Snikos.nikoleris@arm.com : blkSize(block_size), 26312665Snikos.nikoleris@arm.com minTrackedSize(min_size), 26412665Snikos.nikoleris@arm.com numTrackedCaches(max_size > min_size ? 26512665Snikos.nikoleris@arm.com floorLog2(max_size) - floorLog2(min_size) : 0), 26612665Snikos.nikoleris@arm.com inAllCachesMask(mask(numTrackedCaches)), 26712665Snikos.nikoleris@arm.com boundaries(new FALRUBlk *[numTrackedCaches]) 26812665Snikos.nikoleris@arm.com { 26912665Snikos.nikoleris@arm.com fatal_if(numTrackedCaches > sizeof(CachesMask) * 8, 27012665Snikos.nikoleris@arm.com "Not enough bits (%s) in type CachesMask type to keep " 27112665Snikos.nikoleris@arm.com "track of %d caches\n", sizeof(CachesMask), 27212665Snikos.nikoleris@arm.com numTrackedCaches); 27312665Snikos.nikoleris@arm.com } 27412665Snikos.nikoleris@arm.com 27512665Snikos.nikoleris@arm.com ~CacheTracking() 27612665Snikos.nikoleris@arm.com { 27712665Snikos.nikoleris@arm.com delete[] boundaries; 27812665Snikos.nikoleris@arm.com } 27912665Snikos.nikoleris@arm.com 28012665Snikos.nikoleris@arm.com /** 28112665Snikos.nikoleris@arm.com * Initialiaze cache blocks and the tracking mechanism 28212665Snikos.nikoleris@arm.com * 28312665Snikos.nikoleris@arm.com * All blocks in the cache need to be initialized once. 28412665Snikos.nikoleris@arm.com * 28512665Snikos.nikoleris@arm.com * @param blk the MRU block 28612665Snikos.nikoleris@arm.com * @param blk the LRU block 28712665Snikos.nikoleris@arm.com */ 28812665Snikos.nikoleris@arm.com void init(FALRUBlk *head, FALRUBlk *tail); 28912665Snikos.nikoleris@arm.com 29012665Snikos.nikoleris@arm.com /** 29112665Snikos.nikoleris@arm.com * Update boundaries as a block will be moved to the MRU. 29212665Snikos.nikoleris@arm.com * 29312665Snikos.nikoleris@arm.com * For all caches that didn't fit the block before moving it, 29412665Snikos.nikoleris@arm.com * we move their boundaries one block closer to the MRU. We 29512665Snikos.nikoleris@arm.com * also update InCacheMasks as neccessary. 29612665Snikos.nikoleris@arm.com * 29712665Snikos.nikoleris@arm.com * @param blk the block that will be moved to the head 29812665Snikos.nikoleris@arm.com */ 29912665Snikos.nikoleris@arm.com void moveBlockToHead(FALRUBlk *blk); 30012665Snikos.nikoleris@arm.com 30112665Snikos.nikoleris@arm.com /** 30212665Snikos.nikoleris@arm.com * Update boundaries as a block will be moved to the LRU. 30312665Snikos.nikoleris@arm.com * 30412665Snikos.nikoleris@arm.com * For all caches that fitted the block before moving it, we 30512665Snikos.nikoleris@arm.com * move their boundaries one block closer to the LRU. We 30612665Snikos.nikoleris@arm.com * also update InCacheMasks as neccessary. 30712665Snikos.nikoleris@arm.com * 30812665Snikos.nikoleris@arm.com * @param blk the block that will be moved to the head 30912665Snikos.nikoleris@arm.com */ 31012665Snikos.nikoleris@arm.com void moveBlockToTail(FALRUBlk *blk); 31112665Snikos.nikoleris@arm.com 31212665Snikos.nikoleris@arm.com /** 31312665Snikos.nikoleris@arm.com * Notify of a block access. 31412665Snikos.nikoleris@arm.com * 31512665Snikos.nikoleris@arm.com * This should be called every time a block is accessed and it 31612665Snikos.nikoleris@arm.com * updates statistics. If the input block is nullptr then we 31712665Snikos.nikoleris@arm.com * treat the access as a miss. The block's InCacheMask 31812665Snikos.nikoleris@arm.com * determines the caches in which the block fits. 31912665Snikos.nikoleris@arm.com * 32012665Snikos.nikoleris@arm.com * @param blk the block to record the access for 32112665Snikos.nikoleris@arm.com */ 32212665Snikos.nikoleris@arm.com void recordAccess(FALRUBlk *blk); 32312665Snikos.nikoleris@arm.com 32412665Snikos.nikoleris@arm.com /** 32512665Snikos.nikoleris@arm.com * Check that the tracking mechanism is in consistent state. 32612665Snikos.nikoleris@arm.com * 32712665Snikos.nikoleris@arm.com * Iterate from the head (MRU) to the tail (LRU) of the list 32812665Snikos.nikoleris@arm.com * of blocks and assert the inCachesMask and the boundaries 32912665Snikos.nikoleris@arm.com * are in consistent state. 33012665Snikos.nikoleris@arm.com * 33112665Snikos.nikoleris@arm.com * @param head the MRU block of the actual cache 33212665Snikos.nikoleris@arm.com * @param head the LRU block of the actual cache 33312665Snikos.nikoleris@arm.com */ 33412665Snikos.nikoleris@arm.com void check(FALRUBlk *head, FALRUBlk *tail); 33512665Snikos.nikoleris@arm.com 33612665Snikos.nikoleris@arm.com /** 33712665Snikos.nikoleris@arm.com * Register the stats for this object. 33812665Snikos.nikoleris@arm.com */ 33912665Snikos.nikoleris@arm.com void regStats(std::string name); 34012665Snikos.nikoleris@arm.com 34112665Snikos.nikoleris@arm.com private: 34212665Snikos.nikoleris@arm.com /** The size of the cache block */ 34312665Snikos.nikoleris@arm.com const unsigned blkSize; 34412665Snikos.nikoleris@arm.com /** The smallest cache we are tracking */ 34512665Snikos.nikoleris@arm.com const unsigned minTrackedSize; 34612665Snikos.nikoleris@arm.com /** The number of different size caches being tracked. */ 34712665Snikos.nikoleris@arm.com const int numTrackedCaches; 34812665Snikos.nikoleris@arm.com /** A mask for all cache being tracked. */ 34912665Snikos.nikoleris@arm.com const CachesMask inAllCachesMask; 35012665Snikos.nikoleris@arm.com /** Array of pointers to blocks at the cache boundaries. */ 35112665Snikos.nikoleris@arm.com FALRUBlk** boundaries; 35212665Snikos.nikoleris@arm.com 35312665Snikos.nikoleris@arm.com protected: 35412665Snikos.nikoleris@arm.com /** 35512665Snikos.nikoleris@arm.com * @defgroup FALRUStats Fully Associative LRU specific statistics 35612665Snikos.nikoleris@arm.com * The FA lru stack lets us track multiple cache sizes at once. These 35712665Snikos.nikoleris@arm.com * statistics track the hits and misses for different cache sizes. 35812665Snikos.nikoleris@arm.com * @{ 35912665Snikos.nikoleris@arm.com */ 36012665Snikos.nikoleris@arm.com 36112665Snikos.nikoleris@arm.com /** Hits in each cache */ 36212665Snikos.nikoleris@arm.com Stats::Vector hits; 36312665Snikos.nikoleris@arm.com /** Misses in each cache */ 36412665Snikos.nikoleris@arm.com Stats::Vector misses; 36512665Snikos.nikoleris@arm.com /** Total number of accesses */ 36612665Snikos.nikoleris@arm.com Stats::Scalar accesses; 36712665Snikos.nikoleris@arm.com 36812665Snikos.nikoleris@arm.com /** 36912665Snikos.nikoleris@arm.com * @} 37012665Snikos.nikoleris@arm.com */ 37112665Snikos.nikoleris@arm.com }; 37212665Snikos.nikoleris@arm.com CacheTracking cacheTracking; 3732810Srdreslin@umich.edu}; 3742810Srdreslin@umich.edu 3756216Snate@binkert.org#endif // __MEM_CACHE_TAGS_FA_LRU_HH__ 376