fa_lru.hh revision 12665
12810Srdreslin@umich.edu/* 212665Snikos.nikoleris@arm.com * Copyright (c) 2012-2013,2016,2018 ARM Limited 39347SAndreas.Sandberg@arm.com * All rights reserved. 49347SAndreas.Sandberg@arm.com * 59347SAndreas.Sandberg@arm.com * The license below extends only to copyright in the software and shall 69347SAndreas.Sandberg@arm.com * not be construed as granting a license to any other intellectual 79347SAndreas.Sandberg@arm.com * property including but not limited to intellectual property relating 89347SAndreas.Sandberg@arm.com * to a hardware implementation of the functionality of the software 99347SAndreas.Sandberg@arm.com * licensed hereunder. You may use the software subject to the license 109347SAndreas.Sandberg@arm.com * terms below provided that you ensure that this notice is replicated 119347SAndreas.Sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 129347SAndreas.Sandberg@arm.com * modified or unmodified, in source code or in binary form. 139347SAndreas.Sandberg@arm.com * 142810Srdreslin@umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810Srdreslin@umich.edu * All rights reserved. 162810Srdreslin@umich.edu * 172810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 182810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 192810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 202810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 212810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 222810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 232810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 242810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 252810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 262810Srdreslin@umich.edu * this software without specific prior written permission. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810Srdreslin@umich.edu * 402810Srdreslin@umich.edu * Authors: Erik Hallnor 4112665Snikos.nikoleris@arm.com * Nikos Nikoleris 422810Srdreslin@umich.edu */ 432810Srdreslin@umich.edu 442810Srdreslin@umich.edu/** 452810Srdreslin@umich.edu * @file 462810Srdreslin@umich.edu * Declaration of a fully associative LRU tag store. 472810Srdreslin@umich.edu */ 482810Srdreslin@umich.edu 496216Snate@binkert.org#ifndef __MEM_CACHE_TAGS_FA_LRU_HH__ 506216Snate@binkert.org#define __MEM_CACHE_TAGS_FA_LRU_HH__ 512810Srdreslin@umich.edu 522810Srdreslin@umich.edu#include <list> 5311168Sandreas.hansson@arm.com#include <unordered_map> 542810Srdreslin@umich.edu 5512665Snikos.nikoleris@arm.com#include "base/intmath.hh" 5611722Ssophiane.senni@gmail.com#include "mem/cache/base.hh" 5711486Snikos.nikoleris@arm.com#include "mem/cache/blk.hh" 588229Snate@binkert.org#include "mem/cache/tags/base.hh" 592810Srdreslin@umich.edu#include "mem/packet.hh" 609796Sprakash.ramrakhyani@arm.com#include "params/FALRU.hh" 612810Srdreslin@umich.edu 6212665Snikos.nikoleris@arm.com// Uncomment to enable sanity checks for the FALRU cache and the 6312665Snikos.nikoleris@arm.com// TrackedCaches class 6412665Snikos.nikoleris@arm.com//#define FALRU_DEBUG 6512665Snikos.nikoleris@arm.com 6612665Snikos.nikoleris@arm.com// A bitmask of the caches we are keeping track of. Currently the 6712665Snikos.nikoleris@arm.com// lowest bit is the smallest cache we are tracking, as it is 6812665Snikos.nikoleris@arm.com// specified by the corresponding parameter. The rest of the bits are 6912665Snikos.nikoleris@arm.com// for exponentially growing cache sizes. 7012665Snikos.nikoleris@arm.comtypedef uint32_t CachesMask; 7112665Snikos.nikoleris@arm.com 722810Srdreslin@umich.edu/** 732810Srdreslin@umich.edu * A fully associative cache block. 742810Srdreslin@umich.edu */ 752810Srdreslin@umich.educlass FALRUBlk : public CacheBlk 762810Srdreslin@umich.edu{ 7712636Sodanrc@yahoo.com.br public: 782810Srdreslin@umich.edu /** The previous block in LRU order. */ 792810Srdreslin@umich.edu FALRUBlk *prev; 802810Srdreslin@umich.edu /** The next block in LRU order. */ 812810Srdreslin@umich.edu FALRUBlk *next; 822810Srdreslin@umich.edu 8312665Snikos.nikoleris@arm.com /** A bit mask of the caches that fit this block. */ 8412665Snikos.nikoleris@arm.com CachesMask inCachesMask; 852810Srdreslin@umich.edu}; 862810Srdreslin@umich.edu 872810Srdreslin@umich.edu/** 882810Srdreslin@umich.edu * A fully associative LRU cache. Keeps statistics for accesses to a number of 892810Srdreslin@umich.edu * cache sizes at once. 902810Srdreslin@umich.edu */ 912810Srdreslin@umich.educlass FALRU : public BaseTags 922810Srdreslin@umich.edu{ 932810Srdreslin@umich.edu public: 942810Srdreslin@umich.edu /** Typedef the block type used in this class. */ 952810Srdreslin@umich.edu typedef FALRUBlk BlkType; 966227Snate@binkert.org 972810Srdreslin@umich.edu protected: 982810Srdreslin@umich.edu /** The cache blocks. */ 992810Srdreslin@umich.edu FALRUBlk *blks; 1002810Srdreslin@umich.edu 1012810Srdreslin@umich.edu /** The MRU block. */ 1022810Srdreslin@umich.edu FALRUBlk *head; 1032810Srdreslin@umich.edu /** The LRU block. */ 1042810Srdreslin@umich.edu FALRUBlk *tail; 1052810Srdreslin@umich.edu 1062810Srdreslin@umich.edu /** Hash table type mapping addresses to cache block pointers. */ 10711168Sandreas.hansson@arm.com typedef std::unordered_map<Addr, FALRUBlk *, std::hash<Addr> > hash_t; 1082810Srdreslin@umich.edu /** Iterator into the address hash table. */ 1092810Srdreslin@umich.edu typedef hash_t::const_iterator tagIterator; 1102810Srdreslin@umich.edu 1112810Srdreslin@umich.edu /** The address hash table. */ 1122810Srdreslin@umich.edu hash_t tagHash; 1132810Srdreslin@umich.edu 1142810Srdreslin@umich.edu /** 1152810Srdreslin@umich.edu * Find the cache block for the given address. 1162810Srdreslin@umich.edu * @param addr The address to find. 1172810Srdreslin@umich.edu * @return The cache block of the address, if any. 1182810Srdreslin@umich.edu */ 1192810Srdreslin@umich.edu FALRUBlk * hashLookup(Addr addr) const; 1202810Srdreslin@umich.edu 1212810Srdreslin@umich.edu /** 1222810Srdreslin@umich.edu * Move a cache block to the MRU position. 12312648Sodanrc@yahoo.com.br * 1242810Srdreslin@umich.edu * @param blk The block to promote. 1252810Srdreslin@umich.edu */ 1262810Srdreslin@umich.edu void moveToHead(FALRUBlk *blk); 1272810Srdreslin@umich.edu 1282810Srdreslin@umich.edu /** 12912648Sodanrc@yahoo.com.br * Move a cache block to the LRU position. 13012648Sodanrc@yahoo.com.br * 13112648Sodanrc@yahoo.com.br * @param blk The block to demote. 13212648Sodanrc@yahoo.com.br */ 13312648Sodanrc@yahoo.com.br void moveToTail(FALRUBlk *blk); 13412648Sodanrc@yahoo.com.br 13512636Sodanrc@yahoo.com.br public: 1369796Sprakash.ramrakhyani@arm.com typedef FALRUParams Params; 1379796Sprakash.ramrakhyani@arm.com 1382810Srdreslin@umich.edu /** 1392810Srdreslin@umich.edu * Construct and initialize this cache tagstore. 1402810Srdreslin@umich.edu */ 1419796Sprakash.ramrakhyani@arm.com FALRU(const Params *p); 1429086Sandreas.hansson@arm.com ~FALRU(); 1432810Srdreslin@umich.edu 1442810Srdreslin@umich.edu /** 1452810Srdreslin@umich.edu * Register the stats for this object. 1462810Srdreslin@umich.edu */ 14711169Sandreas.hansson@arm.com void regStats() override; 1482810Srdreslin@umich.edu 1492810Srdreslin@umich.edu /** 1503862Sstever@eecs.umich.edu * Invalidate a cache block. 1513862Sstever@eecs.umich.edu * @param blk The block to invalidate. 1522810Srdreslin@umich.edu */ 15311169Sandreas.hansson@arm.com void invalidate(CacheBlk *blk) override; 1542810Srdreslin@umich.edu 1552810Srdreslin@umich.edu /** 15611483Snikos.nikoleris@arm.com * Access block and update replacement data. May not succeed, in which 15711484Snikos.nikoleris@arm.com * case nullptr pointer is returned. This has all the implications of a 15811484Snikos.nikoleris@arm.com * cache access and should only be used as such. 15912665Snikos.nikoleris@arm.com * Returns the access latency and inCachesMask flags as a side effect. 1602810Srdreslin@umich.edu * @param addr The address to look for. 16110028SGiacomo.Gabrielli@arm.com * @param is_secure True if the target memory space is secure. 1622810Srdreslin@umich.edu * @param lat The latency of the access. 16312665Snikos.nikoleris@arm.com * @param in_cache_mask Mask indicating the caches in which the blk fits. 1642810Srdreslin@umich.edu * @return Pointer to the cache block. 1652810Srdreslin@umich.edu */ 16610815Sdavid.guillen@arm.com CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat, 16712665Snikos.nikoleris@arm.com CachesMask *in_cache_mask); 16810815Sdavid.guillen@arm.com 16910815Sdavid.guillen@arm.com /** 17010815Sdavid.guillen@arm.com * Just a wrapper of above function to conform with the base interface. 17110815Sdavid.guillen@arm.com */ 17211870Snikos.nikoleris@arm.com CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override; 1732810Srdreslin@umich.edu 1742810Srdreslin@umich.edu /** 1752810Srdreslin@umich.edu * Find the block in the cache, do not update the replacement data. 1762810Srdreslin@umich.edu * @param addr The address to look for. 17710028SGiacomo.Gabrielli@arm.com * @param is_secure True if the target memory space is secure. 1782810Srdreslin@umich.edu * @param asid The address space ID. 1792810Srdreslin@umich.edu * @return Pointer to the cache block. 1802810Srdreslin@umich.edu */ 18111169Sandreas.hansson@arm.com CacheBlk* findBlock(Addr addr, bool is_secure) const override; 1822810Srdreslin@umich.edu 1832810Srdreslin@umich.edu /** 18412600Sodanrc@yahoo.com.br * Find replacement victim based on address. 18512600Sodanrc@yahoo.com.br * 18612600Sodanrc@yahoo.com.br * @param addr Address to find a victim for. 18712600Sodanrc@yahoo.com.br * @return Cache block to be replaced. 1882810Srdreslin@umich.edu */ 18911169Sandreas.hansson@arm.com CacheBlk* findVictim(Addr addr) override; 1905717Shsul@eecs.umich.edu 19112636Sodanrc@yahoo.com.br /** 19212636Sodanrc@yahoo.com.br * Insert the new block into the cache and update replacement data. 19312636Sodanrc@yahoo.com.br * 19412636Sodanrc@yahoo.com.br * @param pkt Packet holding the address to update 19512636Sodanrc@yahoo.com.br * @param blk The block to update. 19612636Sodanrc@yahoo.com.br */ 19711169Sandreas.hansson@arm.com void insertBlock(PacketPtr pkt, CacheBlk *blk) override; 1982810Srdreslin@umich.edu 1992810Srdreslin@umich.edu /** 20010941Sdavid.guillen@arm.com * Find the cache block given set and way 20110941Sdavid.guillen@arm.com * @param set The set of the block. 20210941Sdavid.guillen@arm.com * @param way The way of the block. 20310941Sdavid.guillen@arm.com * @return The cache block. 20410941Sdavid.guillen@arm.com */ 20511169Sandreas.hansson@arm.com CacheBlk* findBlockBySetAndWay(int set, int way) const override; 20610941Sdavid.guillen@arm.com 20710941Sdavid.guillen@arm.com /** 2082810Srdreslin@umich.edu * Generate the tag from the addres. For fully associative this is just the 2092810Srdreslin@umich.edu * block address. 2102810Srdreslin@umich.edu * @param addr The address to get the tag from. 2112810Srdreslin@umich.edu * @return The tag. 2122810Srdreslin@umich.edu */ 21311169Sandreas.hansson@arm.com Addr extractTag(Addr addr) const override 2142810Srdreslin@umich.edu { 2152810Srdreslin@umich.edu return blkAlign(addr); 2162810Srdreslin@umich.edu } 2172810Srdreslin@umich.edu 2182810Srdreslin@umich.edu /** 2192810Srdreslin@umich.edu * Return the set of an address. Only one set in a fully associative cache. 2202810Srdreslin@umich.edu * @param addr The address to get the set from. 2212810Srdreslin@umich.edu * @return 0. 2222810Srdreslin@umich.edu */ 22311169Sandreas.hansson@arm.com int extractSet(Addr addr) const override 2242810Srdreslin@umich.edu { 2252810Srdreslin@umich.edu return 0; 2262810Srdreslin@umich.edu } 2272810Srdreslin@umich.edu 2282810Srdreslin@umich.edu /** 22912574Sodanrc@yahoo.com.br * Regenerate the block address from the tag. 23012574Sodanrc@yahoo.com.br * 23112574Sodanrc@yahoo.com.br * @param block The block. 2322810Srdreslin@umich.edu * @return the block address. 2332810Srdreslin@umich.edu */ 23412574Sodanrc@yahoo.com.br Addr regenerateBlkAddr(const CacheBlk* blk) const override 2352810Srdreslin@umich.edu { 23612574Sodanrc@yahoo.com.br return blk->tag; 2372810Srdreslin@umich.edu } 2387612SGene.Wu@arm.com 2397612SGene.Wu@arm.com /** 2409663Suri.wiener@arm.com * @todo Implement as in lru. Currently not used 2419663Suri.wiener@arm.com */ 24211169Sandreas.hansson@arm.com virtual std::string print() const override { return ""; } 2439663Suri.wiener@arm.com 2449663Suri.wiener@arm.com /** 2459347SAndreas.Sandberg@arm.com * Visit each block in the tag store and apply a visitor to the 2469347SAndreas.Sandberg@arm.com * block. 2479347SAndreas.Sandberg@arm.com * 2489347SAndreas.Sandberg@arm.com * The visitor should be a function (or object that behaves like a 2499347SAndreas.Sandberg@arm.com * function) that takes a cache block reference as its parameter 2509347SAndreas.Sandberg@arm.com * and returns a bool. A visitor can request the traversal to be 2519347SAndreas.Sandberg@arm.com * stopped by returning false, returning true causes it to be 2529347SAndreas.Sandberg@arm.com * called for the next block in the tag store. 2539347SAndreas.Sandberg@arm.com * 2549347SAndreas.Sandberg@arm.com * \param visitor Visitor to call on each block. 2559347SAndreas.Sandberg@arm.com */ 25611168Sandreas.hansson@arm.com void forEachBlk(CacheBlkVisitor &visitor) override { 2579347SAndreas.Sandberg@arm.com for (int i = 0; i < numBlocks; i++) { 2589347SAndreas.Sandberg@arm.com if (!visitor(blks[i])) 2599347SAndreas.Sandberg@arm.com return; 2609347SAndreas.Sandberg@arm.com } 2619347SAndreas.Sandberg@arm.com } 26212665Snikos.nikoleris@arm.com 26312665Snikos.nikoleris@arm.com private: 26412665Snikos.nikoleris@arm.com /** 26512665Snikos.nikoleris@arm.com * Mechanism that allows us to simultaneously collect miss 26612665Snikos.nikoleris@arm.com * statistics for multiple caches. Currently, we keep track of 26712665Snikos.nikoleris@arm.com * caches from a set minimum size of interest up to the actual 26812665Snikos.nikoleris@arm.com * cache size. 26912665Snikos.nikoleris@arm.com */ 27012665Snikos.nikoleris@arm.com class CacheTracking 27112665Snikos.nikoleris@arm.com { 27212665Snikos.nikoleris@arm.com public: 27312665Snikos.nikoleris@arm.com CacheTracking(unsigned min_size, unsigned max_size, 27412665Snikos.nikoleris@arm.com unsigned block_size) 27512665Snikos.nikoleris@arm.com : blkSize(block_size), 27612665Snikos.nikoleris@arm.com minTrackedSize(min_size), 27712665Snikos.nikoleris@arm.com numTrackedCaches(max_size > min_size ? 27812665Snikos.nikoleris@arm.com floorLog2(max_size) - floorLog2(min_size) : 0), 27912665Snikos.nikoleris@arm.com inAllCachesMask(mask(numTrackedCaches)), 28012665Snikos.nikoleris@arm.com boundaries(new FALRUBlk *[numTrackedCaches]) 28112665Snikos.nikoleris@arm.com { 28212665Snikos.nikoleris@arm.com fatal_if(numTrackedCaches > sizeof(CachesMask) * 8, 28312665Snikos.nikoleris@arm.com "Not enough bits (%s) in type CachesMask type to keep " 28412665Snikos.nikoleris@arm.com "track of %d caches\n", sizeof(CachesMask), 28512665Snikos.nikoleris@arm.com numTrackedCaches); 28612665Snikos.nikoleris@arm.com } 28712665Snikos.nikoleris@arm.com 28812665Snikos.nikoleris@arm.com ~CacheTracking() 28912665Snikos.nikoleris@arm.com { 29012665Snikos.nikoleris@arm.com delete[] boundaries; 29112665Snikos.nikoleris@arm.com } 29212665Snikos.nikoleris@arm.com 29312665Snikos.nikoleris@arm.com /** 29412665Snikos.nikoleris@arm.com * Initialiaze cache blocks and the tracking mechanism 29512665Snikos.nikoleris@arm.com * 29612665Snikos.nikoleris@arm.com * All blocks in the cache need to be initialized once. 29712665Snikos.nikoleris@arm.com * 29812665Snikos.nikoleris@arm.com * @param blk the MRU block 29912665Snikos.nikoleris@arm.com * @param blk the LRU block 30012665Snikos.nikoleris@arm.com */ 30112665Snikos.nikoleris@arm.com void init(FALRUBlk *head, FALRUBlk *tail); 30212665Snikos.nikoleris@arm.com 30312665Snikos.nikoleris@arm.com /** 30412665Snikos.nikoleris@arm.com * Update boundaries as a block will be moved to the MRU. 30512665Snikos.nikoleris@arm.com * 30612665Snikos.nikoleris@arm.com * For all caches that didn't fit the block before moving it, 30712665Snikos.nikoleris@arm.com * we move their boundaries one block closer to the MRU. We 30812665Snikos.nikoleris@arm.com * also update InCacheMasks as neccessary. 30912665Snikos.nikoleris@arm.com * 31012665Snikos.nikoleris@arm.com * @param blk the block that will be moved to the head 31112665Snikos.nikoleris@arm.com */ 31212665Snikos.nikoleris@arm.com void moveBlockToHead(FALRUBlk *blk); 31312665Snikos.nikoleris@arm.com 31412665Snikos.nikoleris@arm.com /** 31512665Snikos.nikoleris@arm.com * Update boundaries as a block will be moved to the LRU. 31612665Snikos.nikoleris@arm.com * 31712665Snikos.nikoleris@arm.com * For all caches that fitted the block before moving it, we 31812665Snikos.nikoleris@arm.com * move their boundaries one block closer to the LRU. We 31912665Snikos.nikoleris@arm.com * also update InCacheMasks as neccessary. 32012665Snikos.nikoleris@arm.com * 32112665Snikos.nikoleris@arm.com * @param blk the block that will be moved to the head 32212665Snikos.nikoleris@arm.com */ 32312665Snikos.nikoleris@arm.com void moveBlockToTail(FALRUBlk *blk); 32412665Snikos.nikoleris@arm.com 32512665Snikos.nikoleris@arm.com /** 32612665Snikos.nikoleris@arm.com * Notify of a block access. 32712665Snikos.nikoleris@arm.com * 32812665Snikos.nikoleris@arm.com * This should be called every time a block is accessed and it 32912665Snikos.nikoleris@arm.com * updates statistics. If the input block is nullptr then we 33012665Snikos.nikoleris@arm.com * treat the access as a miss. The block's InCacheMask 33112665Snikos.nikoleris@arm.com * determines the caches in which the block fits. 33212665Snikos.nikoleris@arm.com * 33312665Snikos.nikoleris@arm.com * @param blk the block to record the access for 33412665Snikos.nikoleris@arm.com */ 33512665Snikos.nikoleris@arm.com void recordAccess(FALRUBlk *blk); 33612665Snikos.nikoleris@arm.com 33712665Snikos.nikoleris@arm.com /** 33812665Snikos.nikoleris@arm.com * Check that the tracking mechanism is in consistent state. 33912665Snikos.nikoleris@arm.com * 34012665Snikos.nikoleris@arm.com * Iterate from the head (MRU) to the tail (LRU) of the list 34112665Snikos.nikoleris@arm.com * of blocks and assert the inCachesMask and the boundaries 34212665Snikos.nikoleris@arm.com * are in consistent state. 34312665Snikos.nikoleris@arm.com * 34412665Snikos.nikoleris@arm.com * @param head the MRU block of the actual cache 34512665Snikos.nikoleris@arm.com * @param head the LRU block of the actual cache 34612665Snikos.nikoleris@arm.com */ 34712665Snikos.nikoleris@arm.com void check(FALRUBlk *head, FALRUBlk *tail); 34812665Snikos.nikoleris@arm.com 34912665Snikos.nikoleris@arm.com /** 35012665Snikos.nikoleris@arm.com * Register the stats for this object. 35112665Snikos.nikoleris@arm.com */ 35212665Snikos.nikoleris@arm.com void regStats(std::string name); 35312665Snikos.nikoleris@arm.com 35412665Snikos.nikoleris@arm.com private: 35512665Snikos.nikoleris@arm.com /** The size of the cache block */ 35612665Snikos.nikoleris@arm.com const unsigned blkSize; 35712665Snikos.nikoleris@arm.com /** The smallest cache we are tracking */ 35812665Snikos.nikoleris@arm.com const unsigned minTrackedSize; 35912665Snikos.nikoleris@arm.com /** The number of different size caches being tracked. */ 36012665Snikos.nikoleris@arm.com const int numTrackedCaches; 36112665Snikos.nikoleris@arm.com /** A mask for all cache being tracked. */ 36212665Snikos.nikoleris@arm.com const CachesMask inAllCachesMask; 36312665Snikos.nikoleris@arm.com /** Array of pointers to blocks at the cache boundaries. */ 36412665Snikos.nikoleris@arm.com FALRUBlk** boundaries; 36512665Snikos.nikoleris@arm.com 36612665Snikos.nikoleris@arm.com protected: 36712665Snikos.nikoleris@arm.com /** 36812665Snikos.nikoleris@arm.com * @defgroup FALRUStats Fully Associative LRU specific statistics 36912665Snikos.nikoleris@arm.com * The FA lru stack lets us track multiple cache sizes at once. These 37012665Snikos.nikoleris@arm.com * statistics track the hits and misses for different cache sizes. 37112665Snikos.nikoleris@arm.com * @{ 37212665Snikos.nikoleris@arm.com */ 37312665Snikos.nikoleris@arm.com 37412665Snikos.nikoleris@arm.com /** Hits in each cache */ 37512665Snikos.nikoleris@arm.com Stats::Vector hits; 37612665Snikos.nikoleris@arm.com /** Misses in each cache */ 37712665Snikos.nikoleris@arm.com Stats::Vector misses; 37812665Snikos.nikoleris@arm.com /** Total number of accesses */ 37912665Snikos.nikoleris@arm.com Stats::Scalar accesses; 38012665Snikos.nikoleris@arm.com 38112665Snikos.nikoleris@arm.com /** 38212665Snikos.nikoleris@arm.com * @} 38312665Snikos.nikoleris@arm.com */ 38412665Snikos.nikoleris@arm.com }; 38512665Snikos.nikoleris@arm.com CacheTracking cacheTracking; 3862810Srdreslin@umich.edu}; 3872810Srdreslin@umich.edu 3886216Snate@binkert.org#endif // __MEM_CACHE_TAGS_FA_LRU_HH__ 389