fa_lru.hh revision 12648
12810Srdreslin@umich.edu/* 211870Snikos.nikoleris@arm.com * Copyright (c) 2012-2013,2016 ARM Limited 39347SAndreas.Sandberg@arm.com * All rights reserved. 49347SAndreas.Sandberg@arm.com * 59347SAndreas.Sandberg@arm.com * The license below extends only to copyright in the software and shall 69347SAndreas.Sandberg@arm.com * not be construed as granting a license to any other intellectual 79347SAndreas.Sandberg@arm.com * property including but not limited to intellectual property relating 89347SAndreas.Sandberg@arm.com * to a hardware implementation of the functionality of the software 99347SAndreas.Sandberg@arm.com * licensed hereunder. You may use the software subject to the license 109347SAndreas.Sandberg@arm.com * terms below provided that you ensure that this notice is replicated 119347SAndreas.Sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 129347SAndreas.Sandberg@arm.com * modified or unmodified, in source code or in binary form. 139347SAndreas.Sandberg@arm.com * 142810Srdreslin@umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810Srdreslin@umich.edu * All rights reserved. 162810Srdreslin@umich.edu * 172810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 182810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 192810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 202810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 212810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 222810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 232810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 242810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 252810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 262810Srdreslin@umich.edu * this software without specific prior written permission. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810Srdreslin@umich.edu * 402810Srdreslin@umich.edu * Authors: Erik Hallnor 412810Srdreslin@umich.edu */ 422810Srdreslin@umich.edu 432810Srdreslin@umich.edu/** 442810Srdreslin@umich.edu * @file 452810Srdreslin@umich.edu * Declaration of a fully associative LRU tag store. 462810Srdreslin@umich.edu */ 472810Srdreslin@umich.edu 486216Snate@binkert.org#ifndef __MEM_CACHE_TAGS_FA_LRU_HH__ 496216Snate@binkert.org#define __MEM_CACHE_TAGS_FA_LRU_HH__ 502810Srdreslin@umich.edu 512810Srdreslin@umich.edu#include <list> 5211168Sandreas.hansson@arm.com#include <unordered_map> 532810Srdreslin@umich.edu 5411722Ssophiane.senni@gmail.com#include "mem/cache/base.hh" 5511486Snikos.nikoleris@arm.com#include "mem/cache/blk.hh" 568229Snate@binkert.org#include "mem/cache/tags/base.hh" 572810Srdreslin@umich.edu#include "mem/packet.hh" 589796Sprakash.ramrakhyani@arm.com#include "params/FALRU.hh" 592810Srdreslin@umich.edu 602810Srdreslin@umich.edu/** 612810Srdreslin@umich.edu * A fully associative cache block. 622810Srdreslin@umich.edu */ 632810Srdreslin@umich.educlass FALRUBlk : public CacheBlk 642810Srdreslin@umich.edu{ 6512636Sodanrc@yahoo.com.br public: 662810Srdreslin@umich.edu /** The previous block in LRU order. */ 672810Srdreslin@umich.edu FALRUBlk *prev; 682810Srdreslin@umich.edu /** The next block in LRU order. */ 692810Srdreslin@umich.edu FALRUBlk *next; 702810Srdreslin@umich.edu 712810Srdreslin@umich.edu /** 722810Srdreslin@umich.edu * A bit mask of the sizes of cache that this block is resident in. 732810Srdreslin@umich.edu * Each bit represents a power of 2 in MB size cache. 742810Srdreslin@umich.edu * If bit 0 is set, this block is in a 1MB cache 752810Srdreslin@umich.edu * If bit 2 is set, this block is in a 4MB cache, etc. 762810Srdreslin@umich.edu * There is one bit for each cache smaller than the full size (default 772810Srdreslin@umich.edu * 16MB). 782810Srdreslin@umich.edu */ 792810Srdreslin@umich.edu int inCache; 802810Srdreslin@umich.edu}; 812810Srdreslin@umich.edu 822810Srdreslin@umich.edu/** 832810Srdreslin@umich.edu * A fully associative LRU cache. Keeps statistics for accesses to a number of 842810Srdreslin@umich.edu * cache sizes at once. 852810Srdreslin@umich.edu */ 862810Srdreslin@umich.educlass FALRU : public BaseTags 872810Srdreslin@umich.edu{ 882810Srdreslin@umich.edu public: 892810Srdreslin@umich.edu /** Typedef the block type used in this class. */ 902810Srdreslin@umich.edu typedef FALRUBlk BlkType; 916227Snate@binkert.org 922810Srdreslin@umich.edu protected: 932810Srdreslin@umich.edu /** Array of pointers to blocks at the cache size boundaries. */ 942810Srdreslin@umich.edu FALRUBlk **cacheBoundaries; 952810Srdreslin@umich.edu /** A mask for the FALRUBlk::inCache bits. */ 962810Srdreslin@umich.edu int cacheMask; 972810Srdreslin@umich.edu /** The number of different size caches being tracked. */ 986227Snate@binkert.org unsigned numCaches; 992810Srdreslin@umich.edu 1002810Srdreslin@umich.edu /** The cache blocks. */ 1012810Srdreslin@umich.edu FALRUBlk *blks; 1022810Srdreslin@umich.edu 1032810Srdreslin@umich.edu /** The MRU block. */ 1042810Srdreslin@umich.edu FALRUBlk *head; 1052810Srdreslin@umich.edu /** The LRU block. */ 1062810Srdreslin@umich.edu FALRUBlk *tail; 1072810Srdreslin@umich.edu 1082810Srdreslin@umich.edu /** Hash table type mapping addresses to cache block pointers. */ 10911168Sandreas.hansson@arm.com typedef std::unordered_map<Addr, FALRUBlk *, std::hash<Addr> > hash_t; 1102810Srdreslin@umich.edu /** Iterator into the address hash table. */ 1112810Srdreslin@umich.edu typedef hash_t::const_iterator tagIterator; 1122810Srdreslin@umich.edu 1132810Srdreslin@umich.edu /** The address hash table. */ 1142810Srdreslin@umich.edu hash_t tagHash; 1152810Srdreslin@umich.edu 1162810Srdreslin@umich.edu /** 1172810Srdreslin@umich.edu * Find the cache block for the given address. 1182810Srdreslin@umich.edu * @param addr The address to find. 1192810Srdreslin@umich.edu * @return The cache block of the address, if any. 1202810Srdreslin@umich.edu */ 1212810Srdreslin@umich.edu FALRUBlk * hashLookup(Addr addr) const; 1222810Srdreslin@umich.edu 1232810Srdreslin@umich.edu /** 1242810Srdreslin@umich.edu * Move a cache block to the MRU position. 12512648Sodanrc@yahoo.com.br * 1262810Srdreslin@umich.edu * @param blk The block to promote. 1272810Srdreslin@umich.edu */ 1282810Srdreslin@umich.edu void moveToHead(FALRUBlk *blk); 1292810Srdreslin@umich.edu 1302810Srdreslin@umich.edu /** 13112648Sodanrc@yahoo.com.br * Move a cache block to the LRU position. 13212648Sodanrc@yahoo.com.br * 13312648Sodanrc@yahoo.com.br * @param blk The block to demote. 13412648Sodanrc@yahoo.com.br */ 13512648Sodanrc@yahoo.com.br void moveToTail(FALRUBlk *blk); 13612648Sodanrc@yahoo.com.br 13712648Sodanrc@yahoo.com.br /** 1382810Srdreslin@umich.edu * Check to make sure all the cache boundaries are still where they should 1392810Srdreslin@umich.edu * be. Used for debugging. 1402810Srdreslin@umich.edu * @return True if everything is correct. 1412810Srdreslin@umich.edu */ 1422810Srdreslin@umich.edu bool check(); 1432810Srdreslin@umich.edu 1442810Srdreslin@umich.edu /** 1452810Srdreslin@umich.edu * @defgroup FALRUStats Fully Associative LRU specific statistics 1462810Srdreslin@umich.edu * The FA lru stack lets us track multiple cache sizes at once. These 1472810Srdreslin@umich.edu * statistics track the hits and misses for different cache sizes. 1482810Srdreslin@umich.edu * @{ 1492810Srdreslin@umich.edu */ 1502810Srdreslin@umich.edu 1512810Srdreslin@umich.edu /** Hits in each cache size >= 128K. */ 1525999Snate@binkert.org Stats::Vector hits; 1532810Srdreslin@umich.edu /** Misses in each cache size >= 128K. */ 1545999Snate@binkert.org Stats::Vector misses; 1552810Srdreslin@umich.edu /** Total number of accesses. */ 1565999Snate@binkert.org Stats::Scalar accesses; 1572810Srdreslin@umich.edu 1582810Srdreslin@umich.edu /** 1592810Srdreslin@umich.edu * @} 1602810Srdreslin@umich.edu */ 1612810Srdreslin@umich.edu 16212636Sodanrc@yahoo.com.br public: 1639796Sprakash.ramrakhyani@arm.com typedef FALRUParams Params; 1649796Sprakash.ramrakhyani@arm.com 1652810Srdreslin@umich.edu /** 1662810Srdreslin@umich.edu * Construct and initialize this cache tagstore. 1672810Srdreslin@umich.edu */ 1689796Sprakash.ramrakhyani@arm.com FALRU(const Params *p); 1699086Sandreas.hansson@arm.com ~FALRU(); 1702810Srdreslin@umich.edu 1712810Srdreslin@umich.edu /** 1722810Srdreslin@umich.edu * Register the stats for this object. 1732810Srdreslin@umich.edu * @param name The name to prepend to the stats name. 1742810Srdreslin@umich.edu */ 17511169Sandreas.hansson@arm.com void regStats() override; 1762810Srdreslin@umich.edu 1772810Srdreslin@umich.edu /** 1783862Sstever@eecs.umich.edu * Invalidate a cache block. 1793862Sstever@eecs.umich.edu * @param blk The block to invalidate. 1802810Srdreslin@umich.edu */ 18111169Sandreas.hansson@arm.com void invalidate(CacheBlk *blk) override; 1822810Srdreslin@umich.edu 1832810Srdreslin@umich.edu /** 18411483Snikos.nikoleris@arm.com * Access block and update replacement data. May not succeed, in which 18511484Snikos.nikoleris@arm.com * case nullptr pointer is returned. This has all the implications of a 18611484Snikos.nikoleris@arm.com * cache access and should only be used as such. 1875716Shsul@eecs.umich.edu * Returns the access latency and inCache flags as a side effect. 1882810Srdreslin@umich.edu * @param addr The address to look for. 18910028SGiacomo.Gabrielli@arm.com * @param is_secure True if the target memory space is secure. 1902810Srdreslin@umich.edu * @param lat The latency of the access. 1912810Srdreslin@umich.edu * @param inCache The FALRUBlk::inCache flags. 1922810Srdreslin@umich.edu * @return Pointer to the cache block. 1932810Srdreslin@umich.edu */ 19410815Sdavid.guillen@arm.com CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat, 19511870Snikos.nikoleris@arm.com int *inCache); 19610815Sdavid.guillen@arm.com 19710815Sdavid.guillen@arm.com /** 19810815Sdavid.guillen@arm.com * Just a wrapper of above function to conform with the base interface. 19910815Sdavid.guillen@arm.com */ 20011870Snikos.nikoleris@arm.com CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override; 2012810Srdreslin@umich.edu 2022810Srdreslin@umich.edu /** 2032810Srdreslin@umich.edu * Find the block in the cache, do not update the replacement data. 2042810Srdreslin@umich.edu * @param addr The address to look for. 20510028SGiacomo.Gabrielli@arm.com * @param is_secure True if the target memory space is secure. 2062810Srdreslin@umich.edu * @param asid The address space ID. 2072810Srdreslin@umich.edu * @return Pointer to the cache block. 2082810Srdreslin@umich.edu */ 20911169Sandreas.hansson@arm.com CacheBlk* findBlock(Addr addr, bool is_secure) const override; 2102810Srdreslin@umich.edu 2112810Srdreslin@umich.edu /** 21212600Sodanrc@yahoo.com.br * Find replacement victim based on address. 21312600Sodanrc@yahoo.com.br * 21412600Sodanrc@yahoo.com.br * @param addr Address to find a victim for. 21512600Sodanrc@yahoo.com.br * @return Cache block to be replaced. 2162810Srdreslin@umich.edu */ 21711169Sandreas.hansson@arm.com CacheBlk* findVictim(Addr addr) override; 2185717Shsul@eecs.umich.edu 21912636Sodanrc@yahoo.com.br /** 22012636Sodanrc@yahoo.com.br * Insert the new block into the cache and update replacement data. 22112636Sodanrc@yahoo.com.br * 22212636Sodanrc@yahoo.com.br * @param pkt Packet holding the address to update 22312636Sodanrc@yahoo.com.br * @param blk The block to update. 22412636Sodanrc@yahoo.com.br */ 22511169Sandreas.hansson@arm.com void insertBlock(PacketPtr pkt, CacheBlk *blk) override; 2262810Srdreslin@umich.edu 2272810Srdreslin@umich.edu /** 22810941Sdavid.guillen@arm.com * Find the cache block given set and way 22910941Sdavid.guillen@arm.com * @param set The set of the block. 23010941Sdavid.guillen@arm.com * @param way The way of the block. 23110941Sdavid.guillen@arm.com * @return The cache block. 23210941Sdavid.guillen@arm.com */ 23311169Sandreas.hansson@arm.com CacheBlk* findBlockBySetAndWay(int set, int way) const override; 23410941Sdavid.guillen@arm.com 23510941Sdavid.guillen@arm.com /** 2362810Srdreslin@umich.edu * Generate the tag from the addres. For fully associative this is just the 2372810Srdreslin@umich.edu * block address. 2382810Srdreslin@umich.edu * @param addr The address to get the tag from. 2392810Srdreslin@umich.edu * @return The tag. 2402810Srdreslin@umich.edu */ 24111169Sandreas.hansson@arm.com Addr extractTag(Addr addr) const override 2422810Srdreslin@umich.edu { 2432810Srdreslin@umich.edu return blkAlign(addr); 2442810Srdreslin@umich.edu } 2452810Srdreslin@umich.edu 2462810Srdreslin@umich.edu /** 2472810Srdreslin@umich.edu * Return the set of an address. Only one set in a fully associative cache. 2482810Srdreslin@umich.edu * @param addr The address to get the set from. 2492810Srdreslin@umich.edu * @return 0. 2502810Srdreslin@umich.edu */ 25111169Sandreas.hansson@arm.com int extractSet(Addr addr) const override 2522810Srdreslin@umich.edu { 2532810Srdreslin@umich.edu return 0; 2542810Srdreslin@umich.edu } 2552810Srdreslin@umich.edu 2562810Srdreslin@umich.edu /** 25712574Sodanrc@yahoo.com.br * Regenerate the block address from the tag. 25812574Sodanrc@yahoo.com.br * 25912574Sodanrc@yahoo.com.br * @param block The block. 2602810Srdreslin@umich.edu * @return the block address. 2612810Srdreslin@umich.edu */ 26212574Sodanrc@yahoo.com.br Addr regenerateBlkAddr(const CacheBlk* blk) const override 2632810Srdreslin@umich.edu { 26412574Sodanrc@yahoo.com.br return blk->tag; 2652810Srdreslin@umich.edu } 2667612SGene.Wu@arm.com 2677612SGene.Wu@arm.com /** 2689663Suri.wiener@arm.com * @todo Implement as in lru. Currently not used 2699663Suri.wiener@arm.com */ 27011169Sandreas.hansson@arm.com virtual std::string print() const override { return ""; } 2719663Suri.wiener@arm.com 2729663Suri.wiener@arm.com /** 2739347SAndreas.Sandberg@arm.com * Visit each block in the tag store and apply a visitor to the 2749347SAndreas.Sandberg@arm.com * block. 2759347SAndreas.Sandberg@arm.com * 2769347SAndreas.Sandberg@arm.com * The visitor should be a function (or object that behaves like a 2779347SAndreas.Sandberg@arm.com * function) that takes a cache block reference as its parameter 2789347SAndreas.Sandberg@arm.com * and returns a bool. A visitor can request the traversal to be 2799347SAndreas.Sandberg@arm.com * stopped by returning false, returning true causes it to be 2809347SAndreas.Sandberg@arm.com * called for the next block in the tag store. 2819347SAndreas.Sandberg@arm.com * 2829347SAndreas.Sandberg@arm.com * \param visitor Visitor to call on each block. 2839347SAndreas.Sandberg@arm.com */ 28411168Sandreas.hansson@arm.com void forEachBlk(CacheBlkVisitor &visitor) override { 2859347SAndreas.Sandberg@arm.com for (int i = 0; i < numBlocks; i++) { 2869347SAndreas.Sandberg@arm.com if (!visitor(blks[i])) 2879347SAndreas.Sandberg@arm.com return; 2889347SAndreas.Sandberg@arm.com } 2899347SAndreas.Sandberg@arm.com } 2902810Srdreslin@umich.edu}; 2912810Srdreslin@umich.edu 2926216Snate@binkert.org#endif // __MEM_CACHE_TAGS_FA_LRU_HH__ 293