fa_lru.cc revision 10360
12810Srdreslin@umich.edu/* 29796Sprakash.ramrakhyani@arm.com * Copyright (c) 2013 ARM Limited 39796Sprakash.ramrakhyani@arm.com * All rights reserved. 49796Sprakash.ramrakhyani@arm.com * 59796Sprakash.ramrakhyani@arm.com * The license below extends only to copyright in the software and shall 69796Sprakash.ramrakhyani@arm.com * not be construed as granting a license to any other intellectual 79796Sprakash.ramrakhyani@arm.com * property including but not limited to intellectual property relating 89796Sprakash.ramrakhyani@arm.com * to a hardware implementation of the functionality of the software 99796Sprakash.ramrakhyani@arm.com * licensed hereunder. You may use the software subject to the license 109796Sprakash.ramrakhyani@arm.com * terms below provided that you ensure that this notice is replicated 119796Sprakash.ramrakhyani@arm.com * unmodified and in its entirety in all distributions of the software, 129796Sprakash.ramrakhyani@arm.com * modified or unmodified, in source code or in binary form. 139796Sprakash.ramrakhyani@arm.com * 142810Srdreslin@umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810Srdreslin@umich.edu * All rights reserved. 162810Srdreslin@umich.edu * 172810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 182810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 192810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 202810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 212810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 222810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 232810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 242810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 252810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 262810Srdreslin@umich.edu * this software without specific prior written permission. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810Srdreslin@umich.edu * 402810Srdreslin@umich.edu * Authors: Erik Hallnor 412810Srdreslin@umich.edu */ 422810Srdreslin@umich.edu 432810Srdreslin@umich.edu/** 442810Srdreslin@umich.edu * @file 452810Srdreslin@umich.edu * Definitions a fully associative LRU tagstore. 462810Srdreslin@umich.edu */ 472810Srdreslin@umich.edu 486216Snate@binkert.org#include <cassert> 492810Srdreslin@umich.edu#include <sstream> 502810Srdreslin@umich.edu 512810Srdreslin@umich.edu#include "base/intmath.hh" 522814Srdreslin@umich.edu#include "base/misc.hh" 536216Snate@binkert.org#include "mem/cache/tags/fa_lru.hh" 542810Srdreslin@umich.edu 552810Srdreslin@umich.eduusing namespace std; 562810Srdreslin@umich.edu 579796Sprakash.ramrakhyani@arm.comFALRU::FALRU(const Params *p) 5810360Sandreas.hansson@arm.com : BaseTags(p), cacheBoundaries(nullptr) 592810Srdreslin@umich.edu{ 602810Srdreslin@umich.edu if (!isPowerOf2(blkSize)) 612810Srdreslin@umich.edu fatal("cache block size (in bytes) `%d' must be a power of two", 622810Srdreslin@umich.edu blkSize); 632810Srdreslin@umich.edu if (!(hitLatency > 0)) 642810Srdreslin@umich.edu fatal("Access latency in cycles must be at least one cycle"); 652810Srdreslin@umich.edu if (!isPowerOf2(size)) 662810Srdreslin@umich.edu fatal("Cache Size must be power of 2 for now"); 672810Srdreslin@umich.edu 682810Srdreslin@umich.edu // Track all cache sizes from 128K up by powers of 2 692810Srdreslin@umich.edu numCaches = floorLog2(size) - 17; 702810Srdreslin@umich.edu if (numCaches >0){ 712810Srdreslin@umich.edu cacheBoundaries = new FALRUBlk *[numCaches]; 722810Srdreslin@umich.edu cacheMask = (1 << numCaches) - 1; 732810Srdreslin@umich.edu } else { 742810Srdreslin@umich.edu cacheMask = 0; 752810Srdreslin@umich.edu } 762810Srdreslin@umich.edu 772810Srdreslin@umich.edu warmupBound = size/blkSize; 786978SLisa.Hsu@amd.com numBlocks = size/blkSize; 792810Srdreslin@umich.edu 806978SLisa.Hsu@amd.com blks = new FALRUBlk[numBlocks]; 812810Srdreslin@umich.edu head = &(blks[0]); 826978SLisa.Hsu@amd.com tail = &(blks[numBlocks-1]); 832810Srdreslin@umich.edu 842810Srdreslin@umich.edu head->prev = NULL; 852810Srdreslin@umich.edu head->next = &(blks[1]); 862810Srdreslin@umich.edu head->inCache = cacheMask; 872810Srdreslin@umich.edu 886978SLisa.Hsu@amd.com tail->prev = &(blks[numBlocks-2]); 892810Srdreslin@umich.edu tail->next = NULL; 902810Srdreslin@umich.edu tail->inCache = 0; 912810Srdreslin@umich.edu 926227Snate@binkert.org unsigned index = (1 << 17) / blkSize; 936227Snate@binkert.org unsigned j = 0; 942810Srdreslin@umich.edu int flags = cacheMask; 956978SLisa.Hsu@amd.com for (unsigned i = 1; i < numBlocks - 1; i++) { 962810Srdreslin@umich.edu blks[i].inCache = flags; 972810Srdreslin@umich.edu if (i == index - 1){ 982810Srdreslin@umich.edu cacheBoundaries[j] = &(blks[i]); 992810Srdreslin@umich.edu flags &= ~ (1<<j); 1002810Srdreslin@umich.edu ++j; 1012810Srdreslin@umich.edu index = index << 1; 1022810Srdreslin@umich.edu } 1032810Srdreslin@umich.edu blks[i].prev = &(blks[i-1]); 1042810Srdreslin@umich.edu blks[i].next = &(blks[i+1]); 1052810Srdreslin@umich.edu blks[i].isTouched = false; 1062810Srdreslin@umich.edu } 1072810Srdreslin@umich.edu assert(j == numCaches); 1086978SLisa.Hsu@amd.com assert(index == numBlocks); 1092810Srdreslin@umich.edu //assert(check()); 1102810Srdreslin@umich.edu} 1112810Srdreslin@umich.edu 1129086Sandreas.hansson@arm.comFALRU::~FALRU() 1139086Sandreas.hansson@arm.com{ 1149086Sandreas.hansson@arm.com if (numCaches) 1159086Sandreas.hansson@arm.com delete[] cacheBoundaries; 1169086Sandreas.hansson@arm.com 1179086Sandreas.hansson@arm.com delete[] blks; 1189086Sandreas.hansson@arm.com} 1199086Sandreas.hansson@arm.com 1202810Srdreslin@umich.eduvoid 1219796Sprakash.ramrakhyani@arm.comFALRU::regStats() 1222810Srdreslin@umich.edu{ 1232810Srdreslin@umich.edu using namespace Stats; 1249796Sprakash.ramrakhyani@arm.com BaseTags::regStats(); 1252810Srdreslin@umich.edu hits 1262810Srdreslin@umich.edu .init(numCaches+1) 1279796Sprakash.ramrakhyani@arm.com .name(name() + ".falru_hits") 1282810Srdreslin@umich.edu .desc("The number of hits in each cache size.") 1292810Srdreslin@umich.edu ; 1302810Srdreslin@umich.edu misses 1312810Srdreslin@umich.edu .init(numCaches+1) 1329796Sprakash.ramrakhyani@arm.com .name(name() + ".falru_misses") 1332810Srdreslin@umich.edu .desc("The number of misses in each cache size.") 1342810Srdreslin@umich.edu ; 1352810Srdreslin@umich.edu accesses 1369796Sprakash.ramrakhyani@arm.com .name(name() + ".falru_accesses") 1372810Srdreslin@umich.edu .desc("The number of accesses to the FA LRU cache.") 1382810Srdreslin@umich.edu ; 1392810Srdreslin@umich.edu 1406227Snate@binkert.org for (unsigned i = 0; i <= numCaches; ++i) { 1412810Srdreslin@umich.edu stringstream size_str; 1422810Srdreslin@umich.edu if (i < 3){ 1432810Srdreslin@umich.edu size_str << (1<<(i+7)) <<"K"; 1442810Srdreslin@umich.edu } else { 1452810Srdreslin@umich.edu size_str << (1<<(i-3)) <<"M"; 1462810Srdreslin@umich.edu } 1472810Srdreslin@umich.edu 1482810Srdreslin@umich.edu hits.subname(i, size_str.str()); 1492810Srdreslin@umich.edu hits.subdesc(i, "Hits in a " + size_str.str() +" cache"); 1502810Srdreslin@umich.edu misses.subname(i, size_str.str()); 1512810Srdreslin@umich.edu misses.subdesc(i, "Misses in a " + size_str.str() +" cache"); 1522810Srdreslin@umich.edu } 1532810Srdreslin@umich.edu} 1542810Srdreslin@umich.edu 1552810Srdreslin@umich.eduFALRUBlk * 1562810Srdreslin@umich.eduFALRU::hashLookup(Addr addr) const 1572810Srdreslin@umich.edu{ 1582810Srdreslin@umich.edu tagIterator iter = tagHash.find(addr); 1592810Srdreslin@umich.edu if (iter != tagHash.end()) { 1602810Srdreslin@umich.edu return (*iter).second; 1612810Srdreslin@umich.edu } 1622810Srdreslin@umich.edu return NULL; 1632810Srdreslin@umich.edu} 1642810Srdreslin@umich.edu 1652810Srdreslin@umich.eduvoid 1669214Slena@cs.wisc.eduFALRU::invalidate(FALRU::BlkType *blk) 1672810Srdreslin@umich.edu{ 1689214Slena@cs.wisc.edu assert(blk); 1699214Slena@cs.wisc.edu tagsInUse--; 1702810Srdreslin@umich.edu} 1712810Srdreslin@umich.edu 1722810Srdreslin@umich.eduFALRUBlk* 17310028SGiacomo.Gabrielli@arm.comFALRU::accessBlock(Addr addr, bool is_secure, Cycles &lat, int context_src, 17410028SGiacomo.Gabrielli@arm.com int *inCache) 1752810Srdreslin@umich.edu{ 1762810Srdreslin@umich.edu accesses++; 1772810Srdreslin@umich.edu int tmp_in_cache = 0; 1782810Srdreslin@umich.edu Addr blkAddr = blkAlign(addr); 1792810Srdreslin@umich.edu FALRUBlk* blk = hashLookup(blkAddr); 1802810Srdreslin@umich.edu 1812810Srdreslin@umich.edu if (blk && blk->isValid()) { 1822810Srdreslin@umich.edu assert(blk->tag == blkAddr); 1832810Srdreslin@umich.edu tmp_in_cache = blk->inCache; 1846227Snate@binkert.org for (unsigned i = 0; i < numCaches; i++) { 1852810Srdreslin@umich.edu if (1<<i & blk->inCache) { 1862810Srdreslin@umich.edu hits[i]++; 1872810Srdreslin@umich.edu } else { 1882810Srdreslin@umich.edu misses[i]++; 1892810Srdreslin@umich.edu } 1902810Srdreslin@umich.edu } 1912810Srdreslin@umich.edu hits[numCaches]++; 1922810Srdreslin@umich.edu if (blk != head){ 1932810Srdreslin@umich.edu moveToHead(blk); 1942810Srdreslin@umich.edu } 1952810Srdreslin@umich.edu } else { 1962810Srdreslin@umich.edu blk = NULL; 1976227Snate@binkert.org for (unsigned i = 0; i <= numCaches; ++i) { 1982810Srdreslin@umich.edu misses[i]++; 1992810Srdreslin@umich.edu } 2002810Srdreslin@umich.edu } 2012810Srdreslin@umich.edu if (inCache) { 2022810Srdreslin@umich.edu *inCache = tmp_in_cache; 2032810Srdreslin@umich.edu } 2042810Srdreslin@umich.edu 2052810Srdreslin@umich.edu lat = hitLatency; 2062810Srdreslin@umich.edu //assert(check()); 2072810Srdreslin@umich.edu return blk; 2082810Srdreslin@umich.edu} 2092810Srdreslin@umich.edu 2102810Srdreslin@umich.edu 2112810Srdreslin@umich.eduFALRUBlk* 21210028SGiacomo.Gabrielli@arm.comFALRU::findBlock(Addr addr, bool is_secure) const 2132810Srdreslin@umich.edu{ 2142810Srdreslin@umich.edu Addr blkAddr = blkAlign(addr); 2152810Srdreslin@umich.edu FALRUBlk* blk = hashLookup(blkAddr); 2162810Srdreslin@umich.edu 2172810Srdreslin@umich.edu if (blk && blk->isValid()) { 2182810Srdreslin@umich.edu assert(blk->tag == blkAddr); 2192810Srdreslin@umich.edu } else { 2202810Srdreslin@umich.edu blk = NULL; 2212810Srdreslin@umich.edu } 2222810Srdreslin@umich.edu return blk; 2232810Srdreslin@umich.edu} 2242810Srdreslin@umich.edu 2252810Srdreslin@umich.eduFALRUBlk* 22610048Saminfar@gmail.comFALRU::findVictim(Addr addr) 2272810Srdreslin@umich.edu{ 2282810Srdreslin@umich.edu FALRUBlk * blk = tail; 2292810Srdreslin@umich.edu assert(blk->inCache == 0); 2302810Srdreslin@umich.edu moveToHead(blk); 2312810Srdreslin@umich.edu tagHash.erase(blk->tag); 2324626Sstever@eecs.umich.edu tagHash[blkAlign(addr)] = blk; 2332810Srdreslin@umich.edu if (blk->isValid()) { 2342814Srdreslin@umich.edu replacements[0]++; 2352810Srdreslin@umich.edu } else { 2362810Srdreslin@umich.edu tagsInUse++; 2372810Srdreslin@umich.edu blk->isTouched = true; 2382810Srdreslin@umich.edu if (!warmedUp && tagsInUse.value() >= warmupBound) { 2392810Srdreslin@umich.edu warmedUp = true; 2407823Ssteve.reinhardt@amd.com warmupCycle = curTick(); 2412810Srdreslin@umich.edu } 2422810Srdreslin@umich.edu } 2432810Srdreslin@umich.edu //assert(check()); 2442810Srdreslin@umich.edu return blk; 2452810Srdreslin@umich.edu} 2462810Srdreslin@umich.edu 2472810Srdreslin@umich.eduvoid 2489796Sprakash.ramrakhyani@arm.comFALRU::insertBlock(PacketPtr pkt, FALRU::BlkType *blk) 2495717Shsul@eecs.umich.edu{ 2505717Shsul@eecs.umich.edu} 2515717Shsul@eecs.umich.edu 2525717Shsul@eecs.umich.eduvoid 2532810Srdreslin@umich.eduFALRU::moveToHead(FALRUBlk *blk) 2542810Srdreslin@umich.edu{ 2552810Srdreslin@umich.edu int updateMask = blk->inCache ^ cacheMask; 2566227Snate@binkert.org for (unsigned i = 0; i < numCaches; i++){ 2572810Srdreslin@umich.edu if ((1<<i) & updateMask) { 2582810Srdreslin@umich.edu cacheBoundaries[i]->inCache &= ~(1<<i); 2592810Srdreslin@umich.edu cacheBoundaries[i] = cacheBoundaries[i]->prev; 2602810Srdreslin@umich.edu } else if (cacheBoundaries[i] == blk) { 2612810Srdreslin@umich.edu cacheBoundaries[i] = blk->prev; 2622810Srdreslin@umich.edu } 2632810Srdreslin@umich.edu } 2642810Srdreslin@umich.edu blk->inCache = cacheMask; 2652810Srdreslin@umich.edu if (blk != head) { 2662810Srdreslin@umich.edu if (blk == tail){ 2672810Srdreslin@umich.edu assert(blk->next == NULL); 2682810Srdreslin@umich.edu tail = blk->prev; 2692810Srdreslin@umich.edu tail->next = NULL; 2702810Srdreslin@umich.edu } else { 2712810Srdreslin@umich.edu blk->prev->next = blk->next; 2722810Srdreslin@umich.edu blk->next->prev = blk->prev; 2732810Srdreslin@umich.edu } 2742810Srdreslin@umich.edu blk->next = head; 2752810Srdreslin@umich.edu blk->prev = NULL; 2762810Srdreslin@umich.edu head->prev = blk; 2772810Srdreslin@umich.edu head = blk; 2782810Srdreslin@umich.edu } 2792810Srdreslin@umich.edu} 2802810Srdreslin@umich.edu 2812810Srdreslin@umich.edubool 2822810Srdreslin@umich.eduFALRU::check() 2832810Srdreslin@umich.edu{ 2842810Srdreslin@umich.edu FALRUBlk* blk = head; 2859550Sandreas.hansson@arm.com int tot_size = 0; 2862810Srdreslin@umich.edu int boundary = 1<<17; 2872810Srdreslin@umich.edu int j = 0; 2882810Srdreslin@umich.edu int flags = cacheMask; 2892810Srdreslin@umich.edu while (blk) { 2909550Sandreas.hansson@arm.com tot_size += blkSize; 2912810Srdreslin@umich.edu if (blk->inCache != flags) { 2922810Srdreslin@umich.edu return false; 2932810Srdreslin@umich.edu } 2949550Sandreas.hansson@arm.com if (tot_size == boundary && blk != tail) { 2952810Srdreslin@umich.edu if (cacheBoundaries[j] != blk) { 2962810Srdreslin@umich.edu return false; 2972810Srdreslin@umich.edu } 2982810Srdreslin@umich.edu flags &=~(1 << j); 2992810Srdreslin@umich.edu boundary = boundary<<1; 3002810Srdreslin@umich.edu ++j; 3012810Srdreslin@umich.edu } 3022810Srdreslin@umich.edu blk = blk->next; 3032810Srdreslin@umich.edu } 3042810Srdreslin@umich.edu return true; 3052810Srdreslin@umich.edu} 3067612SGene.Wu@arm.com 3077612SGene.Wu@arm.comvoid 3087612SGene.Wu@arm.comFALRU::clearLocks() 3097612SGene.Wu@arm.com{ 3107612SGene.Wu@arm.com for (int i = 0; i < numBlocks; i++){ 3117612SGene.Wu@arm.com blks[i].clearLoadLocks(); 3127612SGene.Wu@arm.com } 3137612SGene.Wu@arm.com} 3149796Sprakash.ramrakhyani@arm.com 3159796Sprakash.ramrakhyani@arm.comFALRU * 3169796Sprakash.ramrakhyani@arm.comFALRUParams::create() 3179796Sprakash.ramrakhyani@arm.com{ 3189796Sprakash.ramrakhyani@arm.com return new FALRU(this); 3199796Sprakash.ramrakhyani@arm.com} 3209796Sprakash.ramrakhyani@arm.com 321