base.hh revision 12727:56c23b54bcb1 
1/*
2 * Copyright (c) 2012-2014,2016-2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 *          Ron Dreslinski
42 */
43
44/**
45 * @file
46 * Declaration of a common base class for cache tagstore objects.
47 */
48
49#ifndef __MEM_CACHE_TAGS_BASE_HH__
50#define __MEM_CACHE_TAGS_BASE_HH__
51
52#include <cassert>
53#include <string>
54
55#include "base/callback.hh"
56#include "base/logging.hh"
57#include "base/statistics.hh"
58#include "base/types.hh"
59#include "mem/cache/blk.hh"
60#include "mem/packet.hh"
61#include "params/BaseTags.hh"
62#include "sim/clocked_object.hh"
63
64class BaseCache;
65
66/**
67 * A common base class of Cache tagstore objects.
68 */
69class BaseTags : public ClockedObject
70{
71  protected:
72    /** The block size of the cache. */
73    const unsigned blkSize;
74    /** Mask out all bits that aren't part of the block offset. */
75    const Addr blkMask;
76    /** The size of the cache. */
77    const unsigned size;
78    /** The tag lookup latency of the cache. */
79    const Cycles lookupLatency;
80    /**
81     * The total access latency of the cache. This latency
82     * is different depending on the cache access mode
83     * (parallel or sequential)
84     */
85    const Cycles accessLatency;
86    /** Pointer to the parent cache. */
87    BaseCache *cache;
88
89    /**
90     * The number of tags that need to be touched to meet the warmup
91     * percentage.
92     */
93    const unsigned warmupBound;
94    /** Marked true when the cache is warmed up. */
95    bool warmedUp;
96
97    /** the number of blocks in the cache */
98    const unsigned numBlocks;
99
100    /** The data blocks, 1 per cache block. */
101    std::unique_ptr<uint8_t[]> dataBlks;
102
103    // Statistics
104    /**
105     * TODO: It would be good if these stats were acquired after warmup.
106     * @addtogroup CacheStatistics
107     * @{
108     */
109
110    /** Per cycle average of the number of tags that hold valid data. */
111    Stats::Average tagsInUse;
112
113    /** The total number of references to a block before it is replaced. */
114    Stats::Scalar totalRefs;
115
116    /**
117     * The number of reference counts sampled. This is different from
118     * replacements because we sample all the valid blocks when the simulator
119     * exits.
120     */
121    Stats::Scalar sampledRefs;
122
123    /**
124     * Average number of references to a block before is was replaced.
125     * @todo This should change to an average stat once we have them.
126     */
127    Stats::Formula avgRefs;
128
129    /** The cycle that the warmup percentage was hit. 0 on failure. */
130    Stats::Scalar warmupCycle;
131
132    /** Average occupancy of each requestor using the cache */
133    Stats::AverageVector occupancies;
134
135    /** Average occ % of each requestor using the cache */
136    Stats::Formula avgOccs;
137
138    /** Occupancy of each context/cpu using the cache */
139    Stats::Vector occupanciesTaskId;
140
141    /** Occupancy of each context/cpu using the cache */
142    Stats::Vector2d ageTaskId;
143
144    /** Occ % of each context/cpu using the cache */
145    Stats::Formula percentOccsTaskId;
146
147    /** Number of tags consulted over all accesses. */
148    Stats::Scalar tagAccesses;
149    /** Number of data blocks consulted over all accesses. */
150    Stats::Scalar dataAccesses;
151
152    /**
153     * @}
154     */
155
156  public:
157    typedef BaseTagsParams Params;
158    BaseTags(const Params *p);
159
160    /**
161     * Destructor.
162     */
163    virtual ~BaseTags() {}
164
165    /**
166     * Set the parent cache back pointer.
167     * @param _cache Pointer to parent cache.
168     */
169    void setCache(BaseCache *_cache);
170
171    /**
172     * Register local statistics.
173     */
174    void regStats();
175
176    /**
177     * Average in the reference count for valid blocks when the simulation
178     * exits.
179     */
180    virtual void cleanupRefs() {}
181
182    /**
183     * Computes stats just prior to dump event
184     */
185    virtual void computeStats() {}
186
187    /**
188     * Print all tags used
189     */
190    virtual std::string print() const = 0;
191
192    /**
193     * Find a block using the memory address
194     */
195    virtual CacheBlk * findBlock(Addr addr, bool is_secure) const = 0;
196
197    /**
198     * Align an address to the block size.
199     * @param addr the address to align.
200     * @return The block address.
201     */
202    Addr blkAlign(Addr addr) const
203    {
204        return addr & ~blkMask;
205    }
206
207    /**
208     * Calculate the block offset of an address.
209     * @param addr the address to get the offset of.
210     * @return the block offset.
211     */
212    int extractBlkOffset(Addr addr) const
213    {
214        return (addr & blkMask);
215    }
216
217    /**
218     * Find the cache block given set and way
219     * @param set The set of the block.
220     * @param way The way of the block.
221     * @return The cache block.
222     */
223    virtual CacheBlk *findBlockBySetAndWay(int set, int way) const = 0;
224
225    /**
226     * Limit the allocation for the cache ways.
227     * @param ways The maximum number of ways available for replacement.
228     */
229    virtual void setWayAllocationMax(int ways)
230    {
231        panic("This tag class does not implement way allocation limit!\n");
232    }
233
234    /**
235     * Get the way allocation mask limit.
236     * @return The maximum number of ways available for replacement.
237     */
238    virtual int getWayAllocationMax() const
239    {
240        panic("This tag class does not implement way allocation limit!\n");
241        return -1;
242    }
243
244    /**
245     * This function updates the tags when a block is invalidated
246     *
247     * @param blk A valid block to invalidate.
248     */
249    virtual void invalidate(CacheBlk *blk)
250    {
251        assert(blk);
252        assert(blk->isValid());
253
254        tagsInUse--;
255        occupancies[blk->srcMasterId]--;
256        totalRefs += blk->refCount;
257        sampledRefs++;
258
259        blk->invalidate();
260    }
261
262    /**
263     * Find replacement victim based on address.
264     *
265     * @param addr Address to find a victim for.
266     * @return Cache block to be replaced.
267     */
268    virtual CacheBlk* findVictim(Addr addr) = 0;
269
270    virtual CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) = 0;
271
272    virtual Addr extractTag(Addr addr) const = 0;
273
274    /**
275     * Insert the new block into the cache and update stats.
276     *
277     * @param pkt Packet holding the address to update
278     * @param blk The block to update.
279     */
280    virtual void insertBlock(PacketPtr pkt, CacheBlk *blk);
281
282    /**
283     * Regenerate the block address.
284     *
285     * @param block The block.
286     * @return the block address.
287     */
288    virtual Addr regenerateBlkAddr(const CacheBlk* blk) const = 0;
289
290    virtual int extractSet(Addr addr) const = 0;
291
292    virtual void forEachBlk(CacheBlkVisitor &visitor) = 0;
293};
294
295class BaseTagsCallback : public Callback
296{
297    BaseTags *tags;
298  public:
299    BaseTagsCallback(BaseTags *t) : tags(t) {}
300    virtual void process() { tags->cleanupRefs(); };
301};
302
303class BaseTagsDumpCallback : public Callback
304{
305    BaseTags *tags;
306  public:
307    BaseTagsDumpCallback(BaseTags *t) : tags(t) {}
308    virtual void process() { tags->computeStats(); };
309};
310
311#endif //__MEM_CACHE_TAGS_BASE_HH__
312