base.hh revision 12629:c17d4dc2379e 
1/*
2 * Copyright (c) 2012-2014,2016-2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 *          Ron Dreslinski
42 */
43
44/**
45 * @file
46 * Declaration of a common base class for cache tagstore objects.
47 */
48
49#ifndef __MEM_CACHE_TAGS_BASE_HH__
50#define __MEM_CACHE_TAGS_BASE_HH__
51
52#include <string>
53
54#include "base/callback.hh"
55#include "base/statistics.hh"
56#include "mem/cache/blk.hh"
57#include "mem/cache/replacement_policies/base.hh"
58#include "params/BaseTags.hh"
59#include "sim/clocked_object.hh"
60
61class BaseCache;
62
63/**
64 * A common base class of Cache tagstore objects.
65 */
66class BaseTags : public ClockedObject
67{
68  protected:
69    /** The block size of the cache. */
70    const unsigned blkSize;
71    /** Mask out all bits that aren't part of the block offset. */
72    const Addr blkMask;
73    /** The size of the cache. */
74    const unsigned size;
75    /** The tag lookup latency of the cache. */
76    const Cycles lookupLatency;
77    /**
78     * The total access latency of the cache. This latency
79     * is different depending on the cache access mode
80     * (parallel or sequential)
81     */
82    const Cycles accessLatency;
83    /** Pointer to the parent cache. */
84    BaseCache *cache;
85
86    /**
87     * The number of tags that need to be touched to meet the warmup
88     * percentage.
89     */
90    const unsigned warmupBound;
91    /** Marked true when the cache is warmed up. */
92    bool warmedUp;
93
94    /** the number of blocks in the cache */
95    const unsigned numBlocks;
96
97    /** The data blocks, 1 per cache block. */
98    std::unique_ptr<uint8_t[]> dataBlks;
99
100    // Statistics
101    /**
102     * TODO: It would be good if these stats were acquired after warmup.
103     * @addtogroup CacheStatistics
104     * @{
105     */
106
107    /** Number of replacements of valid blocks per thread. */
108    Stats::Vector replacements;
109    /** Per cycle average of the number of tags that hold valid data. */
110    Stats::Average tagsInUse;
111
112    /** The total number of references to a block before it is replaced. */
113    Stats::Scalar totalRefs;
114
115    /**
116     * The number of reference counts sampled. This is different from
117     * replacements because we sample all the valid blocks when the simulator
118     * exits.
119     */
120    Stats::Scalar sampledRefs;
121
122    /**
123     * Average number of references to a block before is was replaced.
124     * @todo This should change to an average stat once we have them.
125     */
126    Stats::Formula avgRefs;
127
128    /** The cycle that the warmup percentage was hit. 0 on failure. */
129    Stats::Scalar warmupCycle;
130
131    /** Average occupancy of each requestor using the cache */
132    Stats::AverageVector occupancies;
133
134    /** Average occ % of each requestor using the cache */
135    Stats::Formula avgOccs;
136
137    /** Occupancy of each context/cpu using the cache */
138    Stats::Vector occupanciesTaskId;
139
140    /** Occupancy of each context/cpu using the cache */
141    Stats::Vector2d ageTaskId;
142
143    /** Occ % of each context/cpu using the cache */
144    Stats::Formula percentOccsTaskId;
145
146    /** Number of tags consulted over all accesses. */
147    Stats::Scalar tagAccesses;
148    /** Number of data blocks consulted over all accesses. */
149    Stats::Scalar dataAccesses;
150
151    /**
152     * @}
153     */
154
155  public:
156    typedef BaseTagsParams Params;
157    BaseTags(const Params *p);
158
159    /**
160     * Destructor.
161     */
162    virtual ~BaseTags() {}
163
164    /**
165     * Set the parent cache back pointer.
166     * @param _cache Pointer to parent cache.
167     */
168    void setCache(BaseCache *_cache);
169
170    /**
171     * Register local statistics.
172     */
173    void regStats();
174
175    /**
176     * Average in the reference count for valid blocks when the simulation
177     * exits.
178     */
179    virtual void cleanupRefs() {}
180
181    /**
182     * Computes stats just prior to dump event
183     */
184    virtual void computeStats() {}
185
186    /**
187     * Print all tags used
188     */
189    virtual std::string print() const = 0;
190
191    /**
192     * Find a block using the memory address
193     */
194    virtual CacheBlk * findBlock(Addr addr, bool is_secure) const = 0;
195
196    /**
197     * Align an address to the block size.
198     * @param addr the address to align.
199     * @return The block address.
200     */
201    Addr blkAlign(Addr addr) const
202    {
203        return addr & ~blkMask;
204    }
205
206    /**
207     * Calculate the block offset of an address.
208     * @param addr the address to get the offset of.
209     * @return the block offset.
210     */
211    int extractBlkOffset(Addr addr) const
212    {
213        return (addr & blkMask);
214    }
215
216    /**
217     * Find the cache block given set and way
218     * @param set The set of the block.
219     * @param way The way of the block.
220     * @return The cache block.
221     */
222    virtual CacheBlk *findBlockBySetAndWay(int set, int way) const = 0;
223
224    /**
225     * Limit the allocation for the cache ways.
226     * @param ways The maximum number of ways available for replacement.
227     */
228    virtual void setWayAllocationMax(int ways)
229    {
230        panic("This tag class does not implement way allocation limit!\n");
231    }
232
233    /**
234     * Get the way allocation mask limit.
235     * @return The maximum number of ways available for replacement.
236     */
237    virtual int getWayAllocationMax() const
238    {
239        panic("This tag class does not implement way allocation limit!\n");
240        return -1;
241    }
242
243    /**
244     * This function updates the tags when a block is invalidated but
245     * does not invalidate the block itself.
246     * @param blk The block to invalidate.
247     */
248    virtual void invalidate(CacheBlk *blk)
249    {
250        assert(blk);
251        assert(blk->isValid());
252        tagsInUse--;
253        occupancies[blk->srcMasterId]--;
254    }
255
256    /**
257     * Find replacement victim based on address.
258     *
259     * @param addr Address to find a victim for.
260     * @return Cache block to be replaced.
261     */
262    virtual CacheBlk* findVictim(Addr addr) = 0;
263
264    virtual CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) = 0;
265
266    virtual Addr extractTag(Addr addr) const = 0;
267
268    virtual void insertBlock(PacketPtr pkt, CacheBlk *blk) = 0;
269
270    /**
271     * Regenerate the block address.
272     *
273     * @param block The block.
274     * @return the block address.
275     */
276    virtual Addr regenerateBlkAddr(const CacheBlk* blk) const = 0;
277
278    virtual int extractSet(Addr addr) const = 0;
279
280    virtual void forEachBlk(CacheBlkVisitor &visitor) = 0;
281};
282
283class BaseTagsCallback : public Callback
284{
285    BaseTags *tags;
286  public:
287    BaseTagsCallback(BaseTags *t) : tags(t) {}
288    virtual void process() { tags->cleanupRefs(); };
289};
290
291class BaseTagsDumpCallback : public Callback
292{
293    BaseTags *tags;
294  public:
295    BaseTagsDumpCallback(BaseTags *t) : tags(t) {}
296    virtual void process() { tags->computeStats(); };
297};
298
299#endif //__MEM_CACHE_TAGS_BASE_HH__
300