base.hh revision 10815:169af9a2779f
1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 * Ron Dreslinski 42 */ 43 44/** 45 * @file 46 * Declaration of a common base class for cache tagstore objects. 47 */ 48 49#ifndef __BASE_TAGS_HH__ 50#define __BASE_TAGS_HH__ 51 52#include <string> 53 54#include "base/callback.hh" 55#include "base/statistics.hh" 56#include "mem/cache/blk.hh" 57#include "params/BaseTags.hh" 58#include "sim/clocked_object.hh" 59 60class BaseCache; 61 62/** 63 * A common base class of Cache tagstore objects. 64 */ 65class BaseTags : public ClockedObject 66{ 67 protected: 68 /** The block size of the cache. */ 69 const unsigned blkSize; 70 /** The size of the cache. */ 71 const unsigned size; 72 /** The access latency of the cache. */ 73 const Cycles accessLatency; 74 /** Pointer to the parent cache. */ 75 BaseCache *cache; 76 77 /** 78 * The number of tags that need to be touched to meet the warmup 79 * percentage. 80 */ 81 int warmupBound; 82 /** Marked true when the cache is warmed up. */ 83 bool warmedUp; 84 85 /** the number of blocks in the cache */ 86 unsigned numBlocks; 87 88 // Statistics 89 /** 90 * @addtogroup CacheStatistics 91 * @{ 92 */ 93 94 /** Number of replacements of valid blocks per thread. */ 95 Stats::Vector replacements; 96 /** Per cycle average of the number of tags that hold valid data. */ 97 Stats::Average tagsInUse; 98 99 /** The total number of references to a block before it is replaced. */ 100 Stats::Scalar totalRefs; 101 102 /** 103 * The number of reference counts sampled. This is different from 104 * replacements because we sample all the valid blocks when the simulator 105 * exits. 106 */ 107 Stats::Scalar sampledRefs; 108 109 /** 110 * Average number of references to a block before is was replaced. 111 * @todo This should change to an average stat once we have them. 112 */ 113 Stats::Formula avgRefs; 114 115 /** The cycle that the warmup percentage was hit. */ 116 Stats::Scalar warmupCycle; 117 118 /** Average occupancy of each requestor using the cache */ 119 Stats::AverageVector occupancies; 120 121 /** Average occ % of each requestor using the cache */ 122 Stats::Formula avgOccs; 123 124 /** Occupancy of each context/cpu using the cache */ 125 Stats::Vector occupanciesTaskId; 126 127 /** Occupancy of each context/cpu using the cache */ 128 Stats::Vector2d ageTaskId; 129 130 /** Occ % of each context/cpu using the cache */ 131 Stats::Formula percentOccsTaskId; 132 133 /** Number of tags consulted over all accesses. */ 134 Stats::Scalar tagAccesses; 135 /** Number of data blocks consulted over all accesses. */ 136 Stats::Scalar dataAccesses; 137 138 /** 139 * @} 140 */ 141 142 public: 143 typedef BaseTagsParams Params; 144 BaseTags(const Params *p); 145 146 /** 147 * Destructor. 148 */ 149 virtual ~BaseTags() {} 150 151 /** 152 * Set the parent cache back pointer. 153 * @param _cache Pointer to parent cache. 154 */ 155 void setCache(BaseCache *_cache); 156 157 /** 158 * Register local statistics. 159 */ 160 void regStats(); 161 162 /** 163 * Average in the reference count for valid blocks when the simulation 164 * exits. 165 */ 166 virtual void cleanupRefs() {} 167 168 /** 169 * Computes stats just prior to dump event 170 */ 171 virtual void computeStats() {} 172 173 /** 174 *iterated through all blocks and clear all locks 175 *Needed to clear all lock tracking at once 176 */ 177 virtual void clearLocks() {} 178 179 /** 180 * Print all tags used 181 */ 182 virtual std::string print() const = 0; 183 184 /** 185 * Find a block using the memory address 186 */ 187 virtual CacheBlk * findBlock(Addr addr, bool is_secure) const = 0; 188 189 /** 190 * Calculate the block offset of an address. 191 * @param addr the address to get the offset of. 192 * @return the block offset. 193 */ 194 int extractBlkOffset(Addr addr) const 195 { 196 return (addr & (Addr)(blkSize-1)); 197 } 198 199 virtual void invalidate(CacheBlk *blk) = 0; 200 201 virtual CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat, 202 int context_src) = 0; 203 204 virtual Addr extractTag(Addr addr) const = 0; 205 206 virtual void insertBlock(PacketPtr pkt, CacheBlk *blk) = 0; 207 208 virtual Addr regenerateBlkAddr(Addr tag, unsigned set) const = 0; 209 210 virtual CacheBlk* findVictim(Addr addr) = 0; 211 212 virtual int extractSet(Addr addr) const = 0; 213 214 virtual void forEachBlk(CacheBlkVisitor &visitor) = 0; 215}; 216 217class BaseTagsCallback : public Callback 218{ 219 BaseTags *tags; 220 public: 221 BaseTagsCallback(BaseTags *t) : tags(t) {} 222 virtual void process() { tags->cleanupRefs(); }; 223}; 224 225class BaseTagsDumpCallback : public Callback 226{ 227 BaseTags *tags; 228 public: 229 BaseTagsDumpCallback(BaseTags *t) : tags(t) {} 230 virtual void process() { tags->computeStats(); }; 231}; 232 233#endif //__BASE_TAGS_HH__ 234