base.hh revision 12553
12810SN/A/* 211870Snikos.nikoleris@arm.com * Copyright (c) 2012-2014,2016 ARM Limited 39347SAndreas.Sandberg@arm.com * All rights reserved. 49347SAndreas.Sandberg@arm.com * 59347SAndreas.Sandberg@arm.com * The license below extends only to copyright in the software and shall 69347SAndreas.Sandberg@arm.com * not be construed as granting a license to any other intellectual 79347SAndreas.Sandberg@arm.com * property including but not limited to intellectual property relating 89347SAndreas.Sandberg@arm.com * to a hardware implementation of the functionality of the software 99347SAndreas.Sandberg@arm.com * licensed hereunder. You may use the software subject to the license 109347SAndreas.Sandberg@arm.com * terms below provided that you ensure that this notice is replicated 119347SAndreas.Sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 129347SAndreas.Sandberg@arm.com * modified or unmodified, in source code or in binary form. 139347SAndreas.Sandberg@arm.com * 142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Erik Hallnor 412810SN/A * Ron Dreslinski 422810SN/A */ 432810SN/A 442810SN/A/** 452810SN/A * @file 462810SN/A * Declaration of a common base class for cache tagstore objects. 472810SN/A */ 482810SN/A 4912492Sodanrc@yahoo.com.br#ifndef __MEM_CACHE_TAGS_BASE_HH__ 5012492Sodanrc@yahoo.com.br#define __MEM_CACHE_TAGS_BASE_HH__ 512810SN/A 522810SN/A#include <string> 538229Snate@binkert.org 548229Snate@binkert.org#include "base/callback.hh" 552810SN/A#include "base/statistics.hh" 5610815Sdavid.guillen@arm.com#include "mem/cache/blk.hh" 579796Sprakash.ramrakhyani@arm.com#include "params/BaseTags.hh" 589796Sprakash.ramrakhyani@arm.com#include "sim/clocked_object.hh" 592810SN/A 602810SN/Aclass BaseCache; 612810SN/A 622810SN/A/** 632810SN/A * A common base class of Cache tagstore objects. 642810SN/A */ 659796Sprakash.ramrakhyani@arm.comclass BaseTags : public ClockedObject 662810SN/A{ 672810SN/A protected: 689796Sprakash.ramrakhyani@arm.com /** The block size of the cache. */ 699796Sprakash.ramrakhyani@arm.com const unsigned blkSize; 7011893Snikos.nikoleris@arm.com /** Mask out all bits that aren't part of the block offset. */ 7111893Snikos.nikoleris@arm.com const Addr blkMask; 729796Sprakash.ramrakhyani@arm.com /** The size of the cache. */ 739796Sprakash.ramrakhyani@arm.com const unsigned size; 7411722Ssophiane.senni@gmail.com /** The tag lookup latency of the cache. */ 7511722Ssophiane.senni@gmail.com const Cycles lookupLatency; 7611722Ssophiane.senni@gmail.com /** 7711722Ssophiane.senni@gmail.com * The total access latency of the cache. This latency 7811722Ssophiane.senni@gmail.com * is different depending on the cache access mode 7911722Ssophiane.senni@gmail.com * (parallel or sequential) 8011722Ssophiane.senni@gmail.com */ 8110693SMarco.Balboni@ARM.com const Cycles accessLatency; 822810SN/A /** Pointer to the parent cache. */ 832810SN/A BaseCache *cache; 842810SN/A 852810SN/A /** 862810SN/A * The number of tags that need to be touched to meet the warmup 872810SN/A * percentage. 882810SN/A */ 8912513Sodanrc@yahoo.com.br const unsigned warmupBound; 902810SN/A /** Marked true when the cache is warmed up. */ 912810SN/A bool warmedUp; 922810SN/A 936978SLisa.Hsu@amd.com /** the number of blocks in the cache */ 9412553Snikos.nikoleris@arm.com const unsigned numBlocks; 956978SLisa.Hsu@amd.com 962810SN/A // Statistics 972810SN/A /** 9812513Sodanrc@yahoo.com.br * TODO: It would be good if these stats were acquired after warmup. 992810SN/A * @addtogroup CacheStatistics 1002810SN/A * @{ 1012810SN/A */ 1022810SN/A 1032810SN/A /** Number of replacements of valid blocks per thread. */ 1045999Snate@binkert.org Stats::Vector replacements; 1052810SN/A /** Per cycle average of the number of tags that hold valid data. */ 1065999Snate@binkert.org Stats::Average tagsInUse; 1072810SN/A 1082810SN/A /** The total number of references to a block before it is replaced. */ 1095999Snate@binkert.org Stats::Scalar totalRefs; 1102810SN/A 1112810SN/A /** 1122810SN/A * The number of reference counts sampled. This is different from 1132810SN/A * replacements because we sample all the valid blocks when the simulator 1142810SN/A * exits. 1152810SN/A */ 1165999Snate@binkert.org Stats::Scalar sampledRefs; 1172810SN/A 1182810SN/A /** 1192810SN/A * Average number of references to a block before is was replaced. 1202810SN/A * @todo This should change to an average stat once we have them. 1212810SN/A */ 1222810SN/A Stats::Formula avgRefs; 1232810SN/A 12412513Sodanrc@yahoo.com.br /** The cycle that the warmup percentage was hit. 0 on failure. */ 1255999Snate@binkert.org Stats::Scalar warmupCycle; 1266978SLisa.Hsu@amd.com 1278833Sdam.sunwoo@arm.com /** Average occupancy of each requestor using the cache */ 1286978SLisa.Hsu@amd.com Stats::AverageVector occupancies; 1296978SLisa.Hsu@amd.com 1308833Sdam.sunwoo@arm.com /** Average occ % of each requestor using the cache */ 1316978SLisa.Hsu@amd.com Stats::Formula avgOccs; 1326978SLisa.Hsu@amd.com 13310024Sdam.sunwoo@arm.com /** Occupancy of each context/cpu using the cache */ 13410024Sdam.sunwoo@arm.com Stats::Vector occupanciesTaskId; 13510024Sdam.sunwoo@arm.com 13610024Sdam.sunwoo@arm.com /** Occupancy of each context/cpu using the cache */ 13710024Sdam.sunwoo@arm.com Stats::Vector2d ageTaskId; 13810024Sdam.sunwoo@arm.com 13910024Sdam.sunwoo@arm.com /** Occ % of each context/cpu using the cache */ 14010024Sdam.sunwoo@arm.com Stats::Formula percentOccsTaskId; 14110024Sdam.sunwoo@arm.com 14210025Stimothy.jones@arm.com /** Number of tags consulted over all accesses. */ 14310025Stimothy.jones@arm.com Stats::Scalar tagAccesses; 14410025Stimothy.jones@arm.com /** Number of data blocks consulted over all accesses. */ 14510025Stimothy.jones@arm.com Stats::Scalar dataAccesses; 14610025Stimothy.jones@arm.com 1472810SN/A /** 1482810SN/A * @} 1492810SN/A */ 1502810SN/A 1512810SN/A public: 1529796Sprakash.ramrakhyani@arm.com typedef BaseTagsParams Params; 1539796Sprakash.ramrakhyani@arm.com BaseTags(const Params *p); 1542810SN/A 1552810SN/A /** 1562810SN/A * Destructor. 1572810SN/A */ 1582810SN/A virtual ~BaseTags() {} 1592810SN/A 1602810SN/A /** 1619796Sprakash.ramrakhyani@arm.com * Set the parent cache back pointer. 1622810SN/A * @param _cache Pointer to parent cache. 1632810SN/A */ 1642810SN/A void setCache(BaseCache *_cache); 1652810SN/A 1662810SN/A /** 1679796Sprakash.ramrakhyani@arm.com * Register local statistics. 1682810SN/A */ 1699796Sprakash.ramrakhyani@arm.com void regStats(); 1702810SN/A 1712810SN/A /** 1722810SN/A * Average in the reference count for valid blocks when the simulation 1732810SN/A * exits. 1742810SN/A */ 1752810SN/A virtual void cleanupRefs() {} 1767612SGene.Wu@arm.com 1777612SGene.Wu@arm.com /** 17810024Sdam.sunwoo@arm.com * Computes stats just prior to dump event 17910024Sdam.sunwoo@arm.com */ 18010024Sdam.sunwoo@arm.com virtual void computeStats() {} 18110024Sdam.sunwoo@arm.com 18210024Sdam.sunwoo@arm.com /** 1839663Suri.wiener@arm.com * Print all tags used 1849663Suri.wiener@arm.com */ 1859663Suri.wiener@arm.com virtual std::string print() const = 0; 18610815Sdavid.guillen@arm.com 18710815Sdavid.guillen@arm.com /** 18810815Sdavid.guillen@arm.com * Find a block using the memory address 18910815Sdavid.guillen@arm.com */ 19010815Sdavid.guillen@arm.com virtual CacheBlk * findBlock(Addr addr, bool is_secure) const = 0; 19110815Sdavid.guillen@arm.com 19210815Sdavid.guillen@arm.com /** 19311893Snikos.nikoleris@arm.com * Align an address to the block size. 19411893Snikos.nikoleris@arm.com * @param addr the address to align. 19511893Snikos.nikoleris@arm.com * @return The block address. 19611893Snikos.nikoleris@arm.com */ 19711893Snikos.nikoleris@arm.com Addr blkAlign(Addr addr) const 19811893Snikos.nikoleris@arm.com { 19911893Snikos.nikoleris@arm.com return addr & ~blkMask; 20011893Snikos.nikoleris@arm.com } 20111893Snikos.nikoleris@arm.com 20211893Snikos.nikoleris@arm.com /** 20310815Sdavid.guillen@arm.com * Calculate the block offset of an address. 20410815Sdavid.guillen@arm.com * @param addr the address to get the offset of. 20510815Sdavid.guillen@arm.com * @return the block offset. 20610815Sdavid.guillen@arm.com */ 20710815Sdavid.guillen@arm.com int extractBlkOffset(Addr addr) const 20810815Sdavid.guillen@arm.com { 20911893Snikos.nikoleris@arm.com return (addr & blkMask); 21010815Sdavid.guillen@arm.com } 21110815Sdavid.guillen@arm.com 21210941Sdavid.guillen@arm.com /** 21310941Sdavid.guillen@arm.com * Find the cache block given set and way 21410941Sdavid.guillen@arm.com * @param set The set of the block. 21510941Sdavid.guillen@arm.com * @param way The way of the block. 21610941Sdavid.guillen@arm.com * @return The cache block. 21710941Sdavid.guillen@arm.com */ 21810941Sdavid.guillen@arm.com virtual CacheBlk *findBlockBySetAndWay(int set, int way) const = 0; 21910941Sdavid.guillen@arm.com 22010941Sdavid.guillen@arm.com /** 22110941Sdavid.guillen@arm.com * Limit the allocation for the cache ways. 22210941Sdavid.guillen@arm.com * @param ways The maximum number of ways available for replacement. 22310941Sdavid.guillen@arm.com */ 22410941Sdavid.guillen@arm.com virtual void setWayAllocationMax(int ways) 22510941Sdavid.guillen@arm.com { 22610941Sdavid.guillen@arm.com panic("This tag class does not implement way allocation limit!\n"); 22710941Sdavid.guillen@arm.com } 22810941Sdavid.guillen@arm.com 22910941Sdavid.guillen@arm.com /** 23010941Sdavid.guillen@arm.com * Get the way allocation mask limit. 23110941Sdavid.guillen@arm.com * @return The maximum number of ways available for replacement. 23210941Sdavid.guillen@arm.com */ 23310941Sdavid.guillen@arm.com virtual int getWayAllocationMax() const 23410941Sdavid.guillen@arm.com { 23510941Sdavid.guillen@arm.com panic("This tag class does not implement way allocation limit!\n"); 23610941Sdavid.guillen@arm.com return -1; 23710941Sdavid.guillen@arm.com } 23810941Sdavid.guillen@arm.com 23910815Sdavid.guillen@arm.com virtual void invalidate(CacheBlk *blk) = 0; 24010815Sdavid.guillen@arm.com 24111870Snikos.nikoleris@arm.com virtual CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) = 0; 24210815Sdavid.guillen@arm.com 24310815Sdavid.guillen@arm.com virtual Addr extractTag(Addr addr) const = 0; 24410815Sdavid.guillen@arm.com 24510815Sdavid.guillen@arm.com virtual void insertBlock(PacketPtr pkt, CacheBlk *blk) = 0; 24610815Sdavid.guillen@arm.com 24710815Sdavid.guillen@arm.com virtual Addr regenerateBlkAddr(Addr tag, unsigned set) const = 0; 24810815Sdavid.guillen@arm.com 24910815Sdavid.guillen@arm.com virtual CacheBlk* findVictim(Addr addr) = 0; 25010815Sdavid.guillen@arm.com 25110815Sdavid.guillen@arm.com virtual int extractSet(Addr addr) const = 0; 25210815Sdavid.guillen@arm.com 25310815Sdavid.guillen@arm.com virtual void forEachBlk(CacheBlkVisitor &visitor) = 0; 2542810SN/A}; 2552810SN/A 2562810SN/Aclass BaseTagsCallback : public Callback 2572810SN/A{ 2582810SN/A BaseTags *tags; 2592810SN/A public: 2602810SN/A BaseTagsCallback(BaseTags *t) : tags(t) {} 2612810SN/A virtual void process() { tags->cleanupRefs(); }; 2622810SN/A}; 2632810SN/A 26410024Sdam.sunwoo@arm.comclass BaseTagsDumpCallback : public Callback 26510024Sdam.sunwoo@arm.com{ 26610024Sdam.sunwoo@arm.com BaseTags *tags; 26710024Sdam.sunwoo@arm.com public: 26810024Sdam.sunwoo@arm.com BaseTagsDumpCallback(BaseTags *t) : tags(t) {} 26910024Sdam.sunwoo@arm.com virtual void process() { tags->computeStats(); }; 27010024Sdam.sunwoo@arm.com}; 27110024Sdam.sunwoo@arm.com 27212492Sodanrc@yahoo.com.br#endif //__MEM_CACHE_TAGS_BASE_HH__ 273