Tags.py revision 10025:fdf737112e46 
1# Copyright (c) 2012-2013 ARM Limited
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36# Authors: Prakash Ramrakhyani
37
38from m5.params import *
39from m5.proxy import *
40from ClockedObject import ClockedObject
41
42class BaseTags(ClockedObject):
43    type = 'BaseTags'
44    abstract = True
45    cxx_header = "mem/cache/tags/base.hh"
46    # Get the size from the parent (cache)
47    size = Param.MemorySize(Parent.size, "capacity in bytes")
48
49    # Get the block size from the parent (system)
50    block_size = Param.Int(Parent.cache_line_size, "block size in bytes")
51
52    # Get the hit latency from the parent (cache)
53    hit_latency = Param.Cycles(Parent.hit_latency,
54                               "The hit latency for this cache")
55
56class LRU(BaseTags):
57    type = 'LRU'
58    cxx_class = 'LRU'
59    cxx_header = "mem/cache/tags/lru.hh"
60    assoc = Param.Int(Parent.assoc, "associativity")
61    sequential_access = Param.Bool(Parent.sequential_access,
62        "Whether to access tags and data sequentially")
63
64class FALRU(BaseTags):
65    type = 'FALRU'
66    cxx_class = 'FALRU'
67    cxx_header = "mem/cache/tags/fa_lru.hh"
68