stride.hh revision 13422
1/* 2 * Copyright (c) 2012-2013, 2015 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ron Dreslinski 41 */ 42 43/** 44 * @file 45 * Describes a strided prefetcher. 46 */ 47 48#ifndef __MEM_CACHE_PREFETCH_STRIDE_HH__ 49#define __MEM_CACHE_PREFETCH_STRIDE_HH__ 50 51#include <string> 52#include <unordered_map> 53 54#include "base/types.hh" 55#include "mem/cache/prefetch/queued.hh" 56#include "mem/packet.hh" 57 58struct StridePrefetcherParams; 59 60class StridePrefetcher : public QueuedPrefetcher 61{ 62 protected: 63 const int maxConf; 64 const int threshConf; 65 const int minConf; 66 const int startConf; 67 68 const int pcTableAssoc; 69 const int pcTableSets; 70 71 const bool useMasterId; 72 73 const int degree; 74 75 struct StrideEntry 76 { 77 StrideEntry() : instAddr(0), lastAddr(0), isSecure(false), stride(0), 78 confidence(0) 79 { } 80 81 Addr instAddr; 82 Addr lastAddr; 83 bool isSecure; 84 int stride; 85 int confidence; 86 }; 87 88 class PCTable 89 { 90 public: 91 PCTable(int assoc, int sets, const std::string name) : 92 pcTableAssoc(assoc), pcTableSets(sets), _name(name) {} 93 StrideEntry** operator[] (int context) { 94 auto it = entries.find(context); 95 if (it != entries.end()) 96 return it->second; 97 98 return allocateNewContext(context); 99 } 100 101 ~PCTable(); 102 private: 103 const std::string name() {return _name; } 104 const int pcTableAssoc; 105 const int pcTableSets; 106 const std::string _name; 107 std::unordered_map<int, StrideEntry**> entries; 108 109 StrideEntry** allocateNewContext(int context); 110 }; 111 PCTable pcTable; 112 113 bool pcTableHit(Addr pc, bool is_secure, int master_id, StrideEntry* &entry); 114 StrideEntry* pcTableVictim(Addr pc, int master_id); 115 116 Addr pcHash(Addr pc) const; 117 public: 118 119 StridePrefetcher(const StridePrefetcherParams *p); 120 121 void calculatePrefetch(const PacketPtr &pkt, 122 std::vector<AddrPriority> &addresses) override; 123}; 124 125#endif // __MEM_CACHE_PREFETCH_STRIDE_HH__ 126