stride.hh revision 5543
12810SN/A/*
22810SN/A * Copyright (c) 2005 The Regents of The University of Michigan
32810SN/A * All rights reserved.
42810SN/A *
52810SN/A * Redistribution and use in source and binary forms, with or without
62810SN/A * modification, are permitted provided that the following conditions are
72810SN/A * met: redistributions of source code must retain the above copyright
82810SN/A * notice, this list of conditions and the following disclaimer;
92810SN/A * redistributions in binary form must reproduce the above copyright
102810SN/A * notice, this list of conditions and the following disclaimer in the
112810SN/A * documentation and/or other materials provided with the distribution;
122810SN/A * neither the name of the copyright holders nor the names of its
132810SN/A * contributors may be used to endorse or promote products derived from
142810SN/A * this software without specific prior written permission.
152810SN/A *
162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272810SN/A *
282810SN/A * Authors: Ron Dreslinski
292810SN/A */
302810SN/A
312810SN/A/**
322810SN/A * @file
333861SN/A * Describes a strided prefetcher.
342810SN/A */
352810SN/A
362810SN/A#ifndef __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__
372810SN/A#define __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__
382810SN/A
395338Sstever@gmail.com#include "mem/cache/prefetch/base.hh"
402810SN/A
413861SN/Aclass StridePrefetcher : public BasePrefetcher
422810SN/A{
432810SN/A  protected:
442810SN/A
452810SN/A    class strideEntry
462810SN/A    {
472810SN/A      public:
482810SN/A        Addr IAddr;
492810SN/A        Addr MAddr;
502810SN/A        int stride;
512810SN/A        int64_t confidence;
522810SN/A
535543Ssaidi@eecs.umich.edu/*      bool operator < (strideEntry a,strideEntry b)
542810SN/A        {
552810SN/A            if (a.confidence == b.confidence) {
562810SN/A                return true; //??????
572810SN/A            }
582810SN/A            else return a.confidence < b.confidence;
592810SN/A            }*/
602810SN/A    };
612810SN/A    Addr* lastMissAddr[64/*MAX_CPUS*/];
622810SN/A
632810SN/A    std::list<strideEntry*> table[64/*MAX_CPUS*/];
642810SN/A    Tick latency;
652810SN/A    int degree;
662810SN/A    bool useCPUId;
672810SN/A
682810SN/A
692810SN/A  public:
702810SN/A
715034SN/A    StridePrefetcher(const BaseCacheParams *p)
725034SN/A        : BasePrefetcher(p), latency(p->prefetch_latency),
735034SN/A          degree(p->prefetch_degree), useCPUId(p->prefetch_use_cpu_id)
742810SN/A    {
752810SN/A    }
762810SN/A
772810SN/A    ~StridePrefetcher() {}
782810SN/A
793349SN/A    void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
803861SN/A                           std::list<Tick> &delays);
812810SN/A};
822810SN/A
832810SN/A#endif // __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__
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