stride.hh revision 2810
16691Stjones1@inf.ed.ac.uk/* 26691Stjones1@inf.ed.ac.uk * Copyright (c) 2005 The Regents of The University of Michigan 36691Stjones1@inf.ed.ac.uk * All rights reserved. 46691Stjones1@inf.ed.ac.uk * 56691Stjones1@inf.ed.ac.uk * Redistribution and use in source and binary forms, with or without 66691Stjones1@inf.ed.ac.uk * modification, are permitted provided that the following conditions are 76691Stjones1@inf.ed.ac.uk * met: redistributions of source code must retain the above copyright 86691Stjones1@inf.ed.ac.uk * notice, this list of conditions and the following disclaimer; 96691Stjones1@inf.ed.ac.uk * redistributions in binary form must reproduce the above copyright 106691Stjones1@inf.ed.ac.uk * notice, this list of conditions and the following disclaimer in the 116691Stjones1@inf.ed.ac.uk * documentation and/or other materials provided with the distribution; 126691Stjones1@inf.ed.ac.uk * neither the name of the copyright holders nor the names of its 136691Stjones1@inf.ed.ac.uk * contributors may be used to endorse or promote products derived from 146691Stjones1@inf.ed.ac.uk * this software without specific prior written permission. 156691Stjones1@inf.ed.ac.uk * 166691Stjones1@inf.ed.ac.uk * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176691Stjones1@inf.ed.ac.uk * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186691Stjones1@inf.ed.ac.uk * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196691Stjones1@inf.ed.ac.uk * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206691Stjones1@inf.ed.ac.uk * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216691Stjones1@inf.ed.ac.uk * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226691Stjones1@inf.ed.ac.uk * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236691Stjones1@inf.ed.ac.uk * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246691Stjones1@inf.ed.ac.uk * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256691Stjones1@inf.ed.ac.uk * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266691Stjones1@inf.ed.ac.uk * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276691Stjones1@inf.ed.ac.uk * 286691Stjones1@inf.ed.ac.uk * Authors: Ron Dreslinski 296691Stjones1@inf.ed.ac.uk */ 306691Stjones1@inf.ed.ac.uk 316691Stjones1@inf.ed.ac.uk/** 326691Stjones1@inf.ed.ac.uk * @file 336691Stjones1@inf.ed.ac.uk * Describes a strided prefetcher based on template policies. 346691Stjones1@inf.ed.ac.uk */ 356691Stjones1@inf.ed.ac.uk 366691Stjones1@inf.ed.ac.uk#ifndef __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__ 376691Stjones1@inf.ed.ac.uk#define __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__ 386691Stjones1@inf.ed.ac.uk 396691Stjones1@inf.ed.ac.uk#include "base/misc.hh" // fatal, panic, and warn 406691Stjones1@inf.ed.ac.uk 416691Stjones1@inf.ed.ac.uk#include "mem/cache/prefetch/prefetcher.hh" 4210687SAndreas.Sandberg@ARM.com 436691Stjones1@inf.ed.ac.uk/** 448229Snate@binkert.org * A template-policy based cache. The behavior of the cache can be altered by 456691Stjones1@inf.ed.ac.uk * supplying different template policies. TagStore handles all tag and data 466691Stjones1@inf.ed.ac.uk * storage @sa TagStore. Buffering handles all misses and writes/writebacks 476691Stjones1@inf.ed.ac.uk * @sa MissQueue. Coherence handles all coherence policy details @sa 486691Stjones1@inf.ed.ac.uk * UniCoherence, SimpleMultiCoherence. 496691Stjones1@inf.ed.ac.uk */ 506691Stjones1@inf.ed.ac.uktemplate <class TagStore, class Buffering> 516691Stjones1@inf.ed.ac.ukclass StridePrefetcher : public Prefetcher<TagStore, Buffering> 526691Stjones1@inf.ed.ac.uk{ 536691Stjones1@inf.ed.ac.uk protected: 546691Stjones1@inf.ed.ac.uk 556691Stjones1@inf.ed.ac.uk Buffering* mq; 566691Stjones1@inf.ed.ac.uk TagStore* tags; 576691Stjones1@inf.ed.ac.uk 586691Stjones1@inf.ed.ac.uk class strideEntry 596691Stjones1@inf.ed.ac.uk { 606691Stjones1@inf.ed.ac.uk public: 616691Stjones1@inf.ed.ac.uk Addr IAddr; 626691Stjones1@inf.ed.ac.uk Addr MAddr; 636691Stjones1@inf.ed.ac.uk int stride; 646691Stjones1@inf.ed.ac.uk int64_t confidence; 6510558Salexandru.dutu@amd.com 6610558Salexandru.dutu@amd.com/* bool operator < (strideEntry a,strideEntry b) 676691Stjones1@inf.ed.ac.uk { 686691Stjones1@inf.ed.ac.uk if (a.confidence == b.confidence) { 6910558Salexandru.dutu@amd.com return true; //?????? 7010558Salexandru.dutu@amd.com } 7110558Salexandru.dutu@amd.com else return a.confidence < b.confidence; 726691Stjones1@inf.ed.ac.uk }*/ 736691Stjones1@inf.ed.ac.uk }; 746691Stjones1@inf.ed.ac.uk Addr* lastMissAddr[64/*MAX_CPUS*/]; 756691Stjones1@inf.ed.ac.uk 766691Stjones1@inf.ed.ac.uk std::list<strideEntry*> table[64/*MAX_CPUS*/]; 776691Stjones1@inf.ed.ac.uk Tick latency; 786691Stjones1@inf.ed.ac.uk int degree; 796691Stjones1@inf.ed.ac.uk bool useCPUId; 806691Stjones1@inf.ed.ac.uk 816691Stjones1@inf.ed.ac.uk 826691Stjones1@inf.ed.ac.uk public: 836691Stjones1@inf.ed.ac.uk 846691Stjones1@inf.ed.ac.uk StridePrefetcher(int size, bool pageStop, bool serialSquash, 856691Stjones1@inf.ed.ac.uk bool cacheCheckPush, bool onlyData, 866691Stjones1@inf.ed.ac.uk Tick latency, int degree, bool useCPUId) 8710905Sandreas.sandberg@arm.com :Prefetcher<TagStore, Buffering>(size, pageStop, serialSquash, 886691Stjones1@inf.ed.ac.uk cacheCheckPush, onlyData), 896691Stjones1@inf.ed.ac.uk latency(latency), degree(degree), useCPUId(useCPUId) 906691Stjones1@inf.ed.ac.uk { 916691Stjones1@inf.ed.ac.uk } 926691Stjones1@inf.ed.ac.uk 9310905Sandreas.sandberg@arm.com ~StridePrefetcher() {} 946691Stjones1@inf.ed.ac.uk 956691Stjones1@inf.ed.ac.uk void calculatePrefetch(Packet * &pkt, std::list<Addr> &addresses, 966691Stjones1@inf.ed.ac.uk std::list<Tick> &delays) 976691Stjones1@inf.ed.ac.uk { 986691Stjones1@inf.ed.ac.uk// Addr blkAddr = pkt->paddr & ~(Addr)(this->blkSize-1); 996691Stjones1@inf.ed.ac.uk int cpuID = pkt->cpu_num; 1006691Stjones1@inf.ed.ac.uk if (!useCPUId) cpuID = 0; 1016691Stjones1@inf.ed.ac.uk 1026691Stjones1@inf.ed.ac.uk /* Scan Table for IAddr Match */ 1036691Stjones1@inf.ed.ac.uk/* std::list<strideEntry*>::iterator iter; 1046691Stjones1@inf.ed.ac.uk for (iter=table[cpuID].begin(); 1056691Stjones1@inf.ed.ac.uk iter !=table[cpuID].end(); 1066691Stjones1@inf.ed.ac.uk iter++) { 1076691Stjones1@inf.ed.ac.uk if ((*iter)->IAddr == pkt->pc) break; 1086691Stjones1@inf.ed.ac.uk } 1096691Stjones1@inf.ed.ac.uk 1106691Stjones1@inf.ed.ac.uk if (iter != table[cpuID].end()) { 1116691Stjones1@inf.ed.ac.uk //Hit in table 1126691Stjones1@inf.ed.ac.uk 1136691Stjones1@inf.ed.ac.uk int newStride = blkAddr - (*iter)->MAddr; 1146691Stjones1@inf.ed.ac.uk if (newStride == (*iter)->stride) { 1156691Stjones1@inf.ed.ac.uk (*iter)->confidence++; 1166691Stjones1@inf.ed.ac.uk } 1176691Stjones1@inf.ed.ac.uk else { 1186691Stjones1@inf.ed.ac.uk (*iter)->stride = newStride; 1196691Stjones1@inf.ed.ac.uk (*iter)->confidence--; 1206691Stjones1@inf.ed.ac.uk } 1216691Stjones1@inf.ed.ac.uk 1226691Stjones1@inf.ed.ac.uk (*iter)->MAddr = blkAddr; 1236691Stjones1@inf.ed.ac.uk 1246691Stjones1@inf.ed.ac.uk for (int d=1; d <= degree; d++) { 1256691Stjones1@inf.ed.ac.uk Addr newAddr = blkAddr + d * newStride; 1266691Stjones1@inf.ed.ac.uk if (this->pageStop && 1276691Stjones1@inf.ed.ac.uk (blkAddr & ~(TheISA::VMPageSize - 1)) != 1286691Stjones1@inf.ed.ac.uk (newAddr & ~(TheISA::VMPageSize - 1))) 1296691Stjones1@inf.ed.ac.uk { 1306691Stjones1@inf.ed.ac.uk //Spanned the page, so now stop 1316691Stjones1@inf.ed.ac.uk this->pfSpanPage += degree - d + 1; 1326691Stjones1@inf.ed.ac.uk return; 1336691Stjones1@inf.ed.ac.uk } 1346691Stjones1@inf.ed.ac.uk else 1356691Stjones1@inf.ed.ac.uk { 13611347Sandreas.hansson@arm.com addresses.push_back(newAddr); 13710194SGeoffrey.Blake@arm.com delays.push_back(latency); 1386691Stjones1@inf.ed.ac.uk } 1396691Stjones1@inf.ed.ac.uk } 1406691Stjones1@inf.ed.ac.uk } 1416691Stjones1@inf.ed.ac.uk else { 1426691Stjones1@inf.ed.ac.uk //Miss in table 1436691Stjones1@inf.ed.ac.uk //Find lowest confidence and replace 1446691Stjones1@inf.ed.ac.uk 1456691Stjones1@inf.ed.ac.uk } 1466691Stjones1@inf.ed.ac.uk*/ } 1476691Stjones1@inf.ed.ac.uk}; 1486691Stjones1@inf.ed.ac.uk 1496691Stjones1@inf.ed.ac.uk#endif // __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__ 1506691Stjones1@inf.ed.ac.uk