stride.cc revision 8832
12810SN/A/* 22810SN/A * Copyright (c) 2005 The Regents of The University of Michigan 32810SN/A * All rights reserved. 42810SN/A * 52810SN/A * Redistribution and use in source and binary forms, with or without 62810SN/A * modification, are permitted provided that the following conditions are 72810SN/A * met: redistributions of source code must retain the above copyright 82810SN/A * notice, this list of conditions and the following disclaimer; 92810SN/A * redistributions in binary form must reproduce the above copyright 102810SN/A * notice, this list of conditions and the following disclaimer in the 112810SN/A * documentation and/or other materials provided with the distribution; 122810SN/A * neither the name of the copyright holders nor the names of its 132810SN/A * contributors may be used to endorse or promote products derived from 142810SN/A * this software without specific prior written permission. 152810SN/A * 162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810SN/A * 282810SN/A * Authors: Ron Dreslinski 292810SN/A * Steve Reinhardt 302810SN/A */ 312810SN/A 322810SN/A/** 332810SN/A * @file 342810SN/A * Stride Prefetcher template instantiations. 352810SN/A */ 362810SN/A 375875Ssteve.reinhardt@amd.com#include "base/trace.hh" 388232Snate@binkert.org#include "debug/HWPrefetch.hh" 395338Sstever@gmail.com#include "mem/cache/prefetch/stride.hh" 402810SN/A 413861SN/Avoid 423861SN/AStridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses, 433861SN/A std::list<Tick> &delays) 443861SN/A{ 455875Ssteve.reinhardt@amd.com if (!pkt->req->hasPC()) { 465875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, "ignoring request with no PC"); 475875Ssteve.reinhardt@amd.com return; 485875Ssteve.reinhardt@amd.com } 492810SN/A 505875Ssteve.reinhardt@amd.com Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1); 518832SAli.Saidi@ARM.com MasterID master_id = useMasterId ? pkt->req->masterId() : 0; 525875Ssteve.reinhardt@amd.com Addr pc = pkt->req->getPC(); 538832SAli.Saidi@ARM.com assert(master_id < Max_Contexts); 548832SAli.Saidi@ARM.com std::list<StrideEntry*> &tab = table[master_id]; 552810SN/A 565875Ssteve.reinhardt@amd.com /* Scan Table for instAddr Match */ 575875Ssteve.reinhardt@amd.com std::list<StrideEntry*>::iterator iter; 585875Ssteve.reinhardt@amd.com for (iter = tab.begin(); iter != tab.end(); iter++) { 595875Ssteve.reinhardt@amd.com if ((*iter)->instAddr == pc) 605875Ssteve.reinhardt@amd.com break; 615875Ssteve.reinhardt@amd.com } 623861SN/A 635875Ssteve.reinhardt@amd.com if (iter != tab.end()) { 645875Ssteve.reinhardt@amd.com // Hit in table 653861SN/A 665875Ssteve.reinhardt@amd.com int new_stride = blk_addr - (*iter)->missAddr; 675875Ssteve.reinhardt@amd.com bool stride_match = (new_stride == (*iter)->stride); 683861SN/A 695875Ssteve.reinhardt@amd.com if (stride_match && new_stride != 0) { 705875Ssteve.reinhardt@amd.com if ((*iter)->confidence < Max_Conf) 715875Ssteve.reinhardt@amd.com (*iter)->confidence++; 725875Ssteve.reinhardt@amd.com } else { 735875Ssteve.reinhardt@amd.com (*iter)->stride = new_stride; 745875Ssteve.reinhardt@amd.com if ((*iter)->confidence > Min_Conf) 755875Ssteve.reinhardt@amd.com (*iter)->confidence = 0; 765875Ssteve.reinhardt@amd.com } 773861SN/A 785875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, "hit: PC %x blk_addr %x stride %d (%s), conf %d\n", 795875Ssteve.reinhardt@amd.com pc, blk_addr, new_stride, stride_match ? "match" : "change", 805875Ssteve.reinhardt@amd.com (*iter)->confidence); 815875Ssteve.reinhardt@amd.com 825875Ssteve.reinhardt@amd.com (*iter)->missAddr = blk_addr; 835875Ssteve.reinhardt@amd.com 845875Ssteve.reinhardt@amd.com if ((*iter)->confidence <= 0) 855875Ssteve.reinhardt@amd.com return; 865875Ssteve.reinhardt@amd.com 875875Ssteve.reinhardt@amd.com for (int d = 1; d <= degree; d++) { 885875Ssteve.reinhardt@amd.com Addr new_addr = blk_addr + d * new_stride; 895875Ssteve.reinhardt@amd.com if (pageStop && !samePage(blk_addr, new_addr)) { 905875Ssteve.reinhardt@amd.com // Spanned the page, so now stop 915875Ssteve.reinhardt@amd.com pfSpanPage += degree - d + 1; 925875Ssteve.reinhardt@amd.com return; 935875Ssteve.reinhardt@amd.com } else { 945875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, " queuing prefetch to %x @ %d\n", 955875Ssteve.reinhardt@amd.com new_addr, latency); 965875Ssteve.reinhardt@amd.com addresses.push_back(new_addr); 975875Ssteve.reinhardt@amd.com delays.push_back(latency); 985875Ssteve.reinhardt@amd.com } 995875Ssteve.reinhardt@amd.com } 1005875Ssteve.reinhardt@amd.com } else { 1015875Ssteve.reinhardt@amd.com // Miss in table 1025875Ssteve.reinhardt@amd.com // Find lowest confidence and replace 1035875Ssteve.reinhardt@amd.com 1045875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, "miss: PC %x blk_addr %x\n", pc, blk_addr); 1055875Ssteve.reinhardt@amd.com 1065875Ssteve.reinhardt@amd.com if (tab.size() >= 256) { //set default table size is 256 1075875Ssteve.reinhardt@amd.com std::list<StrideEntry*>::iterator min_pos = tab.begin(); 1085875Ssteve.reinhardt@amd.com int min_conf = (*min_pos)->confidence; 1095875Ssteve.reinhardt@amd.com for (iter = min_pos, ++iter; iter != tab.end(); ++iter) { 1105875Ssteve.reinhardt@amd.com if ((*iter)->confidence < min_conf){ 1115875Ssteve.reinhardt@amd.com min_pos = iter; 1125875Ssteve.reinhardt@amd.com min_conf = (*iter)->confidence; 1135875Ssteve.reinhardt@amd.com } 1145875Ssteve.reinhardt@amd.com } 1155875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, " replacing PC %x\n", (*min_pos)->instAddr); 1168509SAli.Saidi@ARM.com 1178509SAli.Saidi@ARM.com // free entry and delete it 1188509SAli.Saidi@ARM.com delete *min_pos; 1195875Ssteve.reinhardt@amd.com tab.erase(min_pos); 1205875Ssteve.reinhardt@amd.com } 1215875Ssteve.reinhardt@amd.com 1225875Ssteve.reinhardt@amd.com StrideEntry *new_entry = new StrideEntry; 1235875Ssteve.reinhardt@amd.com new_entry->instAddr = pc; 1245875Ssteve.reinhardt@amd.com new_entry->missAddr = blk_addr; 1255875Ssteve.reinhardt@amd.com new_entry->stride = 0; 1265875Ssteve.reinhardt@amd.com new_entry->confidence = 0; 1275875Ssteve.reinhardt@amd.com tab.push_back(new_entry); 1285875Ssteve.reinhardt@amd.com } 1293861SN/A} 1308831Smrinmoy.ghosh@arm.com 1318831Smrinmoy.ghosh@arm.com 1328831Smrinmoy.ghosh@arm.comStridePrefetcher* 1338831Smrinmoy.ghosh@arm.comStridePrefetcherParams::create() 1348831Smrinmoy.ghosh@arm.com{ 1358831Smrinmoy.ghosh@arm.com return new StridePrefetcher(this); 1368831Smrinmoy.ghosh@arm.com} 137