base.hh revision 9546:ac0c18d738ce 
1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 */
42
43/**
44 * @file
45 * Miss and writeback queue declarations.
46 */
47
48#ifndef __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
49#define __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
50
51#include <list>
52
53#include "base/statistics.hh"
54#include "mem/packet.hh"
55#include "params/BaseCache.hh"
56#include "sim/clocked_object.hh"
57
58class BaseCache;
59
60class BasePrefetcher : public ClockedObject
61{
62  protected:
63
64    /** A deferred packet, buffered to transmit later. */
65    class DeferredPacket {
66      public:
67        Tick tick;      ///< The tick when the packet is ready to transmit
68        PacketPtr pkt;  ///< Pointer to the packet to transmit
69        DeferredPacket(Tick t, PacketPtr p)
70            : tick(t), pkt(p)
71        {}
72    };
73
74    /** The Prefetch Queue. */
75    std::list<DeferredPacket> pf;
76
77    // PARAMETERS
78
79    /** The number of MSHRs in the Prefetch Queue. */
80    const unsigned size;
81
82    /** Pointr to the parent cache. */
83    BaseCache* cache;
84
85    /** The block size of the parent cache. */
86    int blkSize;
87
88    /** The latency before a prefetch is issued */
89    const Cycles latency;
90
91    /** The number of prefetches to issue */
92    unsigned degree;
93
94    /** If patterns should be found per context id */
95    bool useMasterId;
96    /** Do we prefetch across page boundaries. */
97    bool pageStop;
98
99    /** Do we remove prefetches with later times than a new miss.*/
100    bool serialSquash;
101
102    /** Do we prefetch on only data reads, or on inst reads as well. */
103    bool onlyData;
104
105    /** System we belong to */
106    System* system;
107
108    /** Request id for prefetches */
109    MasterID masterId;
110
111  public:
112
113    Stats::Scalar pfIdentified;
114    Stats::Scalar pfMSHRHit;
115    Stats::Scalar pfCacheHit;
116    Stats::Scalar pfBufferHit;
117    Stats::Scalar pfRemovedFull;
118    Stats::Scalar pfRemovedMSHR;
119    Stats::Scalar pfIssued;
120    Stats::Scalar pfSpanPage;
121    Stats::Scalar pfSquashed;
122
123    void regStats();
124
125  public:
126    typedef BasePrefetcherParams Params;
127    BasePrefetcher(const Params *p);
128
129    virtual ~BasePrefetcher() {}
130
131    void setCache(BaseCache *_cache);
132
133    /**
134     * Notify prefetcher of cache access (may be any access or just
135     * misses, depending on cache parameters.)
136     * @retval Time of next prefetch availability, or 0 if none.
137     */
138    Tick notify(PacketPtr &pkt, Tick tick);
139
140    bool inCache(Addr addr);
141
142    bool inMissQueue(Addr addr);
143
144    PacketPtr getPacket();
145
146    bool havePending()
147    {
148        return !pf.empty();
149    }
150
151    Tick nextPrefetchReadyTime()
152    {
153        return pf.empty() ? MaxTick : pf.front().tick;
154    }
155
156    virtual void calculatePrefetch(PacketPtr &pkt,
157                                   std::list<Addr> &addresses,
158                                   std::list<Cycles> &delays) = 0;
159
160    std::list<DeferredPacket>::iterator inPrefetch(Addr address);
161
162    /**
163     * Utility function: are addresses a and b on the same VM page?
164     */
165    bool samePage(Addr a, Addr b);
166 public:
167    const Params*
168    params() const
169    {
170        return dynamic_cast<const Params *>(_params);
171    }
172
173};
174#endif //__MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
175