base.hh revision 13667:e3ae3619b9ab
12810Srdreslin@umich.edu/* 212665Snikos.nikoleris@arm.com * Copyright (c) 2013-2014 ARM Limited 39347SAndreas.Sandberg@arm.com * All rights reserved. 49347SAndreas.Sandberg@arm.com * 59347SAndreas.Sandberg@arm.com * The license below extends only to copyright in the software and shall 69347SAndreas.Sandberg@arm.com * not be construed as granting a license to any other intellectual 79347SAndreas.Sandberg@arm.com * property including but not limited to intellectual property relating 89347SAndreas.Sandberg@arm.com * to a hardware implementation of the functionality of the software 99347SAndreas.Sandberg@arm.com * licensed hereunder. You may use the software subject to the license 109347SAndreas.Sandberg@arm.com * terms below provided that you ensure that this notice is replicated 119347SAndreas.Sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 129347SAndreas.Sandberg@arm.com * modified or unmodified, in source code or in binary form. 139347SAndreas.Sandberg@arm.com * 142810Srdreslin@umich.edu * Copyright (c) 2005 The Regents of The University of Michigan 152810Srdreslin@umich.edu * All rights reserved. 162810Srdreslin@umich.edu * 172810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 182810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 192810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 202810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 212810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 222810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 232810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 242810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 252810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 262810Srdreslin@umich.edu * this software without specific prior written permission. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810Srdreslin@umich.edu * 402810Srdreslin@umich.edu * Authors: Ron Dreslinski 4112665Snikos.nikoleris@arm.com * Mitch Hayenga 422810Srdreslin@umich.edu */ 432810Srdreslin@umich.edu 442810Srdreslin@umich.edu/** 452810Srdreslin@umich.edu * @file 462810Srdreslin@umich.edu * Miss and writeback queue declarations. 472810Srdreslin@umich.edu */ 482810Srdreslin@umich.edu 496216Snate@binkert.org#ifndef __MEM_CACHE_PREFETCH_BASE_HH__ 506216Snate@binkert.org#define __MEM_CACHE_PREFETCH_BASE_HH__ 512810Srdreslin@umich.edu 5212727Snikos.nikoleris@arm.com#include <cstdint> 5312728Snikos.nikoleris@arm.com 5412727Snikos.nikoleris@arm.com#include "base/statistics.hh" 5511168Sandreas.hansson@arm.com#include "base/types.hh" 562810Srdreslin@umich.edu#include "mem/packet.hh" 5712727Snikos.nikoleris@arm.com#include "mem/request.hh" 5812665Snikos.nikoleris@arm.com#include "sim/clocked_object.hh" 5912727Snikos.nikoleris@arm.com#include "sim/probe/probe.hh" 6012727Snikos.nikoleris@arm.com 6112727Snikos.nikoleris@arm.comclass BaseCache; 6211486Snikos.nikoleris@arm.comstruct BasePrefetcherParams; 638229Snate@binkert.org 642810Srdreslin@umich.educlass BasePrefetcher : public ClockedObject 659796Sprakash.ramrakhyani@arm.com{ 662810Srdreslin@umich.edu class PrefetchListener : public ProbeListenerArgBase<PacketPtr> 6712665Snikos.nikoleris@arm.com { 6812665Snikos.nikoleris@arm.com public: 6912665Snikos.nikoleris@arm.com PrefetchListener(BasePrefetcher &_parent, ProbeManager *pm, 7012665Snikos.nikoleris@arm.com const std::string &name) 7112665Snikos.nikoleris@arm.com : ProbeListenerArgBase(pm, name), 7212665Snikos.nikoleris@arm.com parent(_parent) {} 7312665Snikos.nikoleris@arm.com void notify(const PacketPtr &pkt) override; 7412665Snikos.nikoleris@arm.com protected: 7512665Snikos.nikoleris@arm.com BasePrefetcher &parent; 7612665Snikos.nikoleris@arm.com }; 772810Srdreslin@umich.edu 782810Srdreslin@umich.edu std::vector<PrefetchListener *> listeners; 792810Srdreslin@umich.edu 802810Srdreslin@umich.edu public: 812810Srdreslin@umich.edu 8212636Sodanrc@yahoo.com.br /** 832810Srdreslin@umich.edu * Class containing the information needed by the prefetch to train and 842810Srdreslin@umich.edu * generate new prefetch requests. 852810Srdreslin@umich.edu */ 862810Srdreslin@umich.edu class PrefetchInfo { 872810Srdreslin@umich.edu /** The address. */ 8812665Snikos.nikoleris@arm.com Addr address; 8912665Snikos.nikoleris@arm.com /** The program counter that generated this address. */ 902810Srdreslin@umich.edu Addr pc; 912810Srdreslin@umich.edu /** The requestor ID that generated this address. */ 922810Srdreslin@umich.edu MasterID masterId; 932810Srdreslin@umich.edu /** Validity bit for the PC of this address. */ 942810Srdreslin@umich.edu bool validPC; 952810Srdreslin@umich.edu /** Whether this address targets the secure memory space. */ 962810Srdreslin@umich.edu bool secure; 972810Srdreslin@umich.edu 982810Srdreslin@umich.edu public: 992810Srdreslin@umich.edu /** 1002810Srdreslin@umich.edu * Obtains the address value of this Prefetcher address. 1016227Snate@binkert.org * @return the addres value. 1022810Srdreslin@umich.edu */ 1032810Srdreslin@umich.edu Addr getAddr() const 1042810Srdreslin@umich.edu { 1052810Srdreslin@umich.edu return address; 1062810Srdreslin@umich.edu } 1072810Srdreslin@umich.edu 1082810Srdreslin@umich.edu /** 1092810Srdreslin@umich.edu * Returns true if the address targets the secure memory space. 1102810Srdreslin@umich.edu * @return true if the address targets the secure memory space. 1112810Srdreslin@umich.edu */ 11211168Sandreas.hansson@arm.com bool isSecure() const 1132810Srdreslin@umich.edu { 1142810Srdreslin@umich.edu return secure; 1152810Srdreslin@umich.edu } 1162810Srdreslin@umich.edu 1172810Srdreslin@umich.edu /** 1182810Srdreslin@umich.edu * Returns the program counter that generated this request. 1192810Srdreslin@umich.edu * @return the pc value 1202810Srdreslin@umich.edu */ 1212810Srdreslin@umich.edu Addr getPC() const 1222810Srdreslin@umich.edu { 1232810Srdreslin@umich.edu assert(hasPC()); 1242810Srdreslin@umich.edu return pc; 1252810Srdreslin@umich.edu } 1262810Srdreslin@umich.edu 1272810Srdreslin@umich.edu /** 12812648Sodanrc@yahoo.com.br * Returns true if the associated program counter is valid 1292810Srdreslin@umich.edu * @return true if the program counter has a valid value 1302810Srdreslin@umich.edu */ 1312810Srdreslin@umich.edu bool hasPC() const 1322810Srdreslin@umich.edu { 1332810Srdreslin@umich.edu return validPC; 13412648Sodanrc@yahoo.com.br } 13512648Sodanrc@yahoo.com.br 13612648Sodanrc@yahoo.com.br /** 13712648Sodanrc@yahoo.com.br * Gets the requestor ID that generated this address 13812648Sodanrc@yahoo.com.br * @return the requestor ID that generated this address 13912648Sodanrc@yahoo.com.br */ 14012636Sodanrc@yahoo.com.br MasterID getMasterId() const 1419796Sprakash.ramrakhyani@arm.com { 1429796Sprakash.ramrakhyani@arm.com return masterId; 1432810Srdreslin@umich.edu } 1442810Srdreslin@umich.edu 1452810Srdreslin@umich.edu /** 1469796Sprakash.ramrakhyani@arm.com * Check for equality 1479086Sandreas.hansson@arm.com * @param pfi PrefetchInfo to compare against 1482810Srdreslin@umich.edu * @return True if this object and the provided one are equal 1492810Srdreslin@umich.edu */ 1502810Srdreslin@umich.edu bool sameAddr(PrefetchInfo const &pfi) const 1512810Srdreslin@umich.edu { 15211169Sandreas.hansson@arm.com return this->getAddr() == pfi.getAddr() && 1532810Srdreslin@umich.edu this->isSecure() == pfi.isSecure(); 1542810Srdreslin@umich.edu } 1553862Sstever@eecs.umich.edu 1563862Sstever@eecs.umich.edu /** 1572810Srdreslin@umich.edu * Constructs a PrefetchInfo using a PacketPtr. 15811169Sandreas.hansson@arm.com * @param pkt PacketPtr used to generate the PrefetchInfo 1592810Srdreslin@umich.edu * @param addr the address value of the new object 1602810Srdreslin@umich.edu */ 16111483Snikos.nikoleris@arm.com PrefetchInfo(PacketPtr pkt, Addr addr); 16211484Snikos.nikoleris@arm.com 16311484Snikos.nikoleris@arm.com /** 16412665Snikos.nikoleris@arm.com * Constructs a PrefetchInfo using a new address value and 1652810Srdreslin@umich.edu * another PrefetchInfo as a reference. 16610028SGiacomo.Gabrielli@arm.com * @param pfi PrefetchInfo used to generate this new object 1672810Srdreslin@umich.edu * @param addr the address value of the new object 16812665Snikos.nikoleris@arm.com */ 1692810Srdreslin@umich.edu PrefetchInfo(PrefetchInfo const &pfi, Addr addr); 1702810Srdreslin@umich.edu }; 17110815Sdavid.guillen@arm.com 17212665Snikos.nikoleris@arm.com protected: 17310815Sdavid.guillen@arm.com 17410815Sdavid.guillen@arm.com // PARAMETERS 17510815Sdavid.guillen@arm.com 17610815Sdavid.guillen@arm.com /** Pointr to the parent cache. */ 17711870Snikos.nikoleris@arm.com BaseCache* cache; 1782810Srdreslin@umich.edu 1792810Srdreslin@umich.edu /** The block size of the parent cache. */ 1802810Srdreslin@umich.edu unsigned blkSize; 1812810Srdreslin@umich.edu 18210028SGiacomo.Gabrielli@arm.com /** log_2(block size of the parent cache). */ 1832810Srdreslin@umich.edu unsigned lBlkSize; 1842810Srdreslin@umich.edu 1852810Srdreslin@umich.edu /** Only consult prefetcher on cache misses? */ 18611169Sandreas.hansson@arm.com const bool onMiss; 1872810Srdreslin@umich.edu 1882810Srdreslin@umich.edu /** Consult prefetcher on reads? */ 18912743Sodanrc@yahoo.com.br const bool onRead; 19012743Sodanrc@yahoo.com.br 19112743Sodanrc@yahoo.com.br /** Consult prefetcher on reads? */ 19212743Sodanrc@yahoo.com.br const bool onWrite; 19312743Sodanrc@yahoo.com.br 19412743Sodanrc@yahoo.com.br /** Consult prefetcher on data accesses? */ 19512743Sodanrc@yahoo.com.br const bool onData; 19612743Sodanrc@yahoo.com.br 19712743Sodanrc@yahoo.com.br /** Consult prefetcher on instruction accesses? */ 19812600Sodanrc@yahoo.com.br const bool onInst; 19912600Sodanrc@yahoo.com.br 20012600Sodanrc@yahoo.com.br /** Request id for prefetches */ 20112600Sodanrc@yahoo.com.br const MasterID masterId; 2022810Srdreslin@umich.edu 20311169Sandreas.hansson@arm.com const Addr pageBytes; 2045717Shsul@eecs.umich.edu 20512636Sodanrc@yahoo.com.br /** Prefetch on every access, not just misses */ 20612636Sodanrc@yahoo.com.br const bool prefetchOnAccess; 20712636Sodanrc@yahoo.com.br 20812636Sodanrc@yahoo.com.br /** Use Virtual Addresses for prefetching */ 20912636Sodanrc@yahoo.com.br const bool useVirtualAddresses; 21012636Sodanrc@yahoo.com.br 21111169Sandreas.hansson@arm.com /** Determine if this access should be observed */ 2122810Srdreslin@umich.edu bool observeAccess(const PacketPtr &pkt) const; 2132810Srdreslin@umich.edu 2142810Srdreslin@umich.edu /** Determine if address is in cache */ 2152810Srdreslin@umich.edu bool inCache(Addr addr, bool is_secure) const; 2162810Srdreslin@umich.edu 2172810Srdreslin@umich.edu /** Determine if address is in cache miss queue */ 2182810Srdreslin@umich.edu bool inMissQueue(Addr addr, bool is_secure) const; 21911169Sandreas.hansson@arm.com 2202810Srdreslin@umich.edu bool hasBeenPrefetched(Addr addr, bool is_secure) const; 2212810Srdreslin@umich.edu 2222810Srdreslin@umich.edu /** Determine if addresses are on the same page */ 2232810Srdreslin@umich.edu bool samePage(Addr a, Addr b) const; 2242810Srdreslin@umich.edu /** Determine the address of the block in which a lays */ 22512574Sodanrc@yahoo.com.br Addr blockAddress(Addr a) const; 22612574Sodanrc@yahoo.com.br /** Determine the address of a at block granularity */ 22712574Sodanrc@yahoo.com.br Addr blockIndex(Addr a) const; 2282810Srdreslin@umich.edu /** Determine the address of the page in which a lays */ 2292810Srdreslin@umich.edu Addr pageAddress(Addr a) const; 23012574Sodanrc@yahoo.com.br /** Determine the page-offset of a */ 2312810Srdreslin@umich.edu Addr pageOffset(Addr a) const; 23212574Sodanrc@yahoo.com.br /** Build the address of the i-th block inside the page */ 2332810Srdreslin@umich.edu Addr pageIthBlockAddress(Addr page, uint32_t i) const; 2347612SGene.Wu@arm.com 23512728Snikos.nikoleris@arm.com Stats::Scalar pfIssued; 23612728Snikos.nikoleris@arm.com 23712728Snikos.nikoleris@arm.com /** Total prefetches issued */ 23812728Snikos.nikoleris@arm.com uint64_t issuedPrefetches; 23912728Snikos.nikoleris@arm.com /** Total prefetches that has been useful */ 2409663Suri.wiener@arm.com uint64_t usefulPrefetches; 24112728Snikos.nikoleris@arm.com 2429347SAndreas.Sandberg@arm.com public: 24312728Snikos.nikoleris@arm.com 24412728Snikos.nikoleris@arm.com BasePrefetcher(const BasePrefetcherParams *p); 24512728Snikos.nikoleris@arm.com 2469347SAndreas.Sandberg@arm.com virtual ~BasePrefetcher() {} 24712728Snikos.nikoleris@arm.com 2489347SAndreas.Sandberg@arm.com void setCache(BaseCache *_cache); 24912665Snikos.nikoleris@arm.com 25012665Snikos.nikoleris@arm.com /** 25112665Snikos.nikoleris@arm.com * Notify prefetcher of cache access (may be any access or just 25212665Snikos.nikoleris@arm.com * misses, depending on cache parameters.) 25312665Snikos.nikoleris@arm.com */ 25412665Snikos.nikoleris@arm.com virtual void notify(const PacketPtr &pkt, const PrefetchInfo &pfi) = 0; 25512665Snikos.nikoleris@arm.com 25612665Snikos.nikoleris@arm.com virtual PacketPtr getPacket() = 0; 25712665Snikos.nikoleris@arm.com 25812665Snikos.nikoleris@arm.com virtual Tick nextPrefetchReadyTime() const = 0; 25912665Snikos.nikoleris@arm.com 26012665Snikos.nikoleris@arm.com /** 26112665Snikos.nikoleris@arm.com * Register local statistics. 26212665Snikos.nikoleris@arm.com */ 26312665Snikos.nikoleris@arm.com void regStats() override; 26412665Snikos.nikoleris@arm.com 26512665Snikos.nikoleris@arm.com /** 26612665Snikos.nikoleris@arm.com * Register probe points for this object. 26712665Snikos.nikoleris@arm.com */ 26812665Snikos.nikoleris@arm.com void regProbeListeners() override; 26912665Snikos.nikoleris@arm.com 27012665Snikos.nikoleris@arm.com /** 27112665Snikos.nikoleris@arm.com * Process a notification event from the ProbeListener. 27212665Snikos.nikoleris@arm.com * @param pkt The memory request causing the event 27312665Snikos.nikoleris@arm.com */ 27412665Snikos.nikoleris@arm.com void probeNotify(const PacketPtr &pkt); 27512665Snikos.nikoleris@arm.com 27612665Snikos.nikoleris@arm.com /** 27712665Snikos.nikoleris@arm.com * Add a SimObject and a probe name to listen events from 27812665Snikos.nikoleris@arm.com * @param obj The SimObject pointer to listen from 27912665Snikos.nikoleris@arm.com * @param name The probe name 28012665Snikos.nikoleris@arm.com */ 28112665Snikos.nikoleris@arm.com void addEventProbe(SimObject *obj, const char *name); 28212665Snikos.nikoleris@arm.com}; 28312665Snikos.nikoleris@arm.com#endif //__MEM_CACHE_PREFETCH_BASE_HH__ 28412665Snikos.nikoleris@arm.com