base.hh revision 13551:f352df8e2863 
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 *          Mitch Hayenga
42 */
43
44/**
45 * @file
46 * Miss and writeback queue declarations.
47 */
48
49#ifndef __MEM_CACHE_PREFETCH_BASE_HH__
50#define __MEM_CACHE_PREFETCH_BASE_HH__
51
52#include <cstdint>
53
54#include "base/statistics.hh"
55#include "base/types.hh"
56#include "mem/packet.hh"
57#include "mem/request.hh"
58#include "sim/clocked_object.hh"
59#include "sim/probe/probe.hh"
60
61class BaseCache;
62struct BasePrefetcherParams;
63
64class BasePrefetcher : public ClockedObject
65{
66    class PrefetchListener : public ProbeListenerArgBase<PacketPtr>
67    {
68      public:
69        PrefetchListener(BasePrefetcher &_parent, ProbeManager *pm,
70                         const std::string &name)
71            : ProbeListenerArgBase(pm, name),
72              parent(_parent) {}
73        void notify(const PacketPtr &pkt) override;
74      protected:
75        BasePrefetcher &parent;
76    };
77
78    std::vector<PrefetchListener *> listeners;
79  protected:
80
81    /**
82     * Class containing the information needed by the prefetch to train and
83     * generate new prefetch requests.
84     */
85    class PrefetchInfo {
86        /** The address. */
87        Addr address;
88        /** The program counter that generated this address. */
89        Addr pc;
90        /** The requestor ID that generated this address. */
91        MasterID masterId;
92        /** Validity bit for the PC of this address. */
93        bool validPC;
94        /** Whether this address targets the secure memory space. */
95        bool secure;
96
97      public:
98        /**
99         * Obtains the address value of this Prefetcher address.
100         * @return the addres value.
101         */
102        Addr getAddr() const
103        {
104            return address;
105        }
106
107        /**
108         * Returns true if the address targets the secure memory space.
109         * @return true if the address targets the secure memory space.
110         */
111        bool isSecure() const
112        {
113            return secure;
114        }
115
116        /**
117         * Returns the program counter that generated this request.
118         * @return the pc value
119         */
120        Addr getPC() const
121        {
122            assert(hasPC());
123            return pc;
124        }
125
126        /**
127         * Returns true if the associated program counter is valid
128         * @return true if the program counter has a valid value
129         */
130        bool hasPC() const
131        {
132            return validPC;
133        }
134
135        /**
136         * Gets the requestor ID that generated this address
137         * @return the requestor ID that generated this address
138         */
139        MasterID getMasterId() const
140        {
141            return masterId;
142        }
143
144        /**
145         * Check for equality
146         * @param pfi PrefetchInfo to compare against
147         * @return True if this object and the provided one are equal
148         */
149        bool sameAddr(PrefetchInfo const &pfi) const
150        {
151            return this->getAddr() == pfi.getAddr() &&
152                this->isSecure() == pfi.isSecure();
153        }
154
155        /**
156         * Constructs a PrefetchInfo using a PacketPtr.
157         * @param pkt PacketPtr used to generate the PrefetchInfo
158         * @param addr the address value of the new object
159         */
160        PrefetchInfo(PacketPtr pkt, Addr addr);
161
162        /**
163         * Constructs a PrefetchInfo using a new address value and
164         * another PrefetchInfo as a reference.
165         * @param pfi PrefetchInfo used to generate this new object
166         * @param addr the address value of the new object
167         */
168        PrefetchInfo(PrefetchInfo const &pfi, Addr addr);
169    };
170
171    // PARAMETERS
172
173    /** Pointr to the parent cache. */
174    BaseCache* cache;
175
176    /** The block size of the parent cache. */
177    unsigned blkSize;
178
179    /** log_2(block size of the parent cache). */
180    unsigned lBlkSize;
181
182    /** Only consult prefetcher on cache misses? */
183    const bool onMiss;
184
185    /** Consult prefetcher on reads? */
186    const bool onRead;
187
188    /** Consult prefetcher on reads? */
189    const bool onWrite;
190
191    /** Consult prefetcher on data accesses? */
192    const bool onData;
193
194    /** Consult prefetcher on instruction accesses? */
195    const bool onInst;
196
197    /** Request id for prefetches */
198    const MasterID masterId;
199
200    const Addr pageBytes;
201
202    /** Prefetch on every access, not just misses */
203    const bool prefetchOnAccess;
204
205    /** Use Virtual Addresses for prefetching */
206    const bool useVirtualAddresses;
207
208    /** Determine if this access should be observed */
209    bool observeAccess(const PacketPtr &pkt) const;
210
211    /** Determine if address is in cache */
212    bool inCache(Addr addr, bool is_secure) const;
213
214    /** Determine if address is in cache miss queue */
215    bool inMissQueue(Addr addr, bool is_secure) const;
216
217    /** Determine if addresses are on the same page */
218    bool samePage(Addr a, Addr b) const;
219    /** Determine the address of the block in which a lays */
220    Addr blockAddress(Addr a) const;
221    /** Determine the address of a at block granularity */
222    Addr blockIndex(Addr a) const;
223    /** Determine the address of the page in which a lays */
224    Addr pageAddress(Addr a) const;
225    /** Determine the page-offset of a  */
226    Addr pageOffset(Addr a) const;
227    /** Build the address of the i-th block inside the page */
228    Addr pageIthBlockAddress(Addr page, uint32_t i) const;
229
230    Stats::Scalar pfIssued;
231
232  public:
233
234    BasePrefetcher(const BasePrefetcherParams *p);
235
236    virtual ~BasePrefetcher() {}
237
238    void setCache(BaseCache *_cache);
239
240    /**
241     * Notify prefetcher of cache access (may be any access or just
242     * misses, depending on cache parameters.)
243     */
244    virtual void notify(const PacketPtr &pkt, const PrefetchInfo &pfi) = 0;
245
246    virtual PacketPtr getPacket() = 0;
247
248    virtual Tick nextPrefetchReadyTime() const = 0;
249
250    /**
251     * Register local statistics.
252     */
253    void regStats() override;
254
255    /**
256     * Register probe points for this object.
257     */
258    void regProbeListeners() override;
259
260    /**
261     * Process a notification event from the ProbeListener.
262     * @param pkt The memory request causing the event
263     */
264    void probeNotify(const PacketPtr &pkt);
265
266    /**
267     * Add a SimObject and a probe name to listen events from
268     * @param obj The SimObject pointer to listen from
269     * @param name The probe name
270     */
271    void addEventProbe(SimObject *obj, const char *name);
272};
273#endif //__MEM_CACHE_PREFETCH_BASE_HH__
274