base.hh revision 13422:4ec52da74cd5 
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 *          Mitch Hayenga
42 */
43
44/**
45 * @file
46 * Miss and writeback queue declarations.
47 */
48
49#ifndef __MEM_CACHE_PREFETCH_BASE_HH__
50#define __MEM_CACHE_PREFETCH_BASE_HH__
51
52#include <cstdint>
53
54#include "base/statistics.hh"
55#include "base/types.hh"
56#include "mem/packet.hh"
57#include "mem/request.hh"
58#include "sim/clocked_object.hh"
59#include "sim/probe/probe.hh"
60
61class BaseCache;
62struct BasePrefetcherParams;
63
64class BasePrefetcher : public ClockedObject
65{
66    class PrefetchListener : public ProbeListenerArgBase<PacketPtr>
67    {
68      public:
69        PrefetchListener(BasePrefetcher &_parent, ProbeManager *pm,
70                         const std::string &name)
71            : ProbeListenerArgBase(pm, name),
72              parent(_parent) {}
73        void notify(const PacketPtr &pkt) override;
74      protected:
75        BasePrefetcher &parent;
76    };
77
78    std::vector<PrefetchListener *> listeners;
79  protected:
80
81    // PARAMETERS
82
83    /** Pointr to the parent cache. */
84    BaseCache* cache;
85
86    /** The block size of the parent cache. */
87    unsigned blkSize;
88
89    /** log_2(block size of the parent cache). */
90    unsigned lBlkSize;
91
92    /** Only consult prefetcher on cache misses? */
93    const bool onMiss;
94
95    /** Consult prefetcher on reads? */
96    const bool onRead;
97
98    /** Consult prefetcher on reads? */
99    const bool onWrite;
100
101    /** Consult prefetcher on data accesses? */
102    const bool onData;
103
104    /** Consult prefetcher on instruction accesses? */
105    const bool onInst;
106
107    /** Request id for prefetches */
108    const MasterID masterId;
109
110    const Addr pageBytes;
111
112    /** Prefetch on every access, not just misses */
113    const bool prefetchOnAccess;
114
115    /** Determine if this access should be observed */
116    bool observeAccess(const PacketPtr &pkt) const;
117
118    /** Determine if address is in cache */
119    bool inCache(Addr addr, bool is_secure) const;
120
121    /** Determine if address is in cache miss queue */
122    bool inMissQueue(Addr addr, bool is_secure) const;
123
124    /** Determine if addresses are on the same page */
125    bool samePage(Addr a, Addr b) const;
126    /** Determine the address of the block in which a lays */
127    Addr blockAddress(Addr a) const;
128    /** Determine the address of a at block granularity */
129    Addr blockIndex(Addr a) const;
130    /** Determine the address of the page in which a lays */
131    Addr pageAddress(Addr a) const;
132    /** Determine the page-offset of a  */
133    Addr pageOffset(Addr a) const;
134    /** Build the address of the i-th block inside the page */
135    Addr pageIthBlockAddress(Addr page, uint32_t i) const;
136
137
138    Stats::Scalar pfIssued;
139
140  public:
141
142    BasePrefetcher(const BasePrefetcherParams *p);
143
144    virtual ~BasePrefetcher() {}
145
146    void setCache(BaseCache *_cache);
147
148    /**
149     * Notify prefetcher of cache access (may be any access or just
150     * misses, depending on cache parameters.)
151     */
152    virtual void notify(const PacketPtr &pkt) = 0;
153
154    virtual PacketPtr getPacket() = 0;
155
156    virtual Tick nextPrefetchReadyTime() const = 0;
157
158    /**
159     * Register local statistics.
160     */
161    void regStats() override;
162
163    /**
164     * Register probe points for this object.
165     */
166    void regProbeListeners() override;
167
168    /**
169     * Process a notification event from the ProbeListener.
170     * @param pkt The memory request causing the event
171     */
172    void probeNotify(const PacketPtr &pkt);
173
174    /**
175     * Add a SimObject and a probe name to listen events from
176     * @param obj The SimObject pointer to listen from
177     * @param name The probe name
178     */
179    void addEventProbe(SimObject *obj, const char *name);
180};
181#endif //__MEM_CACHE_PREFETCH_BASE_HH__
182