base.hh revision 12727:56c23b54bcb1
112771Sqtt2@cornell.edu/* 212771Sqtt2@cornell.edu * Copyright (c) 2013-2014 ARM Limited 312771Sqtt2@cornell.edu * All rights reserved. 412771Sqtt2@cornell.edu * 512771Sqtt2@cornell.edu * The license below extends only to copyright in the software and shall 612771Sqtt2@cornell.edu * not be construed as granting a license to any other intellectual 712771Sqtt2@cornell.edu * property including but not limited to intellectual property relating 812771Sqtt2@cornell.edu * to a hardware implementation of the functionality of the software 912771Sqtt2@cornell.edu * licensed hereunder. You may use the software subject to the license 1012771Sqtt2@cornell.edu * terms below provided that you ensure that this notice is replicated 1112771Sqtt2@cornell.edu * unmodified and in its entirety in all distributions of the software, 1212771Sqtt2@cornell.edu * modified or unmodified, in source code or in binary form. 1312771Sqtt2@cornell.edu * 1412771Sqtt2@cornell.edu * Copyright (c) 2005 The Regents of The University of Michigan 1512771Sqtt2@cornell.edu * All rights reserved. 1612771Sqtt2@cornell.edu * 1712771Sqtt2@cornell.edu * Redistribution and use in source and binary forms, with or without 1812771Sqtt2@cornell.edu * modification, are permitted provided that the following conditions are 1912771Sqtt2@cornell.edu * met: redistributions of source code must retain the above copyright 2012771Sqtt2@cornell.edu * notice, this list of conditions and the following disclaimer; 2112771Sqtt2@cornell.edu * redistributions in binary form must reproduce the above copyright 2212771Sqtt2@cornell.edu * notice, this list of conditions and the following disclaimer in the 2312771Sqtt2@cornell.edu * documentation and/or other materials provided with the distribution; 2412771Sqtt2@cornell.edu * neither the name of the copyright holders nor the names of its 2512771Sqtt2@cornell.edu * contributors may be used to endorse or promote products derived from 2612771Sqtt2@cornell.edu * this software without specific prior written permission. 2712771Sqtt2@cornell.edu * 2812771Sqtt2@cornell.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2912771Sqtt2@cornell.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3012771Sqtt2@cornell.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3112771Sqtt2@cornell.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3212771Sqtt2@cornell.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3312771Sqtt2@cornell.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3412771Sqtt2@cornell.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3512771Sqtt2@cornell.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3612771Sqtt2@cornell.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3712771Sqtt2@cornell.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3812771Sqtt2@cornell.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3912771Sqtt2@cornell.edu * 4012771Sqtt2@cornell.edu * Authors: Ron Dreslinski 4112771Sqtt2@cornell.edu * Mitch Hayenga 4212771Sqtt2@cornell.edu */ 4312771Sqtt2@cornell.edu 4412771Sqtt2@cornell.edu/** 4512771Sqtt2@cornell.edu * @file 4612771Sqtt2@cornell.edu * Miss and writeback queue declarations. 4712771Sqtt2@cornell.edu */ 4812771Sqtt2@cornell.edu 4912771Sqtt2@cornell.edu#ifndef __MEM_CACHE_PREFETCH_BASE_HH__ 5012771Sqtt2@cornell.edu#define __MEM_CACHE_PREFETCH_BASE_HH__ 5112771Sqtt2@cornell.edu 5212771Sqtt2@cornell.edu#include <cstdint> 5312771Sqtt2@cornell.edu 5412771Sqtt2@cornell.edu#include "base/statistics.hh" 5512771Sqtt2@cornell.edu#include "base/types.hh" 5612771Sqtt2@cornell.edu#include "mem/packet.hh" 5712771Sqtt2@cornell.edu#include "mem/request.hh" 5812771Sqtt2@cornell.edu#include "sim/clocked_object.hh" 5912771Sqtt2@cornell.edu 6012771Sqtt2@cornell.educlass BaseCache; 6112771Sqtt2@cornell.edustruct BasePrefetcherParams; 6212771Sqtt2@cornell.educlass System; 6312771Sqtt2@cornell.edu 6412771Sqtt2@cornell.educlass BasePrefetcher : public ClockedObject 6512771Sqtt2@cornell.edu{ 6612771Sqtt2@cornell.edu protected: 6712771Sqtt2@cornell.edu 6812771Sqtt2@cornell.edu // PARAMETERS 6912771Sqtt2@cornell.edu 7012771Sqtt2@cornell.edu /** Pointr to the parent cache. */ 7112771Sqtt2@cornell.edu BaseCache* cache; 7212771Sqtt2@cornell.edu 7312771Sqtt2@cornell.edu /** The block size of the parent cache. */ 7412771Sqtt2@cornell.edu unsigned blkSize; 7512771Sqtt2@cornell.edu 7612771Sqtt2@cornell.edu /** log_2(block size of the parent cache). */ 7712771Sqtt2@cornell.edu unsigned lBlkSize; 7812771Sqtt2@cornell.edu 7912771Sqtt2@cornell.edu /** System we belong to */ 8012771Sqtt2@cornell.edu System* system; 8112771Sqtt2@cornell.edu 8212771Sqtt2@cornell.edu /** Only consult prefetcher on cache misses? */ 8312771Sqtt2@cornell.edu bool onMiss; 8412771Sqtt2@cornell.edu 8512771Sqtt2@cornell.edu /** Consult prefetcher on reads? */ 8612771Sqtt2@cornell.edu bool onRead; 8712771Sqtt2@cornell.edu 8812771Sqtt2@cornell.edu /** Consult prefetcher on reads? */ 8912771Sqtt2@cornell.edu bool onWrite; 9012771Sqtt2@cornell.edu 9112771Sqtt2@cornell.edu /** Consult prefetcher on data accesses? */ 9212771Sqtt2@cornell.edu bool onData; 9312771Sqtt2@cornell.edu 9412771Sqtt2@cornell.edu /** Consult prefetcher on instruction accesses? */ 9512771Sqtt2@cornell.edu bool onInst; 9612771Sqtt2@cornell.edu 9712771Sqtt2@cornell.edu /** Request id for prefetches */ 9812771Sqtt2@cornell.edu MasterID masterId; 9912771Sqtt2@cornell.edu 10012771Sqtt2@cornell.edu const Addr pageBytes; 10112771Sqtt2@cornell.edu 10212771Sqtt2@cornell.edu /** Determine if this access should be observed */ 10312771Sqtt2@cornell.edu bool observeAccess(const PacketPtr &pkt) const; 10412771Sqtt2@cornell.edu 10512771Sqtt2@cornell.edu /** Determine if address is in cache */ 10612771Sqtt2@cornell.edu bool inCache(Addr addr, bool is_secure) const; 10712771Sqtt2@cornell.edu 10812771Sqtt2@cornell.edu /** Determine if address is in cache miss queue */ 10912771Sqtt2@cornell.edu bool inMissQueue(Addr addr, bool is_secure) const; 11012771Sqtt2@cornell.edu 11112771Sqtt2@cornell.edu /** Determine if addresses are on the same page */ 11212771Sqtt2@cornell.edu bool samePage(Addr a, Addr b) const; 11312771Sqtt2@cornell.edu /** Determine the address of the block in which a lays */ 114 Addr blockAddress(Addr a) const; 115 /** Determine the address of a at block granularity */ 116 Addr blockIndex(Addr a) const; 117 /** Determine the address of the page in which a lays */ 118 Addr pageAddress(Addr a) const; 119 /** Determine the page-offset of a */ 120 Addr pageOffset(Addr a) const; 121 /** Build the address of the i-th block inside the page */ 122 Addr pageIthBlockAddress(Addr page, uint32_t i) const; 123 124 125 Stats::Scalar pfIssued; 126 127 public: 128 129 BasePrefetcher(const BasePrefetcherParams *p); 130 131 virtual ~BasePrefetcher() {} 132 133 virtual void setCache(BaseCache *_cache); 134 135 /** 136 * Notify prefetcher of cache access (may be any access or just 137 * misses, depending on cache parameters.) 138 * @retval Time of next prefetch availability, or MaxTick if none. 139 */ 140 virtual Tick notify(const PacketPtr &pkt) = 0; 141 142 virtual PacketPtr getPacket() = 0; 143 144 virtual Tick nextPrefetchReadyTime() const = 0; 145 146 virtual void regStats(); 147}; 148#endif //__MEM_CACHE_PREFETCH_BASE_HH__ 149