base.hh revision 10623:b9646f4546ad 
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 *          Mitch Hayenga
42 */
43
44/**
45 * @file
46 * Miss and writeback queue declarations.
47 */
48
49#ifndef __MEM_CACHE_PREFETCH_BASE_HH__
50#define __MEM_CACHE_PREFETCH_BASE_HH__
51
52#include "base/statistics.hh"
53#include "mem/packet.hh"
54#include "params/BasePrefetcher.hh"
55#include "sim/clocked_object.hh"
56
57class BaseCache;
58
59class BasePrefetcher : public ClockedObject
60{
61  protected:
62
63    // PARAMETERS
64
65    /** Pointr to the parent cache. */
66    BaseCache* cache;
67
68    /** The block size of the parent cache. */
69    unsigned blkSize;
70
71    /** System we belong to */
72    System* system;
73
74    /** Only consult prefetcher on cache misses? */
75    bool onMiss;
76
77    /** Consult prefetcher on reads? */
78    bool onRead;
79
80    /** Consult prefetcher on reads? */
81    bool onWrite;
82
83    /** Consult prefetcher on data accesses? */
84    bool onData;
85
86    /** Consult prefetcher on instruction accesses? */
87    bool onInst;
88
89    /** Request id for prefetches */
90    MasterID masterId;
91
92    const Addr pageBytes;
93
94    /** Determine if this access should be observed */
95    bool observeAccess(const PacketPtr &pkt) const;
96
97    /** Determine if address is in cache */
98    bool inCache(Addr addr, bool is_secure) const;
99
100    /** Determine if address is in cache miss queue */
101    bool inMissQueue(Addr addr, bool is_secure) const;
102
103    /** Determine if addresses are on the same page */
104    bool samePage(Addr a, Addr b) const;
105
106    Stats::Scalar pfIssued;
107
108  public:
109
110    BasePrefetcher(const BasePrefetcherParams *p);
111
112    virtual ~BasePrefetcher() {}
113
114    void setCache(BaseCache *_cache);
115
116    /**
117     * Notify prefetcher of cache access (may be any access or just
118     * misses, depending on cache parameters.)
119     * @retval Time of next prefetch availability, or MaxTick if none.
120     */
121    virtual Tick notify(const PacketPtr &pkt) = 0;
122
123    virtual PacketPtr getPacket() = 0;
124
125    virtual Tick nextPrefetchReadyTime() const = 0;
126
127    virtual void regStats();
128};
129#endif //__MEM_CACHE_PREFETCH_BASE_HH__
130