base.hh revision 3861 
1/*
2 * Copyright (c) 2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ron Dreslinski
29 */
30
31/**
32 * @file
33 * Miss and writeback queue declarations.
34 */
35
36#ifndef __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
37#define __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
38
39#include <list>
40
41#include "base/statistics.hh"
42#include "mem/packet.hh"
43
44class BaseCache;
45
46class BasePrefetcher
47{
48  protected:
49
50    /** The Prefetch Queue. */
51    std::list<PacketPtr> pf;
52
53    // PARAMETERS
54
55    /** The number of MSHRs in the Prefetch Queue. */
56    const int size;
57
58    /** Pointr to the parent cache. */
59    BaseCache* cache;
60
61    /** The block size of the parent cache. */
62    int blkSize;
63
64    /** Do we prefetch across page boundaries. */
65    bool pageStop;
66
67    /** Do we remove prefetches with later times than a new miss.*/
68    bool serialSquash;
69
70    /** Do we check if it is in the cache when inserting into buffer,
71        or removing.*/
72    bool cacheCheckPush;
73
74    /** Do we prefetch on only data reads, or on inst reads as well. */
75    bool only_data;
76
77  public:
78
79    Stats::Scalar<> pfIdentified;
80    Stats::Scalar<> pfMSHRHit;
81    Stats::Scalar<> pfCacheHit;
82    Stats::Scalar<> pfBufferHit;
83    Stats::Scalar<> pfRemovedFull;
84    Stats::Scalar<> pfRemovedMSHR;
85    Stats::Scalar<> pfIssued;
86    Stats::Scalar<> pfSpanPage;
87    Stats::Scalar<> pfSquashed;
88
89    void regStats(const std::string &name);
90
91  public:
92    BasePrefetcher(int numMSHRS, bool pageStop, bool serialSquash,
93                   bool cacheCheckPush, bool onlyData);
94
95    virtual ~BasePrefetcher() {}
96
97    void setCache(BaseCache *_cache);
98
99    void handleMiss(PacketPtr &pkt, Tick time);
100
101    bool inCache(Addr addr);
102
103    bool inMissQueue(Addr addr);
104
105    PacketPtr getPacket();
106
107    bool havePending()
108    {
109        return !pf.empty();
110    }
111
112    virtual void calculatePrefetch(PacketPtr &pkt,
113                                   std::list<Addr> &addresses,
114                                   std::list<Tick> &delays) = 0;
115
116    std::list<PacketPtr>::iterator inPrefetch(Addr address);
117};
118
119
120#endif //__MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
121