base.cc revision 5337:f81512eb8bdf
1/* 2 * Copyright (c) 2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ron Dreslinski 29 */ 30 31/** 32 * @file 33 * Hardware Prefetcher Definition. 34 */ 35 36#include "base/trace.hh" 37#include "mem/cache/base_cache.hh" 38#include "mem/cache/prefetch/base_prefetcher.hh" 39#include "mem/request.hh" 40#include <list> 41 42BasePrefetcher::BasePrefetcher(const BaseCacheParams *p) 43 : size(p->prefetcher_size), pageStop(!p->prefetch_past_page), 44 serialSquash(p->prefetch_serial_squash), 45 cacheCheckPush(p->prefetch_cache_check_push), 46 only_data(p->prefetch_data_accesses_only) 47{ 48} 49 50void 51BasePrefetcher::setCache(BaseCache *_cache) 52{ 53 cache = _cache; 54 blkSize = cache->getBlockSize(); 55} 56 57void 58BasePrefetcher::regStats(const std::string &name) 59{ 60 pfIdentified 61 .name(name + ".prefetcher.num_hwpf_identified") 62 .desc("number of hwpf identified") 63 ; 64 65 pfMSHRHit 66 .name(name + ".prefetcher.num_hwpf_already_in_mshr") 67 .desc("number of hwpf that were already in mshr") 68 ; 69 70 pfCacheHit 71 .name(name + ".prefetcher.num_hwpf_already_in_cache") 72 .desc("number of hwpf that were already in the cache") 73 ; 74 75 pfBufferHit 76 .name(name + ".prefetcher.num_hwpf_already_in_prefetcher") 77 .desc("number of hwpf that were already in the prefetch queue") 78 ; 79 80 pfRemovedFull 81 .name(name + ".prefetcher.num_hwpf_evicted") 82 .desc("number of hwpf removed due to no buffer left") 83 ; 84 85 pfRemovedMSHR 86 .name(name + ".prefetcher.num_hwpf_removed_MSHR_hit") 87 .desc("number of hwpf removed because MSHR allocated") 88 ; 89 90 pfIssued 91 .name(name + ".prefetcher.num_hwpf_issued") 92 .desc("number of hwpf issued") 93 ; 94 95 pfSpanPage 96 .name(name + ".prefetcher.num_hwpf_span_page") 97 .desc("number of hwpf spanning a virtual page") 98 ; 99 100 pfSquashed 101 .name(name + ".prefetcher.num_hwpf_squashed_from_miss") 102 .desc("number of hwpf that got squashed due to a miss aborting calculation time") 103 ; 104} 105 106inline bool 107BasePrefetcher::inCache(Addr addr) 108{ 109 if (cache->inCache(addr)) { 110 pfCacheHit++; 111 return true; 112 } 113 return false; 114} 115 116inline bool 117BasePrefetcher::inMissQueue(Addr addr) 118{ 119 if (cache->inMissQueue(addr)) { 120 pfMSHRHit++; 121 return true; 122 } 123 return false; 124} 125 126PacketPtr 127BasePrefetcher::getPacket() 128{ 129 DPRINTF(HWPrefetch, "%s:Requesting a hw_pf to issue\n", cache->name()); 130 131 if (pf.empty()) { 132 DPRINTF(HWPrefetch, "%s:No HW_PF found\n", cache->name()); 133 return NULL; 134 } 135 136 PacketPtr pkt; 137 bool keepTrying = false; 138 do { 139 pkt = *pf.begin(); 140 pf.pop_front(); 141 if (!cacheCheckPush) { 142 keepTrying = cache->inCache(pkt->getAddr()); 143 } 144 if (pf.empty()) { 145 cache->deassertMemSideBusRequest(BaseCache::Request_PF); 146 if (keepTrying) return NULL; //None left, all were in cache 147 } 148 } while (keepTrying); 149 150 pfIssued++; 151 return pkt; 152} 153 154void 155BasePrefetcher::handleMiss(PacketPtr &pkt, Tick time) 156{ 157 if (!pkt->req->isUncacheable() && !(pkt->req->isInstRead() && only_data)) 158 { 159 //Calculate the blk address 160 Addr blkAddr = pkt->getAddr() & ~(Addr)(blkSize-1); 161 162 //Check if miss is in pfq, if so remove it 163 std::list<PacketPtr>::iterator iter = inPrefetch(blkAddr); 164 if (iter != pf.end()) { 165 DPRINTF(HWPrefetch, "%s:Saw a miss to a queued prefetch, removing it\n", cache->name()); 166 pfRemovedMSHR++; 167 pf.erase(iter); 168 if (pf.empty()) 169 cache->deassertMemSideBusRequest(BaseCache::Request_PF); 170 } 171 172 //Remove anything in queue with delay older than time 173 //since everything is inserted in time order, start from end 174 //and work until pf.empty() or time is earlier 175 //This is done to emulate Aborting the previous work on a new miss 176 //Needed for serial calculators like GHB 177 if (serialSquash) { 178 iter = pf.end(); 179 iter--; 180 while (!pf.empty() && ((*iter)->time >= time)) { 181 pfSquashed++; 182 pf.pop_back(); 183 iter--; 184 } 185 if (pf.empty()) 186 cache->deassertMemSideBusRequest(BaseCache::Request_PF); 187 } 188 189 190 std::list<Addr> addresses; 191 std::list<Tick> delays; 192 calculatePrefetch(pkt, addresses, delays); 193 194 std::list<Addr>::iterator addr = addresses.begin(); 195 std::list<Tick>::iterator delay = delays.begin(); 196 while (addr != addresses.end()) 197 { 198 DPRINTF(HWPrefetch, "%s:Found a pf canidate, inserting into prefetch queue\n", cache->name()); 199 //temp calc this here... 200 pfIdentified++; 201 //create a prefetch memreq 202 Request * prefetchReq = new Request(*addr, blkSize, 0); 203 PacketPtr prefetch; 204 prefetch = new Packet(prefetchReq, MemCmd::HardPFReq, -1); 205 prefetch->allocate(); 206 prefetch->req->setThreadContext(pkt->req->getCpuNum(), 207 pkt->req->getThreadNum()); 208 209 prefetch->time = time + (*delay); //@todo ADD LATENCY HERE 210 //... initialize 211 212 //Check if it is already in the cache 213 if (cacheCheckPush) { 214 if (cache->inCache(prefetch->getAddr())) { 215 addr++; 216 delay++; 217 continue; 218 } 219 } 220 221 //Check if it is already in the miss_queue 222 if (cache->inMissQueue(prefetch->getAddr())) { 223 addr++; 224 delay++; 225 continue; 226 } 227 228 //Check if it is already in the pf buffer 229 if (inPrefetch(prefetch->getAddr()) != pf.end()) { 230 pfBufferHit++; 231 addr++; 232 delay++; 233 continue; 234 } 235 236 //We just remove the head if we are full 237 if (pf.size() == size) 238 { 239 DPRINTF(HWPrefetch, "%s:Inserting into prefetch queue, it was full removing oldest\n", cache->name()); 240 pfRemovedFull++; 241 pf.pop_front(); 242 } 243 244 pf.push_back(prefetch); 245 246 //Make sure to request the bus, with proper delay 247 cache->requestMemSideBus(BaseCache::Request_PF, prefetch->time); 248 249 //Increment through the list 250 addr++; 251 delay++; 252 } 253 } 254} 255 256std::list<PacketPtr>::iterator 257BasePrefetcher::inPrefetch(Addr address) 258{ 259 //Guaranteed to only be one match, we always check before inserting 260 std::list<PacketPtr>::iterator iter; 261 for (iter=pf.begin(); iter != pf.end(); iter++) { 262 if (((*iter)->getAddr() & ~(Addr)(blkSize-1)) == address) { 263 return iter; 264 } 265 } 266 return pf.end(); 267} 268 269 270