base.cc revision 13717:11e81e2a98bd 
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 *          Mitch Hayenga
42 */
43
44/**
45 * @file
46 * Hardware Prefetcher Definition.
47 */
48
49#include "mem/cache/prefetch/base.hh"
50
51#include <cassert>
52
53#include "base/intmath.hh"
54#include "cpu/base.hh"
55#include "mem/cache/base.hh"
56#include "params/BasePrefetcher.hh"
57#include "sim/system.hh"
58
59BasePrefetcher::PrefetchInfo::PrefetchInfo(PacketPtr pkt, Addr addr)
60  : address(addr), pc(pkt->req->hasPC() ? pkt->req->getPC() : 0),
61    masterId(pkt->req->masterId()), validPC(pkt->req->hasPC()),
62    secure(pkt->isSecure())
63{
64}
65
66BasePrefetcher::PrefetchInfo::PrefetchInfo(PrefetchInfo const &pfi, Addr addr)
67  : address(addr), pc(pfi.pc), masterId(pfi.masterId), validPC(pfi.validPC),
68    secure(pfi.secure)
69{
70}
71
72void
73BasePrefetcher::PrefetchListener::notify(const PacketPtr &pkt)
74{
75    if (isFill) {
76        parent.notifyFill(pkt);
77    } else {
78        parent.probeNotify(pkt);
79    }
80}
81
82BasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p)
83    : ClockedObject(p), listeners(), cache(nullptr), blkSize(p->block_size),
84      lBlkSize(floorLog2(blkSize)), onMiss(p->on_miss), onRead(p->on_read),
85      onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
86      masterId(p->sys->getMasterId(this)), pageBytes(p->sys->getPageBytes()),
87      prefetchOnAccess(p->prefetch_on_access),
88      useVirtualAddresses(p->use_virtual_addresses), issuedPrefetches(0),
89      usefulPrefetches(0)
90{
91}
92
93void
94BasePrefetcher::setCache(BaseCache *_cache)
95{
96    assert(!cache);
97    cache = _cache;
98
99    // If the cache has a different block size from the system's, save it
100    blkSize = cache->getBlockSize();
101    lBlkSize = floorLog2(blkSize);
102}
103
104void
105BasePrefetcher::regStats()
106{
107    ClockedObject::regStats();
108
109    pfIssued
110        .name(name() + ".num_hwpf_issued")
111        .desc("number of hwpf issued")
112        ;
113
114}
115
116bool
117BasePrefetcher::observeAccess(const PacketPtr &pkt) const
118{
119    Addr addr = pkt->getAddr();
120    bool fetch = pkt->req->isInstFetch();
121    bool read = pkt->isRead();
122    bool inv = pkt->isInvalidate();
123    bool is_secure = pkt->isSecure();
124
125    if (pkt->req->isUncacheable()) return false;
126    if (fetch && !onInst) return false;
127    if (!fetch && !onData) return false;
128    if (!fetch && read && !onRead) return false;
129    if (!fetch && !read && !onWrite) return false;
130    if (!fetch && !read && inv) return false;
131    if (pkt->cmd == MemCmd::CleanEvict) return false;
132
133    if (onMiss) {
134        return !inCache(addr, is_secure) &&
135               !inMissQueue(addr, is_secure);
136    }
137
138    return true;
139}
140
141bool
142BasePrefetcher::inCache(Addr addr, bool is_secure) const
143{
144    return cache->inCache(addr, is_secure);
145}
146
147bool
148BasePrefetcher::inMissQueue(Addr addr, bool is_secure) const
149{
150    return cache->inMissQueue(addr, is_secure);
151}
152
153bool
154BasePrefetcher::hasBeenPrefetched(Addr addr, bool is_secure) const
155{
156    return cache->hasBeenPrefetched(addr, is_secure);
157}
158
159bool
160BasePrefetcher::samePage(Addr a, Addr b) const
161{
162    return roundDown(a, pageBytes) == roundDown(b, pageBytes);
163}
164
165Addr
166BasePrefetcher::blockAddress(Addr a) const
167{
168    return a & ~((Addr)blkSize-1);
169}
170
171Addr
172BasePrefetcher::blockIndex(Addr a) const
173{
174    return a >> lBlkSize;
175}
176
177Addr
178BasePrefetcher::pageAddress(Addr a) const
179{
180    return roundDown(a, pageBytes);
181}
182
183Addr
184BasePrefetcher::pageOffset(Addr a) const
185{
186    return a & (pageBytes - 1);
187}
188
189Addr
190BasePrefetcher::pageIthBlockAddress(Addr page, uint32_t blockIndex) const
191{
192    return page + (blockIndex << lBlkSize);
193}
194
195void
196BasePrefetcher::probeNotify(const PacketPtr &pkt)
197{
198    // Don't notify prefetcher on SWPrefetch, cache maintenance
199    // operations or for writes that we are coaslescing.
200    if (pkt->cmd.isSWPrefetch()) return;
201    if (pkt->req->isCacheMaintenance()) return;
202    if (pkt->isWrite() && cache != nullptr && cache->coalesce()) return;
203
204    if (hasBeenPrefetched(pkt->getAddr(), pkt->isSecure())) {
205        usefulPrefetches += 1;
206    }
207
208    // Verify this access type is observed by prefetcher
209    if (observeAccess(pkt)) {
210        if (useVirtualAddresses && pkt->req->hasVaddr()) {
211            PrefetchInfo pfi(pkt, pkt->req->getVaddr());
212            notify(pkt, pfi);
213        } else if (!useVirtualAddresses && pkt->req->hasPaddr()) {
214            PrefetchInfo pfi(pkt, pkt->req->getPaddr());
215            notify(pkt, pfi);
216        }
217    }
218}
219
220void
221BasePrefetcher::regProbeListeners()
222{
223    /**
224     * If no probes were added by the configuration scripts, connect to the
225     * parent cache using the probe "Miss". Also connect to "Hit", if the
226     * cache is configured to prefetch on accesses.
227     */
228    if (listeners.empty() && cache != nullptr) {
229        ProbeManager *pm(cache->getProbeManager());
230        listeners.push_back(new PrefetchListener(*this, pm, "Miss"));
231        listeners.push_back(new PrefetchListener(*this, pm, "Fill", true));
232        if (prefetchOnAccess) {
233            listeners.push_back(new PrefetchListener(*this, pm, "Hit"));
234        }
235    }
236}
237
238void
239BasePrefetcher::addEventProbe(SimObject *obj, const char *name)
240{
241    ProbeManager *pm(obj->getProbeManager());
242    listeners.push_back(new PrefetchListener(*this, pm, name));
243}
244