base.cc revision 11793:ef606668d247 
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 *          Mitch Hayenga
42 */
43
44/**
45 * @file
46 * Hardware Prefetcher Definition.
47 */
48
49#include "mem/cache/prefetch/base.hh"
50
51#include <list>
52
53#include "base/intmath.hh"
54#include "mem/cache/base.hh"
55#include "sim/system.hh"
56
57BasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p)
58    : ClockedObject(p), cache(nullptr), blkSize(0), lBlkSize(0),
59      system(p->sys), onMiss(p->on_miss), onRead(p->on_read),
60      onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
61      masterId(system->getMasterId(name())),
62      pageBytes(system->getPageBytes())
63{
64}
65
66void
67BasePrefetcher::setCache(BaseCache *_cache)
68{
69    assert(!cache);
70    cache = _cache;
71    blkSize = cache->getBlockSize();
72    lBlkSize = floorLog2(blkSize);
73}
74
75void
76BasePrefetcher::regStats()
77{
78    ClockedObject::regStats();
79
80    pfIssued
81        .name(name() + ".num_hwpf_issued")
82        .desc("number of hwpf issued")
83        ;
84
85}
86
87bool
88BasePrefetcher::observeAccess(const PacketPtr &pkt) const
89{
90    Addr addr = pkt->getAddr();
91    bool fetch = pkt->req->isInstFetch();
92    bool read = pkt->isRead();
93    bool inv = pkt->isInvalidate();
94    bool is_secure = pkt->isSecure();
95
96    if (pkt->req->isUncacheable()) return false;
97    if (fetch && !onInst) return false;
98    if (!fetch && !onData) return false;
99    if (!fetch && read && !onRead) return false;
100    if (!fetch && !read && !onWrite) return false;
101    if (!fetch && !read && inv) return false;
102    if (pkt->cmd == MemCmd::CleanEvict) return false;
103
104    if (onMiss) {
105        return !inCache(addr, is_secure) &&
106               !inMissQueue(addr, is_secure);
107    }
108
109    return true;
110}
111
112bool
113BasePrefetcher::inCache(Addr addr, bool is_secure) const
114{
115    if (cache->inCache(addr, is_secure)) {
116        return true;
117    }
118    return false;
119}
120
121bool
122BasePrefetcher::inMissQueue(Addr addr, bool is_secure) const
123{
124    if (cache->inMissQueue(addr, is_secure)) {
125        return true;
126    }
127    return false;
128}
129
130bool
131BasePrefetcher::samePage(Addr a, Addr b) const
132{
133    return roundDown(a, pageBytes) == roundDown(b, pageBytes);
134}
135
136Addr
137BasePrefetcher::blockAddress(Addr a) const
138{
139    return a & ~(blkSize-1);
140}
141
142Addr
143BasePrefetcher::blockIndex(Addr a) const
144{
145    return a >> lBlkSize;
146}
147
148Addr
149BasePrefetcher::pageAddress(Addr a) const
150{
151    return roundDown(a, pageBytes);
152}
153
154Addr
155BasePrefetcher::pageOffset(Addr a) const
156{
157    return a & (pageBytes - 1);
158}
159
160Addr
161BasePrefetcher::pageIthBlockAddress(Addr page, uint32_t blockIndex) const
162{
163    return page + (blockIndex << lBlkSize);
164}
165