base.cc revision 8991
12810SN/A/* 22810SN/A * Copyright (c) 2005 The Regents of The University of Michigan 32810SN/A * All rights reserved. 42810SN/A * 52810SN/A * Redistribution and use in source and binary forms, with or without 62810SN/A * modification, are permitted provided that the following conditions are 72810SN/A * met: redistributions of source code must retain the above copyright 82810SN/A * notice, this list of conditions and the following disclaimer; 92810SN/A * redistributions in binary form must reproduce the above copyright 102810SN/A * notice, this list of conditions and the following disclaimer in the 112810SN/A * documentation and/or other materials provided with the distribution; 122810SN/A * neither the name of the copyright holders nor the names of its 132810SN/A * contributors may be used to endorse or promote products derived from 142810SN/A * this software without specific prior written permission. 152810SN/A * 162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810SN/A * 282810SN/A * Authors: Ron Dreslinski 292810SN/A */ 302810SN/A 312810SN/A/** 322810SN/A * @file 332810SN/A * Hardware Prefetcher Definition. 342810SN/A */ 352810SN/A 366658Snate@binkert.org#include <list> 376658Snate@binkert.org 385875Ssteve.reinhardt@amd.com#include "arch/isa_traits.hh" 392810SN/A#include "base/trace.hh" 406658Snate@binkert.org#include "config/the_isa.hh" 418232Snate@binkert.org#include "debug/HWPrefetch.hh" 428229Snate@binkert.org#include "mem/cache/prefetch/base.hh" 435338Sstever@gmail.com#include "mem/cache/base.hh" 442814SN/A#include "mem/request.hh" 458832SAli.Saidi@ARM.com#include "sim/system.hh" 462810SN/A 478831Smrinmoy.ghosh@arm.comBasePrefetcher::BasePrefetcher(const Params *p) 488831Smrinmoy.ghosh@arm.com : SimObject(p), size(p->size), latency(p->latency), degree(p->degree), 498832SAli.Saidi@ARM.com useMasterId(p->use_master_id), pageStop(!p->cross_pages), 508832SAli.Saidi@ARM.com serialSquash(p->serial_squash), onlyData(p->data_accesses_only), 518832SAli.Saidi@ARM.com system(p->sys), masterId(system->getMasterId(name())) 522810SN/A{ 532810SN/A} 542810SN/A 552810SN/Avoid 562810SN/ABasePrefetcher::setCache(BaseCache *_cache) 572810SN/A{ 582810SN/A cache = _cache; 592810SN/A blkSize = cache->getBlockSize(); 602810SN/A} 612810SN/A 622810SN/Avoid 638831Smrinmoy.ghosh@arm.comBasePrefetcher::regStats() 642810SN/A{ 652810SN/A pfIdentified 668831Smrinmoy.ghosh@arm.com .name(name() + ".prefetcher.num_hwpf_identified") 672810SN/A .desc("number of hwpf identified") 682810SN/A ; 692810SN/A 702810SN/A pfMSHRHit 718831Smrinmoy.ghosh@arm.com .name(name() + ".prefetcher.num_hwpf_already_in_mshr") 722810SN/A .desc("number of hwpf that were already in mshr") 732810SN/A ; 742810SN/A 752810SN/A pfCacheHit 768831Smrinmoy.ghosh@arm.com .name(name() + ".prefetcher.num_hwpf_already_in_cache") 772810SN/A .desc("number of hwpf that were already in the cache") 782810SN/A ; 792810SN/A 802810SN/A pfBufferHit 818831Smrinmoy.ghosh@arm.com .name(name() + ".prefetcher.num_hwpf_already_in_prefetcher") 822810SN/A .desc("number of hwpf that were already in the prefetch queue") 832810SN/A ; 842810SN/A 852810SN/A pfRemovedFull 868831Smrinmoy.ghosh@arm.com .name(name() + ".prefetcher.num_hwpf_evicted") 872810SN/A .desc("number of hwpf removed due to no buffer left") 882810SN/A ; 892810SN/A 902810SN/A pfRemovedMSHR 918831Smrinmoy.ghosh@arm.com .name(name() + ".prefetcher.num_hwpf_removed_MSHR_hit") 922810SN/A .desc("number of hwpf removed because MSHR allocated") 932810SN/A ; 942810SN/A 952810SN/A pfIssued 968831Smrinmoy.ghosh@arm.com .name(name() + ".prefetcher.num_hwpf_issued") 972810SN/A .desc("number of hwpf issued") 982810SN/A ; 992810SN/A 1002810SN/A pfSpanPage 1018831Smrinmoy.ghosh@arm.com .name(name() + ".prefetcher.num_hwpf_span_page") 1022810SN/A .desc("number of hwpf spanning a virtual page") 1032810SN/A ; 1042810SN/A 1052810SN/A pfSquashed 1068831Smrinmoy.ghosh@arm.com .name(name() + ".prefetcher.num_hwpf_squashed_from_miss") 1075875Ssteve.reinhardt@amd.com .desc("number of hwpf that got squashed due to a miss " 1085875Ssteve.reinhardt@amd.com "aborting calculation time") 1092810SN/A ; 1102810SN/A} 1112810SN/A 1123861SN/Ainline bool 1133861SN/ABasePrefetcher::inCache(Addr addr) 1143861SN/A{ 1153861SN/A if (cache->inCache(addr)) { 1163861SN/A pfCacheHit++; 1173861SN/A return true; 1183861SN/A } 1193861SN/A return false; 1203861SN/A} 1213861SN/A 1223861SN/Ainline bool 1233861SN/ABasePrefetcher::inMissQueue(Addr addr) 1243861SN/A{ 1253861SN/A if (cache->inMissQueue(addr)) { 1263861SN/A pfMSHRHit++; 1273861SN/A return true; 1283861SN/A } 1293861SN/A return false; 1303861SN/A} 1313861SN/A 1323349SN/APacketPtr 1332810SN/ABasePrefetcher::getPacket() 1342810SN/A{ 1355875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, "Requesting a hw_pf to issue\n"); 1362810SN/A 1372810SN/A if (pf.empty()) { 1385875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, "No HW_PF found\n"); 1392810SN/A return NULL; 1402810SN/A } 1412810SN/A 1428533SLisa.Hsu@amd.com PacketPtr pkt = *pf.begin(); 1438509SAli.Saidi@ARM.com while (!pf.empty()) { 1442810SN/A pkt = *pf.begin(); 1452810SN/A pf.pop_front(); 1465875Ssteve.reinhardt@amd.com 1478509SAli.Saidi@ARM.com Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1); 1488509SAli.Saidi@ARM.com 1498509SAli.Saidi@ARM.com if (!inCache(blk_addr) && !inMissQueue(blk_addr)) 1508509SAli.Saidi@ARM.com // we found a prefetch, return it 1518509SAli.Saidi@ARM.com break; 1528509SAli.Saidi@ARM.com 1538509SAli.Saidi@ARM.com DPRINTF(HWPrefetch, "addr 0x%x in cache, skipping\n", pkt->getAddr()); 1548509SAli.Saidi@ARM.com delete pkt->req; 1558509SAli.Saidi@ARM.com delete pkt; 1565875Ssteve.reinhardt@amd.com 1572810SN/A if (pf.empty()) { 1584628SN/A cache->deassertMemSideBusRequest(BaseCache::Request_PF); 1598509SAli.Saidi@ARM.com return NULL; // None left, all were in cache 1602810SN/A } 1618509SAli.Saidi@ARM.com } 1622810SN/A 1632810SN/A pfIssued++; 1645875Ssteve.reinhardt@amd.com assert(pkt != NULL); 1655875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, "returning 0x%x\n", pkt->getAddr()); 1662810SN/A return pkt; 1672810SN/A} 1682810SN/A 1695875Ssteve.reinhardt@amd.com 1705875Ssteve.reinhardt@amd.comTick 1715875Ssteve.reinhardt@amd.comBasePrefetcher::notify(PacketPtr &pkt, Tick time) 1722810SN/A{ 1736105Ssteve.reinhardt@amd.com if (!pkt->req->isUncacheable() && !(pkt->req->isInstFetch() && onlyData)) { 1745875Ssteve.reinhardt@amd.com // Calculate the blk address 1755875Ssteve.reinhardt@amd.com Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1); 1762810SN/A 1775875Ssteve.reinhardt@amd.com // Check if miss is in pfq, if so remove it 1785875Ssteve.reinhardt@amd.com std::list<PacketPtr>::iterator iter = inPrefetch(blk_addr); 1792810SN/A if (iter != pf.end()) { 1805875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, "Saw a miss to a queued prefetch addr: " 1815875Ssteve.reinhardt@amd.com "0x%x, removing it\n", blk_addr); 1822810SN/A pfRemovedMSHR++; 1835875Ssteve.reinhardt@amd.com delete (*iter)->req; 1845875Ssteve.reinhardt@amd.com delete (*iter); 1858991SAli.Saidi@ARM.com iter = pf.erase(iter); 1862810SN/A if (pf.empty()) 1874628SN/A cache->deassertMemSideBusRequest(BaseCache::Request_PF); 1882810SN/A } 1892810SN/A 1905875Ssteve.reinhardt@amd.com // Remove anything in queue with delay older than time 1915875Ssteve.reinhardt@amd.com // since everything is inserted in time order, start from end 1925875Ssteve.reinhardt@amd.com // and work until pf.empty() or time is earlier 1935875Ssteve.reinhardt@amd.com // This is done to emulate Aborting the previous work on a new miss 1945875Ssteve.reinhardt@amd.com // Needed for serial calculators like GHB 1952810SN/A if (serialSquash) { 1962810SN/A iter = pf.end(); 1978991SAli.Saidi@ARM.com if (iter != pf.begin()) 1988991SAli.Saidi@ARM.com iter--; 1992810SN/A while (!pf.empty() && ((*iter)->time >= time)) { 2002810SN/A pfSquashed++; 2015875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, "Squashing old prefetch addr: 0x%x\n", 2025875Ssteve.reinhardt@amd.com (*iter)->getAddr()); 2035875Ssteve.reinhardt@amd.com delete (*iter)->req; 2045875Ssteve.reinhardt@amd.com delete (*iter); 2058991SAli.Saidi@ARM.com iter = pf.erase(iter); 2068991SAli.Saidi@ARM.com if (iter != pf.begin()) 2078991SAli.Saidi@ARM.com iter--; 2082810SN/A } 2092810SN/A if (pf.empty()) 2104628SN/A cache->deassertMemSideBusRequest(BaseCache::Request_PF); 2112810SN/A } 2122810SN/A 2132810SN/A 2142810SN/A std::list<Addr> addresses; 2152810SN/A std::list<Tick> delays; 2162810SN/A calculatePrefetch(pkt, addresses, delays); 2172810SN/A 2185875Ssteve.reinhardt@amd.com std::list<Addr>::iterator addrIter = addresses.begin(); 2195875Ssteve.reinhardt@amd.com std::list<Tick>::iterator delayIter = delays.begin(); 2205875Ssteve.reinhardt@amd.com for (; addrIter != addresses.end(); ++addrIter, ++delayIter) { 2215875Ssteve.reinhardt@amd.com Addr addr = *addrIter; 2225875Ssteve.reinhardt@amd.com 2232810SN/A pfIdentified++; 2245875Ssteve.reinhardt@amd.com 2255875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, "Found a pf candidate addr: 0x%x, " 2265875Ssteve.reinhardt@amd.com "inserting into prefetch queue with delay %d time %d\n", 2275875Ssteve.reinhardt@amd.com addr, *delayIter, time); 2285875Ssteve.reinhardt@amd.com 2295875Ssteve.reinhardt@amd.com // Check if it is already in the pf buffer 2305875Ssteve.reinhardt@amd.com if (inPrefetch(addr) != pf.end()) { 2315875Ssteve.reinhardt@amd.com pfBufferHit++; 2325875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, "Prefetch addr already in pf buffer\n"); 2335875Ssteve.reinhardt@amd.com continue; 2345875Ssteve.reinhardt@amd.com } 2355875Ssteve.reinhardt@amd.com 2365875Ssteve.reinhardt@amd.com // create a prefetch memreq 2378832SAli.Saidi@ARM.com Request *prefetchReq = new Request(*addrIter, blkSize, 0, masterId); 2385875Ssteve.reinhardt@amd.com PacketPtr prefetch = 2398949Sandreas.hansson@arm.com new Packet(prefetchReq, MemCmd::HardPFReq); 2402825SN/A prefetch->allocate(); 2415714Shsul@eecs.umich.edu prefetch->req->setThreadContext(pkt->req->contextId(), 2425714Shsul@eecs.umich.edu pkt->req->threadId()); 2432814SN/A 2445875Ssteve.reinhardt@amd.com prefetch->time = time + (*delayIter); // @todo ADD LATENCY HERE 2452810SN/A 2465875Ssteve.reinhardt@amd.com // We just remove the head if we are full 2475875Ssteve.reinhardt@amd.com if (pf.size() == size) { 2482810SN/A pfRemovedFull++; 2495875Ssteve.reinhardt@amd.com PacketPtr old_pkt = *pf.begin(); 2505875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, "Prefetch queue full, " 2515875Ssteve.reinhardt@amd.com "removing oldest 0x%x\n", old_pkt->getAddr()); 2525875Ssteve.reinhardt@amd.com delete old_pkt->req; 2535875Ssteve.reinhardt@amd.com delete old_pkt; 2542810SN/A pf.pop_front(); 2552810SN/A } 2562810SN/A 2572810SN/A pf.push_back(prefetch); 2582810SN/A } 2592810SN/A } 2605875Ssteve.reinhardt@amd.com 2615875Ssteve.reinhardt@amd.com return pf.empty() ? 0 : pf.front()->time; 2622810SN/A} 2632810SN/A 2643349SN/Astd::list<PacketPtr>::iterator 2652810SN/ABasePrefetcher::inPrefetch(Addr address) 2662810SN/A{ 2675875Ssteve.reinhardt@amd.com // Guaranteed to only be one match, we always check before inserting 2683349SN/A std::list<PacketPtr>::iterator iter; 2695875Ssteve.reinhardt@amd.com for (iter = pf.begin(); iter != pf.end(); iter++) { 2702814SN/A if (((*iter)->getAddr() & ~(Addr)(blkSize-1)) == address) { 2712810SN/A return iter; 2722810SN/A } 2732810SN/A } 2742810SN/A return pf.end(); 2752810SN/A} 2762810SN/A 2775875Ssteve.reinhardt@amd.combool 2785875Ssteve.reinhardt@amd.comBasePrefetcher::samePage(Addr a, Addr b) 2795875Ssteve.reinhardt@amd.com{ 2805875Ssteve.reinhardt@amd.com return roundDown(a, TheISA::VMPageSize) == roundDown(b, TheISA::VMPageSize); 2815875Ssteve.reinhardt@amd.com} 2828831Smrinmoy.ghosh@arm.com 2838831Smrinmoy.ghosh@arm.com 284