base.cc revision 13434
112968Sgiacomo.travaglini@arm.com/* 212968Sgiacomo.travaglini@arm.com * Copyright (c) 2013-2014 ARM Limited 312968Sgiacomo.travaglini@arm.com * All rights reserved. 412968Sgiacomo.travaglini@arm.com * 512968Sgiacomo.travaglini@arm.com * The license below extends only to copyright in the software and shall 612968Sgiacomo.travaglini@arm.com * not be construed as granting a license to any other intellectual 712968Sgiacomo.travaglini@arm.com * property including but not limited to intellectual property relating 812968Sgiacomo.travaglini@arm.com * to a hardware implementation of the functionality of the software 912968Sgiacomo.travaglini@arm.com * licensed hereunder. You may use the software subject to the license 1012968Sgiacomo.travaglini@arm.com * terms below provided that you ensure that this notice is replicated 1112968Sgiacomo.travaglini@arm.com * unmodified and in its entirety in all distributions of the software, 1212968Sgiacomo.travaglini@arm.com * modified or unmodified, in source code or in binary form. 1312968Sgiacomo.travaglini@arm.com * 1412968Sgiacomo.travaglini@arm.com * Copyright (c) 2005 The Regents of The University of Michigan 1512968Sgiacomo.travaglini@arm.com * All rights reserved. 1612968Sgiacomo.travaglini@arm.com * 1712968Sgiacomo.travaglini@arm.com * Redistribution and use in source and binary forms, with or without 1812968Sgiacomo.travaglini@arm.com * modification, are permitted provided that the following conditions are 1912968Sgiacomo.travaglini@arm.com * met: redistributions of source code must retain the above copyright 2012968Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer; 2112968Sgiacomo.travaglini@arm.com * redistributions in binary form must reproduce the above copyright 2212968Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer in the 2312968Sgiacomo.travaglini@arm.com * documentation and/or other materials provided with the distribution; 2412968Sgiacomo.travaglini@arm.com * neither the name of the copyright holders nor the names of its 2512968Sgiacomo.travaglini@arm.com * contributors may be used to endorse or promote products derived from 2612968Sgiacomo.travaglini@arm.com * this software without specific prior written permission. 2712968Sgiacomo.travaglini@arm.com * 2812968Sgiacomo.travaglini@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2912968Sgiacomo.travaglini@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3012968Sgiacomo.travaglini@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3112968Sgiacomo.travaglini@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3212968Sgiacomo.travaglini@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3312968Sgiacomo.travaglini@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3412968Sgiacomo.travaglini@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3512968Sgiacomo.travaglini@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3612968Sgiacomo.travaglini@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3712968Sgiacomo.travaglini@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3812968Sgiacomo.travaglini@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3912968Sgiacomo.travaglini@arm.com * 4012968Sgiacomo.travaglini@arm.com * Authors: Ron Dreslinski 4112968Sgiacomo.travaglini@arm.com * Mitch Hayenga 4212968Sgiacomo.travaglini@arm.com */ 4312968Sgiacomo.travaglini@arm.com 4412968Sgiacomo.travaglini@arm.com/** 4512968Sgiacomo.travaglini@arm.com * @file 4612968Sgiacomo.travaglini@arm.com * Hardware Prefetcher Definition. 4712968Sgiacomo.travaglini@arm.com */ 4812968Sgiacomo.travaglini@arm.com 4912968Sgiacomo.travaglini@arm.com#include "mem/cache/prefetch/base.hh" 5012968Sgiacomo.travaglini@arm.com 5112968Sgiacomo.travaglini@arm.com#include <cassert> 5212968Sgiacomo.travaglini@arm.com 5312968Sgiacomo.travaglini@arm.com#include "base/intmath.hh" 5412968Sgiacomo.travaglini@arm.com#include "cpu/base.hh" 5512968Sgiacomo.travaglini@arm.com#include "mem/cache/base.hh" 5612968Sgiacomo.travaglini@arm.com#include "params/BasePrefetcher.hh" 5712968Sgiacomo.travaglini@arm.com#include "sim/system.hh" 5812968Sgiacomo.travaglini@arm.com 5912968Sgiacomo.travaglini@arm.comvoid 6012968Sgiacomo.travaglini@arm.comBasePrefetcher::PrefetchListener::notify(const PacketPtr &pkt) 6112968Sgiacomo.travaglini@arm.com{ 6212968Sgiacomo.travaglini@arm.com parent.probeNotify(pkt); 6312968Sgiacomo.travaglini@arm.com} 6412968Sgiacomo.travaglini@arm.com 6512968Sgiacomo.travaglini@arm.comBasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p) 6612968Sgiacomo.travaglini@arm.com : ClockedObject(p), listeners(), cache(nullptr), blkSize(p->block_size), 6712968Sgiacomo.travaglini@arm.com lBlkSize(floorLog2(blkSize)), onMiss(p->on_miss), onRead(p->on_read), 6812968Sgiacomo.travaglini@arm.com onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst), 6912968Sgiacomo.travaglini@arm.com masterId(p->sys->getMasterId(this)), pageBytes(p->sys->getPageBytes()), 7012968Sgiacomo.travaglini@arm.com prefetchOnAccess(p->prefetch_on_access) 7112968Sgiacomo.travaglini@arm.com{ 7212968Sgiacomo.travaglini@arm.com} 7312968Sgiacomo.travaglini@arm.com 7412968Sgiacomo.travaglini@arm.comvoid 7512968Sgiacomo.travaglini@arm.comBasePrefetcher::setCache(BaseCache *_cache) 7612968Sgiacomo.travaglini@arm.com{ 7712968Sgiacomo.travaglini@arm.com assert(!cache); 7812968Sgiacomo.travaglini@arm.com cache = _cache; 7912968Sgiacomo.travaglini@arm.com 8012968Sgiacomo.travaglini@arm.com // If the cache has a different block size from the system's, save it 8112968Sgiacomo.travaglini@arm.com blkSize = cache->getBlockSize(); 8212968Sgiacomo.travaglini@arm.com lBlkSize = floorLog2(blkSize); 8312968Sgiacomo.travaglini@arm.com} 8412968Sgiacomo.travaglini@arm.com 8512968Sgiacomo.travaglini@arm.comvoid 8612968Sgiacomo.travaglini@arm.comBasePrefetcher::regStats() 8712968Sgiacomo.travaglini@arm.com{ 8812968Sgiacomo.travaglini@arm.com ClockedObject::regStats(); 8912968Sgiacomo.travaglini@arm.com 9012968Sgiacomo.travaglini@arm.com pfIssued 9112968Sgiacomo.travaglini@arm.com .name(name() + ".num_hwpf_issued") 9212968Sgiacomo.travaglini@arm.com .desc("number of hwpf issued") 9312968Sgiacomo.travaglini@arm.com ; 9412968Sgiacomo.travaglini@arm.com 9512968Sgiacomo.travaglini@arm.com} 9612968Sgiacomo.travaglini@arm.com 9712968Sgiacomo.travaglini@arm.combool 9812968Sgiacomo.travaglini@arm.comBasePrefetcher::observeAccess(const PacketPtr &pkt) const 9912968Sgiacomo.travaglini@arm.com{ 10012968Sgiacomo.travaglini@arm.com Addr addr = pkt->getAddr(); 10112968Sgiacomo.travaglini@arm.com bool fetch = pkt->req->isInstFetch(); 102 bool read = pkt->isRead(); 103 bool inv = pkt->isInvalidate(); 104 bool is_secure = pkt->isSecure(); 105 106 if (pkt->req->isUncacheable()) return false; 107 if (fetch && !onInst) return false; 108 if (!fetch && !onData) return false; 109 if (!fetch && read && !onRead) return false; 110 if (!fetch && !read && !onWrite) return false; 111 if (!fetch && !read && inv) return false; 112 if (pkt->cmd == MemCmd::CleanEvict) return false; 113 114 if (onMiss) { 115 return !inCache(addr, is_secure) && 116 !inMissQueue(addr, is_secure); 117 } 118 119 return true; 120} 121 122bool 123BasePrefetcher::inCache(Addr addr, bool is_secure) const 124{ 125 return cache->inCache(addr, is_secure); 126} 127 128bool 129BasePrefetcher::inMissQueue(Addr addr, bool is_secure) const 130{ 131 return cache->inMissQueue(addr, is_secure); 132} 133 134bool 135BasePrefetcher::samePage(Addr a, Addr b) const 136{ 137 return roundDown(a, pageBytes) == roundDown(b, pageBytes); 138} 139 140Addr 141BasePrefetcher::blockAddress(Addr a) const 142{ 143 return a & ~((Addr)blkSize-1); 144} 145 146Addr 147BasePrefetcher::blockIndex(Addr a) const 148{ 149 return a >> lBlkSize; 150} 151 152Addr 153BasePrefetcher::pageAddress(Addr a) const 154{ 155 return roundDown(a, pageBytes); 156} 157 158Addr 159BasePrefetcher::pageOffset(Addr a) const 160{ 161 return a & (pageBytes - 1); 162} 163 164Addr 165BasePrefetcher::pageIthBlockAddress(Addr page, uint32_t blockIndex) const 166{ 167 return page + (blockIndex << lBlkSize); 168} 169 170void 171BasePrefetcher::probeNotify(const PacketPtr &pkt) 172{ 173 // Don't notify prefetcher on SWPrefetch, cache maintenance 174 // operations or for writes that we are coaslescing. 175 if (pkt->cmd.isSWPrefetch()) return; 176 if (pkt->req->isCacheMaintenance()) return; 177 if (pkt->isWrite() && cache != nullptr && cache->coalesce()) return; 178 notify(pkt); 179} 180 181void 182BasePrefetcher::regProbeListeners() 183{ 184 /** 185 * If no probes were added by the configuration scripts, connect to the 186 * parent cache using the probe "Miss". Also connect to "Hit", if the 187 * cache is configured to prefetch on accesses. 188 */ 189 if (listeners.empty() && cache != nullptr) { 190 ProbeManager *pm(cache->getProbeManager()); 191 listeners.push_back(new PrefetchListener(*this, pm, "Miss")); 192 if (prefetchOnAccess) { 193 listeners.push_back(new PrefetchListener(*this, pm, "Hit")); 194 } 195 } 196} 197 198void 199BasePrefetcher::addEventProbe(SimObject *obj, const char *name) 200{ 201 ProbeManager *pm(obj->getProbeManager()); 202 listeners.push_back(new PrefetchListener(*this, pm, name)); 203} 204