base.cc revision 13422
12810SN/A/* 210623Smitch.hayenga@arm.com * Copyright (c) 2013-2014 ARM Limited 39546Sandreas.hansson@arm.com * All rights reserved. 49546Sandreas.hansson@arm.com * 59546Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 69546Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 79546Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 89546Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 99546Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 109546Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 119546Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 129546Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 139546Sandreas.hansson@arm.com * 142810SN/A * Copyright (c) 2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Ron Dreslinski 4110623Smitch.hayenga@arm.com * Mitch Hayenga 422810SN/A */ 432810SN/A 442810SN/A/** 452810SN/A * @file 462810SN/A * Hardware Prefetcher Definition. 472810SN/A */ 482810SN/A 4911793Sbrandon.potter@amd.com#include "mem/cache/prefetch/base.hh" 5011793Sbrandon.potter@amd.com 5112727Snikos.nikoleris@arm.com#include <cassert> 526658Snate@binkert.org 5311438SRekai.GonzalezAlberquilla@arm.com#include "base/intmath.hh" 5413416Sjavier.bueno@metempsy.com#include "cpu/base.hh" 555338Sstever@gmail.com#include "mem/cache/base.hh" 5612727Snikos.nikoleris@arm.com#include "params/BasePrefetcher.hh" 578832SAli.Saidi@ARM.com#include "sim/system.hh" 582810SN/A 5913416Sjavier.bueno@metempsy.comvoid 6013416Sjavier.bueno@metempsy.comBasePrefetcher::PrefetchListener::notify(const PacketPtr &pkt) 6113416Sjavier.bueno@metempsy.com{ 6213416Sjavier.bueno@metempsy.com parent.probeNotify(pkt); 6313416Sjavier.bueno@metempsy.com} 6413416Sjavier.bueno@metempsy.com 6510623Smitch.hayenga@arm.comBasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p) 6613422Sodanrc@yahoo.com.br : ClockedObject(p), listeners(), cache(nullptr), blkSize(p->block_size), 6713422Sodanrc@yahoo.com.br lBlkSize(floorLog2(blkSize)), onMiss(p->on_miss), onRead(p->on_read), 6810623Smitch.hayenga@arm.com onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst), 6913422Sodanrc@yahoo.com.br masterId(p->sys->getMasterId(this)), pageBytes(p->sys->getPageBytes()), 7013416Sjavier.bueno@metempsy.com prefetchOnAccess(p->prefetch_on_access) 712810SN/A{ 722810SN/A} 732810SN/A 742810SN/Avoid 752810SN/ABasePrefetcher::setCache(BaseCache *_cache) 762810SN/A{ 7710360Sandreas.hansson@arm.com assert(!cache); 782810SN/A cache = _cache; 7913422Sodanrc@yahoo.com.br 8013422Sodanrc@yahoo.com.br // If the cache has a different block size from the system's, save it 812810SN/A blkSize = cache->getBlockSize(); 8211438SRekai.GonzalezAlberquilla@arm.com lBlkSize = floorLog2(blkSize); 832810SN/A} 842810SN/A 852810SN/Avoid 868831Smrinmoy.ghosh@arm.comBasePrefetcher::regStats() 872810SN/A{ 8811522Sstephan.diestelhorst@arm.com ClockedObject::regStats(); 8911522Sstephan.diestelhorst@arm.com 902810SN/A pfIssued 9110623Smitch.hayenga@arm.com .name(name() + ".num_hwpf_issued") 922810SN/A .desc("number of hwpf issued") 932810SN/A ; 9411438SRekai.GonzalezAlberquilla@arm.com 952810SN/A} 962810SN/A 9710623Smitch.hayenga@arm.combool 9810623Smitch.hayenga@arm.comBasePrefetcher::observeAccess(const PacketPtr &pkt) const 9910623Smitch.hayenga@arm.com{ 10010623Smitch.hayenga@arm.com Addr addr = pkt->getAddr(); 10110623Smitch.hayenga@arm.com bool fetch = pkt->req->isInstFetch(); 10210626SCurtis.Dunham@arm.com bool read = pkt->isRead(); 10310626SCurtis.Dunham@arm.com bool inv = pkt->isInvalidate(); 10410623Smitch.hayenga@arm.com bool is_secure = pkt->isSecure(); 10510623Smitch.hayenga@arm.com 10610623Smitch.hayenga@arm.com if (pkt->req->isUncacheable()) return false; 10710623Smitch.hayenga@arm.com if (fetch && !onInst) return false; 10810623Smitch.hayenga@arm.com if (!fetch && !onData) return false; 10910623Smitch.hayenga@arm.com if (!fetch && read && !onRead) return false; 11010623Smitch.hayenga@arm.com if (!fetch && !read && !onWrite) return false; 11110626SCurtis.Dunham@arm.com if (!fetch && !read && inv) return false; 11210883Sali.jafri@arm.com if (pkt->cmd == MemCmd::CleanEvict) return false; 11310623Smitch.hayenga@arm.com 11410623Smitch.hayenga@arm.com if (onMiss) { 11510623Smitch.hayenga@arm.com return !inCache(addr, is_secure) && 11610623Smitch.hayenga@arm.com !inMissQueue(addr, is_secure); 11710623Smitch.hayenga@arm.com } 11810623Smitch.hayenga@arm.com 11910623Smitch.hayenga@arm.com return true; 12010623Smitch.hayenga@arm.com} 12110623Smitch.hayenga@arm.com 12210623Smitch.hayenga@arm.combool 12310623Smitch.hayenga@arm.comBasePrefetcher::inCache(Addr addr, bool is_secure) const 1243861SN/A{ 12513422Sodanrc@yahoo.com.br return cache->inCache(addr, is_secure); 1263861SN/A} 1273861SN/A 12810623Smitch.hayenga@arm.combool 12910623Smitch.hayenga@arm.comBasePrefetcher::inMissQueue(Addr addr, bool is_secure) const 1303861SN/A{ 13113422Sodanrc@yahoo.com.br return cache->inMissQueue(addr, is_secure); 1323861SN/A} 1333861SN/A 1345875Ssteve.reinhardt@amd.combool 13510466Sandreas.hansson@arm.comBasePrefetcher::samePage(Addr a, Addr b) const 1365875Ssteve.reinhardt@amd.com{ 13710466Sandreas.hansson@arm.com return roundDown(a, pageBytes) == roundDown(b, pageBytes); 1385875Ssteve.reinhardt@amd.com} 1398831Smrinmoy.ghosh@arm.com 14011438SRekai.GonzalezAlberquilla@arm.comAddr 14111438SRekai.GonzalezAlberquilla@arm.comBasePrefetcher::blockAddress(Addr a) const 14211438SRekai.GonzalezAlberquilla@arm.com{ 14311438SRekai.GonzalezAlberquilla@arm.com return a & ~(blkSize-1); 14411438SRekai.GonzalezAlberquilla@arm.com} 1458831Smrinmoy.ghosh@arm.com 14611438SRekai.GonzalezAlberquilla@arm.comAddr 14711438SRekai.GonzalezAlberquilla@arm.comBasePrefetcher::blockIndex(Addr a) const 14811438SRekai.GonzalezAlberquilla@arm.com{ 14911438SRekai.GonzalezAlberquilla@arm.com return a >> lBlkSize; 15011438SRekai.GonzalezAlberquilla@arm.com} 15111438SRekai.GonzalezAlberquilla@arm.com 15211438SRekai.GonzalezAlberquilla@arm.comAddr 15311438SRekai.GonzalezAlberquilla@arm.comBasePrefetcher::pageAddress(Addr a) const 15411438SRekai.GonzalezAlberquilla@arm.com{ 15511438SRekai.GonzalezAlberquilla@arm.com return roundDown(a, pageBytes); 15611438SRekai.GonzalezAlberquilla@arm.com} 15711438SRekai.GonzalezAlberquilla@arm.com 15811438SRekai.GonzalezAlberquilla@arm.comAddr 15911438SRekai.GonzalezAlberquilla@arm.comBasePrefetcher::pageOffset(Addr a) const 16011438SRekai.GonzalezAlberquilla@arm.com{ 16111438SRekai.GonzalezAlberquilla@arm.com return a & (pageBytes - 1); 16211438SRekai.GonzalezAlberquilla@arm.com} 16311438SRekai.GonzalezAlberquilla@arm.com 16411438SRekai.GonzalezAlberquilla@arm.comAddr 16511438SRekai.GonzalezAlberquilla@arm.comBasePrefetcher::pageIthBlockAddress(Addr page, uint32_t blockIndex) const 16611438SRekai.GonzalezAlberquilla@arm.com{ 16711438SRekai.GonzalezAlberquilla@arm.com return page + (blockIndex << lBlkSize); 16811438SRekai.GonzalezAlberquilla@arm.com} 16913416Sjavier.bueno@metempsy.com 17013416Sjavier.bueno@metempsy.comvoid 17113416Sjavier.bueno@metempsy.comBasePrefetcher::probeNotify(const PacketPtr &pkt) 17213416Sjavier.bueno@metempsy.com{ 17313416Sjavier.bueno@metempsy.com // Don't notify prefetcher on SWPrefetch, cache maintenance 17413416Sjavier.bueno@metempsy.com // operations or for writes that we are coaslescing. 17513416Sjavier.bueno@metempsy.com if (pkt->cmd.isSWPrefetch()) return; 17613416Sjavier.bueno@metempsy.com if (pkt->req->isCacheMaintenance()) return; 17713416Sjavier.bueno@metempsy.com if (pkt->isWrite() && cache != nullptr && cache->coalesce()) return; 17813416Sjavier.bueno@metempsy.com notify(pkt); 17913416Sjavier.bueno@metempsy.com} 18013416Sjavier.bueno@metempsy.com 18113416Sjavier.bueno@metempsy.comvoid 18213416Sjavier.bueno@metempsy.comBasePrefetcher::regProbeListeners() 18313416Sjavier.bueno@metempsy.com{ 18413416Sjavier.bueno@metempsy.com /** 18513416Sjavier.bueno@metempsy.com * If no probes were added by the configuration scripts, connect to the 18613416Sjavier.bueno@metempsy.com * parent cache using the probe "Miss". Also connect to "Hit", if the 18713416Sjavier.bueno@metempsy.com * cache is configured to prefetch on accesses. 18813416Sjavier.bueno@metempsy.com */ 18913416Sjavier.bueno@metempsy.com if (listeners.empty() && cache != nullptr) { 19013416Sjavier.bueno@metempsy.com ProbeManager *pm(cache->getProbeManager()); 19113416Sjavier.bueno@metempsy.com listeners.push_back(new PrefetchListener(*this, pm, "Miss")); 19213416Sjavier.bueno@metempsy.com if (prefetchOnAccess) { 19313416Sjavier.bueno@metempsy.com listeners.push_back(new PrefetchListener(*this, pm, "Hit")); 19413416Sjavier.bueno@metempsy.com } 19513416Sjavier.bueno@metempsy.com } 19613416Sjavier.bueno@metempsy.com} 19713416Sjavier.bueno@metempsy.com 19813416Sjavier.bueno@metempsy.comvoid 19913416Sjavier.bueno@metempsy.comBasePrefetcher::addEventProbe(SimObject *obj, const char *name) 20013416Sjavier.bueno@metempsy.com{ 20113416Sjavier.bueno@metempsy.com ProbeManager *pm(obj->getProbeManager()); 20213416Sjavier.bueno@metempsy.com listeners.push_back(new PrefetchListener(*this, pm, name)); 20313416Sjavier.bueno@metempsy.com} 204