base.cc revision 10024
12810SN/A/* 29546Sandreas.hansson@arm.com * Copyright (c) 2013 ARM Limited 39546Sandreas.hansson@arm.com * All rights reserved. 49546Sandreas.hansson@arm.com * 59546Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 69546Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 79546Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 89546Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 99546Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 109546Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 119546Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 129546Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 139546Sandreas.hansson@arm.com * 142810SN/A * Copyright (c) 2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Ron Dreslinski 412810SN/A */ 422810SN/A 432810SN/A/** 442810SN/A * @file 452810SN/A * Hardware Prefetcher Definition. 462810SN/A */ 472810SN/A 486658Snate@binkert.org#include <list> 496658Snate@binkert.org 505875Ssteve.reinhardt@amd.com#include "arch/isa_traits.hh" 512810SN/A#include "base/trace.hh" 526658Snate@binkert.org#include "config/the_isa.hh" 538232Snate@binkert.org#include "debug/HWPrefetch.hh" 548229Snate@binkert.org#include "mem/cache/prefetch/base.hh" 555338Sstever@gmail.com#include "mem/cache/base.hh" 562814SN/A#include "mem/request.hh" 578832SAli.Saidi@ARM.com#include "sim/system.hh" 582810SN/A 598831Smrinmoy.ghosh@arm.comBasePrefetcher::BasePrefetcher(const Params *p) 609288Sandreas.hansson@arm.com : ClockedObject(p), size(p->size), latency(p->latency), degree(p->degree), 618832SAli.Saidi@ARM.com useMasterId(p->use_master_id), pageStop(!p->cross_pages), 628832SAli.Saidi@ARM.com serialSquash(p->serial_squash), onlyData(p->data_accesses_only), 638832SAli.Saidi@ARM.com system(p->sys), masterId(system->getMasterId(name())) 642810SN/A{ 652810SN/A} 662810SN/A 672810SN/Avoid 682810SN/ABasePrefetcher::setCache(BaseCache *_cache) 692810SN/A{ 702810SN/A cache = _cache; 712810SN/A blkSize = cache->getBlockSize(); 722810SN/A} 732810SN/A 742810SN/Avoid 758831Smrinmoy.ghosh@arm.comBasePrefetcher::regStats() 762810SN/A{ 772810SN/A pfIdentified 788831Smrinmoy.ghosh@arm.com .name(name() + ".prefetcher.num_hwpf_identified") 792810SN/A .desc("number of hwpf identified") 802810SN/A ; 812810SN/A 822810SN/A pfMSHRHit 838831Smrinmoy.ghosh@arm.com .name(name() + ".prefetcher.num_hwpf_already_in_mshr") 842810SN/A .desc("number of hwpf that were already in mshr") 852810SN/A ; 862810SN/A 872810SN/A pfCacheHit 888831Smrinmoy.ghosh@arm.com .name(name() + ".prefetcher.num_hwpf_already_in_cache") 892810SN/A .desc("number of hwpf that were already in the cache") 902810SN/A ; 912810SN/A 922810SN/A pfBufferHit 938831Smrinmoy.ghosh@arm.com .name(name() + ".prefetcher.num_hwpf_already_in_prefetcher") 942810SN/A .desc("number of hwpf that were already in the prefetch queue") 952810SN/A ; 962810SN/A 972810SN/A pfRemovedFull 988831Smrinmoy.ghosh@arm.com .name(name() + ".prefetcher.num_hwpf_evicted") 992810SN/A .desc("number of hwpf removed due to no buffer left") 1002810SN/A ; 1012810SN/A 1022810SN/A pfRemovedMSHR 1038831Smrinmoy.ghosh@arm.com .name(name() + ".prefetcher.num_hwpf_removed_MSHR_hit") 1042810SN/A .desc("number of hwpf removed because MSHR allocated") 1052810SN/A ; 1062810SN/A 1072810SN/A pfIssued 1088831Smrinmoy.ghosh@arm.com .name(name() + ".prefetcher.num_hwpf_issued") 1092810SN/A .desc("number of hwpf issued") 1102810SN/A ; 1112810SN/A 1122810SN/A pfSpanPage 1138831Smrinmoy.ghosh@arm.com .name(name() + ".prefetcher.num_hwpf_span_page") 1142810SN/A .desc("number of hwpf spanning a virtual page") 1152810SN/A ; 1162810SN/A 1172810SN/A pfSquashed 1188831Smrinmoy.ghosh@arm.com .name(name() + ".prefetcher.num_hwpf_squashed_from_miss") 1195875Ssteve.reinhardt@amd.com .desc("number of hwpf that got squashed due to a miss " 1205875Ssteve.reinhardt@amd.com "aborting calculation time") 1212810SN/A ; 1222810SN/A} 1232810SN/A 1243861SN/Ainline bool 1253861SN/ABasePrefetcher::inCache(Addr addr) 1263861SN/A{ 1273861SN/A if (cache->inCache(addr)) { 1283861SN/A pfCacheHit++; 1293861SN/A return true; 1303861SN/A } 1313861SN/A return false; 1323861SN/A} 1333861SN/A 1343861SN/Ainline bool 1353861SN/ABasePrefetcher::inMissQueue(Addr addr) 1363861SN/A{ 1373861SN/A if (cache->inMissQueue(addr)) { 1383861SN/A pfMSHRHit++; 1393861SN/A return true; 1403861SN/A } 1413861SN/A return false; 1423861SN/A} 1433861SN/A 1443349SN/APacketPtr 1452810SN/ABasePrefetcher::getPacket() 1462810SN/A{ 1475875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, "Requesting a hw_pf to issue\n"); 1482810SN/A 1492810SN/A if (pf.empty()) { 1505875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, "No HW_PF found\n"); 1512810SN/A return NULL; 1522810SN/A } 1532810SN/A 1549546Sandreas.hansson@arm.com PacketPtr pkt = pf.begin()->pkt; 1558509SAli.Saidi@ARM.com while (!pf.empty()) { 1569546Sandreas.hansson@arm.com pkt = pf.begin()->pkt; 1572810SN/A pf.pop_front(); 1585875Ssteve.reinhardt@amd.com 1598509SAli.Saidi@ARM.com Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1); 1608509SAli.Saidi@ARM.com 1618509SAli.Saidi@ARM.com if (!inCache(blk_addr) && !inMissQueue(blk_addr)) 1628509SAli.Saidi@ARM.com // we found a prefetch, return it 1638509SAli.Saidi@ARM.com break; 1648509SAli.Saidi@ARM.com 1658509SAli.Saidi@ARM.com DPRINTF(HWPrefetch, "addr 0x%x in cache, skipping\n", pkt->getAddr()); 1668509SAli.Saidi@ARM.com delete pkt->req; 1678509SAli.Saidi@ARM.com delete pkt; 1685875Ssteve.reinhardt@amd.com 1692810SN/A if (pf.empty()) { 1704628SN/A cache->deassertMemSideBusRequest(BaseCache::Request_PF); 1718509SAli.Saidi@ARM.com return NULL; // None left, all were in cache 1722810SN/A } 1738509SAli.Saidi@ARM.com } 1742810SN/A 1752810SN/A pfIssued++; 1765875Ssteve.reinhardt@amd.com assert(pkt != NULL); 1775875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, "returning 0x%x\n", pkt->getAddr()); 1782810SN/A return pkt; 1792810SN/A} 1802810SN/A 1815875Ssteve.reinhardt@amd.com 1825875Ssteve.reinhardt@amd.comTick 1839546Sandreas.hansson@arm.comBasePrefetcher::notify(PacketPtr &pkt, Tick tick) 1842810SN/A{ 1856105Ssteve.reinhardt@amd.com if (!pkt->req->isUncacheable() && !(pkt->req->isInstFetch() && onlyData)) { 1865875Ssteve.reinhardt@amd.com // Calculate the blk address 1875875Ssteve.reinhardt@amd.com Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1); 1882810SN/A 1895875Ssteve.reinhardt@amd.com // Check if miss is in pfq, if so remove it 1909546Sandreas.hansson@arm.com std::list<DeferredPacket>::iterator iter = inPrefetch(blk_addr); 1912810SN/A if (iter != pf.end()) { 1925875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, "Saw a miss to a queued prefetch addr: " 1935875Ssteve.reinhardt@amd.com "0x%x, removing it\n", blk_addr); 1942810SN/A pfRemovedMSHR++; 1959546Sandreas.hansson@arm.com delete iter->pkt->req; 1969546Sandreas.hansson@arm.com delete iter->pkt; 1978991SAli.Saidi@ARM.com iter = pf.erase(iter); 1982810SN/A if (pf.empty()) 1994628SN/A cache->deassertMemSideBusRequest(BaseCache::Request_PF); 2002810SN/A } 2012810SN/A 2025875Ssteve.reinhardt@amd.com // Remove anything in queue with delay older than time 2035875Ssteve.reinhardt@amd.com // since everything is inserted in time order, start from end 2045875Ssteve.reinhardt@amd.com // and work until pf.empty() or time is earlier 2055875Ssteve.reinhardt@amd.com // This is done to emulate Aborting the previous work on a new miss 2065875Ssteve.reinhardt@amd.com // Needed for serial calculators like GHB 2072810SN/A if (serialSquash) { 2082810SN/A iter = pf.end(); 2098991SAli.Saidi@ARM.com if (iter != pf.begin()) 2108991SAli.Saidi@ARM.com iter--; 2119546Sandreas.hansson@arm.com while (!pf.empty() && iter->tick >= tick) { 2122810SN/A pfSquashed++; 2135875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, "Squashing old prefetch addr: 0x%x\n", 2149546Sandreas.hansson@arm.com iter->pkt->getAddr()); 2159546Sandreas.hansson@arm.com delete iter->pkt->req; 2169546Sandreas.hansson@arm.com delete iter->pkt; 2178991SAli.Saidi@ARM.com iter = pf.erase(iter); 2188991SAli.Saidi@ARM.com if (iter != pf.begin()) 2198991SAli.Saidi@ARM.com iter--; 2202810SN/A } 2212810SN/A if (pf.empty()) 2224628SN/A cache->deassertMemSideBusRequest(BaseCache::Request_PF); 2232810SN/A } 2242810SN/A 2252810SN/A 2262810SN/A std::list<Addr> addresses; 2279288Sandreas.hansson@arm.com std::list<Cycles> delays; 2282810SN/A calculatePrefetch(pkt, addresses, delays); 2292810SN/A 2305875Ssteve.reinhardt@amd.com std::list<Addr>::iterator addrIter = addresses.begin(); 2319288Sandreas.hansson@arm.com std::list<Cycles>::iterator delayIter = delays.begin(); 2325875Ssteve.reinhardt@amd.com for (; addrIter != addresses.end(); ++addrIter, ++delayIter) { 2335875Ssteve.reinhardt@amd.com Addr addr = *addrIter; 2345875Ssteve.reinhardt@amd.com 2352810SN/A pfIdentified++; 2365875Ssteve.reinhardt@amd.com 2375875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, "Found a pf candidate addr: 0x%x, " 2385875Ssteve.reinhardt@amd.com "inserting into prefetch queue with delay %d time %d\n", 2395875Ssteve.reinhardt@amd.com addr, *delayIter, time); 2405875Ssteve.reinhardt@amd.com 2415875Ssteve.reinhardt@amd.com // Check if it is already in the pf buffer 2425875Ssteve.reinhardt@amd.com if (inPrefetch(addr) != pf.end()) { 2435875Ssteve.reinhardt@amd.com pfBufferHit++; 2445875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, "Prefetch addr already in pf buffer\n"); 2455875Ssteve.reinhardt@amd.com continue; 2465875Ssteve.reinhardt@amd.com } 2475875Ssteve.reinhardt@amd.com 2485875Ssteve.reinhardt@amd.com // create a prefetch memreq 2498832SAli.Saidi@ARM.com Request *prefetchReq = new Request(*addrIter, blkSize, 0, masterId); 25010024Sdam.sunwoo@arm.com prefetchReq->taskId(ContextSwitchTaskId::Prefetcher); 2515875Ssteve.reinhardt@amd.com PacketPtr prefetch = 2528949Sandreas.hansson@arm.com new Packet(prefetchReq, MemCmd::HardPFReq); 2532825SN/A prefetch->allocate(); 2545714Shsul@eecs.umich.edu prefetch->req->setThreadContext(pkt->req->contextId(), 2555714Shsul@eecs.umich.edu pkt->req->threadId()); 2562814SN/A 2575875Ssteve.reinhardt@amd.com // We just remove the head if we are full 2585875Ssteve.reinhardt@amd.com if (pf.size() == size) { 2592810SN/A pfRemovedFull++; 2609546Sandreas.hansson@arm.com PacketPtr old_pkt = pf.begin()->pkt; 2615875Ssteve.reinhardt@amd.com DPRINTF(HWPrefetch, "Prefetch queue full, " 2625875Ssteve.reinhardt@amd.com "removing oldest 0x%x\n", old_pkt->getAddr()); 2635875Ssteve.reinhardt@amd.com delete old_pkt->req; 2645875Ssteve.reinhardt@amd.com delete old_pkt; 2652810SN/A pf.pop_front(); 2662810SN/A } 2672810SN/A 2689546Sandreas.hansson@arm.com pf.push_back(DeferredPacket(tick + clockPeriod() * *delayIter, 2699546Sandreas.hansson@arm.com prefetch)); 2702810SN/A } 2712810SN/A } 2725875Ssteve.reinhardt@amd.com 2739546Sandreas.hansson@arm.com return pf.empty() ? 0 : pf.front().tick; 2742810SN/A} 2752810SN/A 2769546Sandreas.hansson@arm.comstd::list<BasePrefetcher::DeferredPacket>::iterator 2772810SN/ABasePrefetcher::inPrefetch(Addr address) 2782810SN/A{ 2795875Ssteve.reinhardt@amd.com // Guaranteed to only be one match, we always check before inserting 2809546Sandreas.hansson@arm.com std::list<DeferredPacket>::iterator iter; 2815875Ssteve.reinhardt@amd.com for (iter = pf.begin(); iter != pf.end(); iter++) { 2829546Sandreas.hansson@arm.com if ((iter->pkt->getAddr() & ~(Addr)(blkSize-1)) == address) { 2832810SN/A return iter; 2842810SN/A } 2852810SN/A } 2862810SN/A return pf.end(); 2872810SN/A} 2882810SN/A 2895875Ssteve.reinhardt@amd.combool 2905875Ssteve.reinhardt@amd.comBasePrefetcher::samePage(Addr a, Addr b) 2915875Ssteve.reinhardt@amd.com{ 2925875Ssteve.reinhardt@amd.com return roundDown(a, TheISA::VMPageSize) == roundDown(b, TheISA::VMPageSize); 2935875Ssteve.reinhardt@amd.com} 2948831Smrinmoy.ghosh@arm.com 2958831Smrinmoy.ghosh@arm.com 296