noncoherent_cache.hh revision 13478
1/* 2 * Copyright (c) 2012-2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 * Dave Greene 42 * Steve Reinhardt 43 * Ron Dreslinski 44 * Andreas Hansson 45 * Nikos Nikoleris 46 */ 47 48/** 49 * @file 50 * Specifies a non-coherent cache. The non-coherent cache is expected 51 * to be located below the point of coherency. All valid blocks in the 52 * non-coherent cache can always be written to without any prior 53 * invalidations or snoops. 54 */ 55 56#ifndef __MEM_CACHE_NONCOHERENT_CACHE_HH__ 57#define __MEM_CACHE_NONCOHERENT_CACHE_HH__ 58 59#include "base/logging.hh" 60#include "base/types.hh" 61#include "mem/cache/base.hh" 62#include "mem/packet.hh" 63 64class CacheBlk; 65class MSHR; 66struct NoncoherentCacheParams; 67 68/** 69 * A non-coherent cache 70 */ 71class NoncoherentCache : public BaseCache 72{ 73 protected: 74 bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 75 PacketList &writebacks) override; 76 77 void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, 78 Tick forward_time, 79 Tick request_time) override; 80 81 void recvTimingReq(PacketPtr pkt) override; 82 83 void doWritebacks(PacketList& writebacks, 84 Tick forward_time) override; 85 86 void doWritebacksAtomic(PacketList& writebacks) override; 87 88 void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, 89 CacheBlk *blk) override; 90 91 void recvTimingResp(PacketPtr pkt) override; 92 93 void recvTimingSnoopReq(PacketPtr pkt) override { 94 panic("Unexpected timing snoop request %s", pkt->print()); 95 } 96 97 void recvTimingSnoopResp(PacketPtr pkt) override { 98 panic("Unexpected timing snoop response %s", pkt->print()); 99 } 100 101 Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk, 102 PacketList &writebacks) override; 103 104 Tick recvAtomic(PacketPtr pkt) override; 105 106 Tick recvAtomicSnoop(PacketPtr pkt) override { 107 panic("Unexpected atomic snoop request %s", pkt->print()); 108 } 109 110 void functionalAccess(PacketPtr pkt, bool from_cpu_side) override; 111 112 void satisfyRequest(PacketPtr pkt, CacheBlk *blk, 113 bool deferred_response = false, 114 bool pending_downgrade = false) override; 115 116 /* 117 * Creates a new packet with the request to be send to the memory 118 * below. The noncoherent cache is below the point of coherence 119 * and therefore all fills bring in writable, therefore the 120 * needs_writeble parameter is ignored. 121 */ 122 PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, 123 bool needs_writable, 124 bool is_whole_line_write) const override; 125 126 M5_NODISCARD PacketPtr evictBlock(CacheBlk *blk) override; 127 128 public: 129 NoncoherentCache(const NoncoherentCacheParams *p); 130}; 131 132#endif // __MEM_CACHE_NONCOHERENTCACHE_HH__ 133