noncoherent_cache.hh revision 13017
112726Snikos.nikoleris@arm.com/*
212726Snikos.nikoleris@arm.com * Copyright (c) 2012-2018 ARM Limited
312726Snikos.nikoleris@arm.com * All rights reserved.
412726Snikos.nikoleris@arm.com *
512726Snikos.nikoleris@arm.com * The license below extends only to copyright in the software and shall
612726Snikos.nikoleris@arm.com * not be construed as granting a license to any other intellectual
712726Snikos.nikoleris@arm.com * property including but not limited to intellectual property relating
812726Snikos.nikoleris@arm.com * to a hardware implementation of the functionality of the software
912726Snikos.nikoleris@arm.com * licensed hereunder.  You may use the software subject to the license
1012726Snikos.nikoleris@arm.com * terms below provided that you ensure that this notice is replicated
1112726Snikos.nikoleris@arm.com * unmodified and in its entirety in all distributions of the software,
1212726Snikos.nikoleris@arm.com * modified or unmodified, in source code or in binary form.
1312726Snikos.nikoleris@arm.com *
1412726Snikos.nikoleris@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan
1512726Snikos.nikoleris@arm.com * All rights reserved.
1612726Snikos.nikoleris@arm.com *
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1812726Snikos.nikoleris@arm.com * modification, are permitted provided that the following conditions are
1912726Snikos.nikoleris@arm.com * met: redistributions of source code must retain the above copyright
2012726Snikos.nikoleris@arm.com * notice, this list of conditions and the following disclaimer;
2112726Snikos.nikoleris@arm.com * redistributions in binary form must reproduce the above copyright
2212726Snikos.nikoleris@arm.com * notice, this list of conditions and the following disclaimer in the
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2612726Snikos.nikoleris@arm.com * this software without specific prior written permission.
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2812726Snikos.nikoleris@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
2912726Snikos.nikoleris@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
3012726Snikos.nikoleris@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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3712726Snikos.nikoleris@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
3812726Snikos.nikoleris@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3912726Snikos.nikoleris@arm.com *
4012726Snikos.nikoleris@arm.com * Authors: Erik Hallnor
4112726Snikos.nikoleris@arm.com *          Dave Greene
4212726Snikos.nikoleris@arm.com *          Steve Reinhardt
4312726Snikos.nikoleris@arm.com *          Ron Dreslinski
4412726Snikos.nikoleris@arm.com *          Andreas Hansson
4512726Snikos.nikoleris@arm.com *          Nikos Nikoleris
4612726Snikos.nikoleris@arm.com */
4712726Snikos.nikoleris@arm.com
4812726Snikos.nikoleris@arm.com/**
4912726Snikos.nikoleris@arm.com * @file
5012726Snikos.nikoleris@arm.com * Specifies a non-coherent cache. The non-coherent cache is expected
5112726Snikos.nikoleris@arm.com * to be located below the point of coherency. All valid blocks in the
5212726Snikos.nikoleris@arm.com * non-coherent cache can always be written to without any prior
5312726Snikos.nikoleris@arm.com * invalidations or snoops.
5412726Snikos.nikoleris@arm.com */
5512726Snikos.nikoleris@arm.com
5612726Snikos.nikoleris@arm.com#ifndef __MEM_CACHE_NONCOHERENT_CACHE_HH__
5712726Snikos.nikoleris@arm.com#define __MEM_CACHE_NONCOHERENT_CACHE_HH__
5812726Snikos.nikoleris@arm.com
5912726Snikos.nikoleris@arm.com#include "base/logging.hh"
6012726Snikos.nikoleris@arm.com#include "base/types.hh"
6112726Snikos.nikoleris@arm.com#include "mem/cache/base.hh"
6212726Snikos.nikoleris@arm.com#include "mem/packet.hh"
6312726Snikos.nikoleris@arm.com
6412726Snikos.nikoleris@arm.comclass CacheBlk;
6512726Snikos.nikoleris@arm.comclass MSHR;
6612726Snikos.nikoleris@arm.comstruct NoncoherentCacheParams;
6712726Snikos.nikoleris@arm.com
6812726Snikos.nikoleris@arm.com/**
6912726Snikos.nikoleris@arm.com * A non-coherent cache
7012726Snikos.nikoleris@arm.com */
7112726Snikos.nikoleris@arm.comclass NoncoherentCache : public BaseCache
7212726Snikos.nikoleris@arm.com{
7312726Snikos.nikoleris@arm.com  protected:
7412726Snikos.nikoleris@arm.com    bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
7512726Snikos.nikoleris@arm.com                PacketList &writebacks) override;
7612726Snikos.nikoleris@arm.com
7712726Snikos.nikoleris@arm.com    void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
7812726Snikos.nikoleris@arm.com                             Tick forward_time,
7912726Snikos.nikoleris@arm.com                             Tick request_time) override;
8012726Snikos.nikoleris@arm.com
8112726Snikos.nikoleris@arm.com    void recvTimingReq(PacketPtr pkt) override;
8212726Snikos.nikoleris@arm.com
8312726Snikos.nikoleris@arm.com    void doWritebacks(PacketList& writebacks,
8412726Snikos.nikoleris@arm.com                      Tick forward_time) override;
8512726Snikos.nikoleris@arm.com
8612726Snikos.nikoleris@arm.com    void doWritebacksAtomic(PacketList& writebacks) override;
8712726Snikos.nikoleris@arm.com
8812726Snikos.nikoleris@arm.com    void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
8912726Snikos.nikoleris@arm.com                            CacheBlk *blk, PacketList& writebacks) override;
9012726Snikos.nikoleris@arm.com
9112726Snikos.nikoleris@arm.com    void recvTimingResp(PacketPtr pkt) override;
9212726Snikos.nikoleris@arm.com
9312726Snikos.nikoleris@arm.com    void recvTimingSnoopReq(PacketPtr pkt) override {
9412726Snikos.nikoleris@arm.com        panic("Unexpected timing snoop request %s", pkt->print());
9512726Snikos.nikoleris@arm.com    }
9612726Snikos.nikoleris@arm.com
9712726Snikos.nikoleris@arm.com    void recvTimingSnoopResp(PacketPtr pkt) override {
9812726Snikos.nikoleris@arm.com        panic("Unexpected timing snoop response %s", pkt->print());
9912726Snikos.nikoleris@arm.com    }
10012726Snikos.nikoleris@arm.com
10113017Snikos.nikoleris@arm.com    Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
10212726Snikos.nikoleris@arm.com                               PacketList &writebacks) override;
10312726Snikos.nikoleris@arm.com
10412726Snikos.nikoleris@arm.com    Tick recvAtomic(PacketPtr pkt) override;
10512726Snikos.nikoleris@arm.com
10612726Snikos.nikoleris@arm.com    Tick recvAtomicSnoop(PacketPtr pkt) override {
10712726Snikos.nikoleris@arm.com        panic("Unexpected atomic snoop request %s", pkt->print());
10812726Snikos.nikoleris@arm.com    }
10912726Snikos.nikoleris@arm.com
11012726Snikos.nikoleris@arm.com    void functionalAccess(PacketPtr pkt, bool from_cpu_side) override;
11112726Snikos.nikoleris@arm.com
11212726Snikos.nikoleris@arm.com    void satisfyRequest(PacketPtr pkt, CacheBlk *blk,
11312726Snikos.nikoleris@arm.com                        bool deferred_response = false,
11412726Snikos.nikoleris@arm.com                        bool pending_downgrade = false) override;
11512726Snikos.nikoleris@arm.com
11612726Snikos.nikoleris@arm.com    /*
11712726Snikos.nikoleris@arm.com     * Creates a new packet with the request to be send to the memory
11812726Snikos.nikoleris@arm.com     * below. The noncoherent cache is below the point of coherence
11912726Snikos.nikoleris@arm.com     * and therefore all fills bring in writable, therefore the
12012726Snikos.nikoleris@arm.com     * needs_writeble parameter is ignored.
12112726Snikos.nikoleris@arm.com     */
12212726Snikos.nikoleris@arm.com    PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
12312726Snikos.nikoleris@arm.com                               bool needs_writable) const override;
12412726Snikos.nikoleris@arm.com
12512726Snikos.nikoleris@arm.com    M5_NODISCARD PacketPtr evictBlock(CacheBlk *blk) override;
12612726Snikos.nikoleris@arm.com
12712726Snikos.nikoleris@arm.com    void evictBlock(CacheBlk *blk, PacketList &writebacks) override;
12812726Snikos.nikoleris@arm.com
12912726Snikos.nikoleris@arm.com  public:
13012726Snikos.nikoleris@arm.com    NoncoherentCache(const NoncoherentCacheParams *p);
13112726Snikos.nikoleris@arm.com};
13212726Snikos.nikoleris@arm.com
13312726Snikos.nikoleris@arm.com#endif // __MEM_CACHE_NONCOHERENTCACHE_HH__
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