mshr_queue.cc revision 9725
12810SN/A/*
29725Sandreas.hansson@arm.com * Copyright (c) 2012-2013 ARM Limited
39347SAndreas.Sandberg@arm.com * All rights reserved.
49347SAndreas.Sandberg@arm.com *
59347SAndreas.Sandberg@arm.com * The license below extends only to copyright in the software and shall
69347SAndreas.Sandberg@arm.com * not be construed as granting a license to any other intellectual
79347SAndreas.Sandberg@arm.com * property including but not limited to intellectual property relating
89347SAndreas.Sandberg@arm.com * to a hardware implementation of the functionality of the software
99347SAndreas.Sandberg@arm.com * licensed hereunder.  You may use the software subject to the license
109347SAndreas.Sandberg@arm.com * terms below provided that you ensure that this notice is replicated
119347SAndreas.Sandberg@arm.com * unmodified and in its entirety in all distributions of the software,
129347SAndreas.Sandberg@arm.com * modified or unmodified, in source code or in binary form.
139347SAndreas.Sandberg@arm.com *
142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan
152810SN/A * All rights reserved.
162810SN/A *
172810SN/A * Redistribution and use in source and binary forms, with or without
182810SN/A * modification, are permitted provided that the following conditions are
192810SN/A * met: redistributions of source code must retain the above copyright
202810SN/A * notice, this list of conditions and the following disclaimer;
212810SN/A * redistributions in binary form must reproduce the above copyright
222810SN/A * notice, this list of conditions and the following disclaimer in the
232810SN/A * documentation and/or other materials provided with the distribution;
242810SN/A * neither the name of the copyright holders nor the names of its
252810SN/A * contributors may be used to endorse or promote products derived from
262810SN/A * this software without specific prior written permission.
272810SN/A *
282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
392810SN/A *
402810SN/A * Authors: Erik Hallnor
419347SAndreas.Sandberg@arm.com *          Andreas Sandberg
422810SN/A */
432810SN/A
442810SN/A/** @file
454626SN/A * Definition of MSHRQueue class functions.
462810SN/A */
472810SN/A
485338Sstever@gmail.com#include "mem/cache/mshr_queue.hh"
492810SN/A
502810SN/Ausing namespace std;
512810SN/A
525314SN/AMSHRQueue::MSHRQueue(const std::string &_label,
535314SN/A                     int num_entries, int reserve, int _index)
549725Sandreas.hansson@arm.com    : label(_label), numEntries(num_entries + reserve - 1),
559725Sandreas.hansson@arm.com      numReserve(reserve), registers(numEntries),
569725Sandreas.hansson@arm.com      drainManager(NULL), allocated(0), inServiceEntries(0), index(_index)
572810SN/A{
584626SN/A    for (int i = 0; i < numEntries; ++i) {
594626SN/A        registers[i].queue = this;
602810SN/A        freeList.push_back(&registers[i]);
612810SN/A    }
622810SN/A}
632810SN/A
644626SN/AMSHR *
652991SN/AMSHRQueue::findMatch(Addr addr) const
662810SN/A{
672810SN/A    MSHR::ConstIterator i = allocatedList.begin();
682810SN/A    MSHR::ConstIterator end = allocatedList.end();
692810SN/A    for (; i != end; ++i) {
702810SN/A        MSHR *mshr = *i;
712810SN/A        if (mshr->addr == addr) {
722810SN/A            return mshr;
732810SN/A        }
742810SN/A    }
752810SN/A    return NULL;
762810SN/A}
772810SN/A
782810SN/Abool
792991SN/AMSHRQueue::findMatches(Addr addr, vector<MSHR*>& matches) const
802810SN/A{
812810SN/A    // Need an empty vector
822810SN/A    assert(matches.empty());
832810SN/A    bool retval = false;
842810SN/A    MSHR::ConstIterator i = allocatedList.begin();
852810SN/A    MSHR::ConstIterator end = allocatedList.end();
862810SN/A    for (; i != end; ++i) {
872810SN/A        MSHR *mshr = *i;
882810SN/A        if (mshr->addr == addr) {
892810SN/A            retval = true;
902810SN/A            matches.push_back(mshr);
912810SN/A        }
922810SN/A    }
932810SN/A    return retval;
944920SN/A}
952810SN/A
964920SN/A
974920SN/Abool
984920SN/AMSHRQueue::checkFunctional(PacketPtr pkt, Addr blk_addr)
994920SN/A{
1005314SN/A    pkt->pushLabel(label);
1014920SN/A    MSHR::ConstIterator i = allocatedList.begin();
1024920SN/A    MSHR::ConstIterator end = allocatedList.end();
1034920SN/A    for (; i != end; ++i) {
1044920SN/A        MSHR *mshr = *i;
1054920SN/A        if (mshr->addr == blk_addr && mshr->checkFunctional(pkt)) {
1065314SN/A            pkt->popLabel();
1074920SN/A            return true;
1084920SN/A        }
1094920SN/A    }
1105314SN/A    pkt->popLabel();
1114920SN/A    return false;
1122810SN/A}
1132810SN/A
1144920SN/A
1154626SN/AMSHR *
1164626SN/AMSHRQueue::findPending(Addr addr, int size) const
1172810SN/A{
1184666SN/A    MSHR::ConstIterator i = readyList.begin();
1194666SN/A    MSHR::ConstIterator end = readyList.end();
1202810SN/A    for (; i != end; ++i) {
1212810SN/A        MSHR *mshr = *i;
1224626SN/A        if (mshr->addr < addr) {
1234626SN/A            if (mshr->addr + mshr->size > addr) {
1242810SN/A                return mshr;
1252810SN/A            }
1262810SN/A        } else {
1274626SN/A            if (addr + size > mshr->addr) {
1282810SN/A                return mshr;
1292810SN/A            }
1302810SN/A        }
1312810SN/A    }
1322810SN/A    return NULL;
1332810SN/A}
1342810SN/A
1354666SN/A
1364666SN/AMSHR::Iterator
1374666SN/AMSHRQueue::addToReadyList(MSHR *mshr)
1384666SN/A{
1394871SN/A    if (readyList.empty() || readyList.back()->readyTime <= mshr->readyTime) {
1404666SN/A        return readyList.insert(readyList.end(), mshr);
1414666SN/A    }
1424666SN/A
1434666SN/A    MSHR::Iterator i = readyList.begin();
1444666SN/A    MSHR::Iterator end = readyList.end();
1454666SN/A    for (; i != end; ++i) {
1464871SN/A        if ((*i)->readyTime > mshr->readyTime) {
1474666SN/A            return readyList.insert(i, mshr);
1484666SN/A        }
1494666SN/A    }
1504666SN/A    assert(false);
1514904SN/A    return end;  // keep stupid compilers happy
1524666SN/A}
1534666SN/A
1544666SN/A
1554626SN/AMSHR *
1564666SN/AMSHRQueue::allocate(Addr addr, int size, PacketPtr &pkt,
1574666SN/A                    Tick when, Counter order)
1582810SN/A{
1593149SN/A    assert(!freeList.empty());
1602810SN/A    MSHR *mshr = freeList.front();
1612810SN/A    assert(mshr->getNumTargets() == 0);
1622810SN/A    freeList.pop_front();
1632810SN/A
1644666SN/A    mshr->allocate(addr, size, pkt, when, order);
1652810SN/A    mshr->allocIter = allocatedList.insert(allocatedList.end(), mshr);
1664666SN/A    mshr->readyIter = addToReadyList(mshr);
1672810SN/A
1682810SN/A    allocated += 1;
1692810SN/A    return mshr;
1702810SN/A}
1712810SN/A
1722810SN/A
1732810SN/Avoid
1744626SN/AMSHRQueue::deallocate(MSHR *mshr)
1752810SN/A{
1762810SN/A    deallocateOne(mshr);
1772810SN/A}
1782810SN/A
1792810SN/AMSHR::Iterator
1804626SN/AMSHRQueue::deallocateOne(MSHR *mshr)
1812810SN/A{
1822810SN/A    MSHR::Iterator retval = allocatedList.erase(mshr->allocIter);
1832810SN/A    freeList.push_front(mshr);
1842810SN/A    allocated--;
1852810SN/A    if (mshr->inService) {
1864626SN/A        inServiceEntries--;
1872810SN/A    } else {
1884666SN/A        readyList.erase(mshr->readyIter);
1892810SN/A    }
1902810SN/A    mshr->deallocate();
1919347SAndreas.Sandberg@arm.com    if (drainManager && allocated == 0) {
1929347SAndreas.Sandberg@arm.com        // Notify the drain manager that we have completed draining if
1939347SAndreas.Sandberg@arm.com        // there are no other outstanding requests in this MSHR queue.
1949347SAndreas.Sandberg@arm.com        drainManager->signalDrainDone();
1959347SAndreas.Sandberg@arm.com        drainManager = NULL;
1969347SAndreas.Sandberg@arm.com        setDrainState(Drainable::Drained);
1979347SAndreas.Sandberg@arm.com    }
1982810SN/A    return retval;
1992810SN/A}
2002810SN/A
2012810SN/Avoid
2022810SN/AMSHRQueue::moveToFront(MSHR *mshr)
2032810SN/A{
2042810SN/A    if (!mshr->inService) {
2052810SN/A        assert(mshr == *(mshr->readyIter));
2064666SN/A        readyList.erase(mshr->readyIter);
2074666SN/A        mshr->readyIter = readyList.insert(readyList.begin(), mshr);
2082810SN/A    }
2092810SN/A}
2102810SN/A
2112810SN/Avoid
2127667Ssteve.reinhardt@amd.comMSHRQueue::markInService(MSHR *mshr, PacketPtr pkt)
2132810SN/A{
2147667Ssteve.reinhardt@amd.com    if (mshr->markInService(pkt)) {
2152810SN/A        deallocate(mshr);
2164908SN/A    } else {
2174908SN/A        readyList.erase(mshr->readyIter);
2184908SN/A        inServiceEntries += 1;
2192810SN/A    }
2202810SN/A}
2212810SN/A
2222810SN/Avoid
2234626SN/AMSHRQueue::markPending(MSHR *mshr)
2242810SN/A{
2254666SN/A    assert(mshr->inService);
2262810SN/A    mshr->inService = false;
2274626SN/A    --inServiceEntries;
2282810SN/A    /**
2292810SN/A     * @ todo might want to add rerequests to front of pending list for
2302810SN/A     * performance.
2312810SN/A     */
2324666SN/A    mshr->readyIter = addToReadyList(mshr);
2332810SN/A}
2342810SN/A
2352810SN/Avoid
2362813SN/AMSHRQueue::squash(int threadNum)
2372810SN/A{
2382810SN/A    MSHR::Iterator i = allocatedList.begin();
2392810SN/A    MSHR::Iterator end = allocatedList.end();
2402810SN/A    for (; i != end;) {
2412810SN/A        MSHR *mshr = *i;
2422813SN/A        if (mshr->threadNum == threadNum) {
2432810SN/A            while (mshr->hasTargets()) {
2442810SN/A                mshr->popTarget();
2455715Shsul@eecs.umich.edu                assert(0/*target->req->threadId()*/ == threadNum);
2462810SN/A            }
2472810SN/A            assert(!mshr->hasTargets());
2489725Sandreas.hansson@arm.com            assert(mshr->getNumTargets()==0);
2492810SN/A            if (!mshr->inService) {
2502810SN/A                i = deallocateOne(mshr);
2512810SN/A            } else {
2522810SN/A                //mshr->pkt->flags &= ~CACHE_LINE_FILL;
2532810SN/A                ++i;
2542810SN/A            }
2552810SN/A        } else {
2562810SN/A            ++i;
2572810SN/A        }
2582810SN/A    }
2592810SN/A}
2609347SAndreas.Sandberg@arm.com
2619347SAndreas.Sandberg@arm.comunsigned int
2629347SAndreas.Sandberg@arm.comMSHRQueue::drain(DrainManager *dm)
2639347SAndreas.Sandberg@arm.com{
2649347SAndreas.Sandberg@arm.com    if (allocated == 0) {
2659347SAndreas.Sandberg@arm.com        setDrainState(Drainable::Drained);
2669347SAndreas.Sandberg@arm.com        return 0;
2679347SAndreas.Sandberg@arm.com    } else {
2689347SAndreas.Sandberg@arm.com        drainManager = dm;
2699347SAndreas.Sandberg@arm.com        setDrainState(Drainable::Draining);
2709347SAndreas.Sandberg@arm.com        return 1;
2719347SAndreas.Sandberg@arm.com    }
2729347SAndreas.Sandberg@arm.com}
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