mshr_queue.cc revision 10764
12810SN/A/* 210764Sandreas.hansson@arm.com * Copyright (c) 2012-2013, 2015 ARM Limited 39347SAndreas.Sandberg@arm.com * All rights reserved. 49347SAndreas.Sandberg@arm.com * 59347SAndreas.Sandberg@arm.com * The license below extends only to copyright in the software and shall 69347SAndreas.Sandberg@arm.com * not be construed as granting a license to any other intellectual 79347SAndreas.Sandberg@arm.com * property including but not limited to intellectual property relating 89347SAndreas.Sandberg@arm.com * to a hardware implementation of the functionality of the software 99347SAndreas.Sandberg@arm.com * licensed hereunder. You may use the software subject to the license 109347SAndreas.Sandberg@arm.com * terms below provided that you ensure that this notice is replicated 119347SAndreas.Sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 129347SAndreas.Sandberg@arm.com * modified or unmodified, in source code or in binary form. 139347SAndreas.Sandberg@arm.com * 142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Erik Hallnor 419347SAndreas.Sandberg@arm.com * Andreas Sandberg 422810SN/A */ 432810SN/A 442810SN/A/** @file 454626SN/A * Definition of MSHRQueue class functions. 462810SN/A */ 472810SN/A 4810509SAli.Saidi@ARM.com#include "base/trace.hh" 495338Sstever@gmail.com#include "mem/cache/mshr_queue.hh" 5010509SAli.Saidi@ARM.com#include "debug/Drain.hh" 512810SN/A 522810SN/Ausing namespace std; 532810SN/A 545314SN/AMSHRQueue::MSHRQueue(const std::string &_label, 5510622Smitch.hayenga@arm.com int num_entries, int reserve, int demand_reserve, 5610622Smitch.hayenga@arm.com int _index) 579725Sandreas.hansson@arm.com : label(_label), numEntries(num_entries + reserve - 1), 5810622Smitch.hayenga@arm.com numReserve(reserve), demandReserve(demand_reserve), 5910622Smitch.hayenga@arm.com registers(numEntries), drainManager(NULL), allocated(0), 6010622Smitch.hayenga@arm.com inServiceEntries(0), index(_index) 612810SN/A{ 624626SN/A for (int i = 0; i < numEntries; ++i) { 634626SN/A registers[i].queue = this; 642810SN/A freeList.push_back(®isters[i]); 652810SN/A } 662810SN/A} 672810SN/A 684626SN/AMSHR * 6910764Sandreas.hansson@arm.comMSHRQueue::findMatch(Addr blk_addr, bool is_secure) const 702810SN/A{ 712810SN/A MSHR::ConstIterator i = allocatedList.begin(); 722810SN/A MSHR::ConstIterator end = allocatedList.end(); 732810SN/A for (; i != end; ++i) { 742810SN/A MSHR *mshr = *i; 7510764Sandreas.hansson@arm.com if (mshr->blkAddr == blk_addr && mshr->isSecure == is_secure) { 762810SN/A return mshr; 772810SN/A } 782810SN/A } 792810SN/A return NULL; 802810SN/A} 812810SN/A 822810SN/Abool 8310764Sandreas.hansson@arm.comMSHRQueue::findMatches(Addr blk_addr, bool is_secure, 8410764Sandreas.hansson@arm.com vector<MSHR*>& matches) const 852810SN/A{ 862810SN/A // Need an empty vector 872810SN/A assert(matches.empty()); 882810SN/A bool retval = false; 892810SN/A MSHR::ConstIterator i = allocatedList.begin(); 902810SN/A MSHR::ConstIterator end = allocatedList.end(); 912810SN/A for (; i != end; ++i) { 922810SN/A MSHR *mshr = *i; 9310764Sandreas.hansson@arm.com if (mshr->blkAddr == blk_addr && mshr->isSecure == is_secure) { 942810SN/A retval = true; 952810SN/A matches.push_back(mshr); 962810SN/A } 972810SN/A } 982810SN/A return retval; 994920SN/A} 1002810SN/A 1014920SN/A 1024920SN/Abool 1034920SN/AMSHRQueue::checkFunctional(PacketPtr pkt, Addr blk_addr) 1044920SN/A{ 1055314SN/A pkt->pushLabel(label); 1064920SN/A MSHR::ConstIterator i = allocatedList.begin(); 1074920SN/A MSHR::ConstIterator end = allocatedList.end(); 1084920SN/A for (; i != end; ++i) { 1094920SN/A MSHR *mshr = *i; 11010764Sandreas.hansson@arm.com if (mshr->blkAddr == blk_addr && mshr->checkFunctional(pkt)) { 1115314SN/A pkt->popLabel(); 1124920SN/A return true; 1134920SN/A } 1144920SN/A } 1155314SN/A pkt->popLabel(); 1164920SN/A return false; 1172810SN/A} 1182810SN/A 1194920SN/A 1204626SN/AMSHR * 12110764Sandreas.hansson@arm.comMSHRQueue::findPending(Addr blk_addr, bool is_secure) const 1222810SN/A{ 1234666SN/A MSHR::ConstIterator i = readyList.begin(); 1244666SN/A MSHR::ConstIterator end = readyList.end(); 1252810SN/A for (; i != end; ++i) { 1262810SN/A MSHR *mshr = *i; 12710764Sandreas.hansson@arm.com if (mshr->blkAddr == blk_addr && mshr->isSecure == is_secure) { 12810764Sandreas.hansson@arm.com return mshr; 1292810SN/A } 1302810SN/A } 1312810SN/A return NULL; 1322810SN/A} 1332810SN/A 1344666SN/A 1354666SN/AMSHR::Iterator 1364666SN/AMSHRQueue::addToReadyList(MSHR *mshr) 1374666SN/A{ 1384871SN/A if (readyList.empty() || readyList.back()->readyTime <= mshr->readyTime) { 1394666SN/A return readyList.insert(readyList.end(), mshr); 1404666SN/A } 1414666SN/A 1424666SN/A MSHR::Iterator i = readyList.begin(); 1434666SN/A MSHR::Iterator end = readyList.end(); 1444666SN/A for (; i != end; ++i) { 1454871SN/A if ((*i)->readyTime > mshr->readyTime) { 1464666SN/A return readyList.insert(i, mshr); 1474666SN/A } 1484666SN/A } 1494666SN/A assert(false); 1504904SN/A return end; // keep stupid compilers happy 1514666SN/A} 1524666SN/A 1534666SN/A 1544626SN/AMSHR * 15510764Sandreas.hansson@arm.comMSHRQueue::allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt, 15610764Sandreas.hansson@arm.com Tick when_ready, Counter order) 1572810SN/A{ 1583149SN/A assert(!freeList.empty()); 1592810SN/A MSHR *mshr = freeList.front(); 1602810SN/A assert(mshr->getNumTargets() == 0); 1612810SN/A freeList.pop_front(); 1622810SN/A 16310764Sandreas.hansson@arm.com mshr->allocate(blk_addr, blk_size, pkt, when_ready, order); 1642810SN/A mshr->allocIter = allocatedList.insert(allocatedList.end(), mshr); 1654666SN/A mshr->readyIter = addToReadyList(mshr); 1662810SN/A 1672810SN/A allocated += 1; 1682810SN/A return mshr; 1692810SN/A} 1702810SN/A 1712810SN/A 1722810SN/Avoid 1734626SN/AMSHRQueue::deallocate(MSHR *mshr) 1742810SN/A{ 1752810SN/A deallocateOne(mshr); 1762810SN/A} 1772810SN/A 1782810SN/AMSHR::Iterator 1794626SN/AMSHRQueue::deallocateOne(MSHR *mshr) 1802810SN/A{ 1812810SN/A MSHR::Iterator retval = allocatedList.erase(mshr->allocIter); 1822810SN/A freeList.push_front(mshr); 1832810SN/A allocated--; 1842810SN/A if (mshr->inService) { 1854626SN/A inServiceEntries--; 1862810SN/A } else { 1874666SN/A readyList.erase(mshr->readyIter); 1882810SN/A } 1892810SN/A mshr->deallocate(); 1909347SAndreas.Sandberg@arm.com if (drainManager && allocated == 0) { 1919347SAndreas.Sandberg@arm.com // Notify the drain manager that we have completed draining if 1929347SAndreas.Sandberg@arm.com // there are no other outstanding requests in this MSHR queue. 19310509SAli.Saidi@ARM.com DPRINTF(Drain, "MSHRQueue now empty, signalling drained\n"); 1949347SAndreas.Sandberg@arm.com drainManager->signalDrainDone(); 1959347SAndreas.Sandberg@arm.com drainManager = NULL; 1969347SAndreas.Sandberg@arm.com setDrainState(Drainable::Drained); 1979347SAndreas.Sandberg@arm.com } 1982810SN/A return retval; 1992810SN/A} 2002810SN/A 2012810SN/Avoid 2022810SN/AMSHRQueue::moveToFront(MSHR *mshr) 2032810SN/A{ 2042810SN/A if (!mshr->inService) { 2052810SN/A assert(mshr == *(mshr->readyIter)); 2064666SN/A readyList.erase(mshr->readyIter); 2074666SN/A mshr->readyIter = readyList.insert(readyList.begin(), mshr); 2082810SN/A } 2092810SN/A} 2102810SN/A 2112810SN/Avoid 21210679Sandreas.hansson@arm.comMSHRQueue::markInService(MSHR *mshr, bool pending_dirty_resp) 2132810SN/A{ 21410679Sandreas.hansson@arm.com if (mshr->markInService(pending_dirty_resp)) { 2152810SN/A deallocate(mshr); 2164908SN/A } else { 2174908SN/A readyList.erase(mshr->readyIter); 2184908SN/A inServiceEntries += 1; 2192810SN/A } 2202810SN/A} 2212810SN/A 2222810SN/Avoid 2234626SN/AMSHRQueue::markPending(MSHR *mshr) 2242810SN/A{ 2254666SN/A assert(mshr->inService); 2262810SN/A mshr->inService = false; 2274626SN/A --inServiceEntries; 2282810SN/A /** 2292810SN/A * @ todo might want to add rerequests to front of pending list for 2302810SN/A * performance. 2312810SN/A */ 2324666SN/A mshr->readyIter = addToReadyList(mshr); 2332810SN/A} 2342810SN/A 23510192Smitch.hayenga@arm.combool 23610192Smitch.hayenga@arm.comMSHRQueue::forceDeallocateTarget(MSHR *mshr) 23710192Smitch.hayenga@arm.com{ 23810192Smitch.hayenga@arm.com bool was_full = isFull(); 23910192Smitch.hayenga@arm.com assert(mshr->hasTargets()); 24010192Smitch.hayenga@arm.com // Pop the prefetch off of the target list 24110192Smitch.hayenga@arm.com mshr->popTarget(); 24210192Smitch.hayenga@arm.com // Delete mshr if no remaining targets 24310192Smitch.hayenga@arm.com if (!mshr->hasTargets() && !mshr->promoteDeferredTargets()) { 24410192Smitch.hayenga@arm.com deallocateOne(mshr); 24510192Smitch.hayenga@arm.com } 24610192Smitch.hayenga@arm.com 24710192Smitch.hayenga@arm.com // Notify if MSHR queue no longer full 24810192Smitch.hayenga@arm.com return was_full && !isFull(); 24910192Smitch.hayenga@arm.com} 25010192Smitch.hayenga@arm.com 2512810SN/Avoid 2522813SN/AMSHRQueue::squash(int threadNum) 2532810SN/A{ 2542810SN/A MSHR::Iterator i = allocatedList.begin(); 2552810SN/A MSHR::Iterator end = allocatedList.end(); 2562810SN/A for (; i != end;) { 2572810SN/A MSHR *mshr = *i; 2582813SN/A if (mshr->threadNum == threadNum) { 2592810SN/A while (mshr->hasTargets()) { 2602810SN/A mshr->popTarget(); 2615715Shsul@eecs.umich.edu assert(0/*target->req->threadId()*/ == threadNum); 2622810SN/A } 2632810SN/A assert(!mshr->hasTargets()); 2649725Sandreas.hansson@arm.com assert(mshr->getNumTargets()==0); 2652810SN/A if (!mshr->inService) { 2662810SN/A i = deallocateOne(mshr); 2672810SN/A } else { 2682810SN/A //mshr->pkt->flags &= ~CACHE_LINE_FILL; 2692810SN/A ++i; 2702810SN/A } 2712810SN/A } else { 2722810SN/A ++i; 2732810SN/A } 2742810SN/A } 2752810SN/A} 2769347SAndreas.Sandberg@arm.com 2779347SAndreas.Sandberg@arm.comunsigned int 2789347SAndreas.Sandberg@arm.comMSHRQueue::drain(DrainManager *dm) 2799347SAndreas.Sandberg@arm.com{ 2809347SAndreas.Sandberg@arm.com if (allocated == 0) { 2819347SAndreas.Sandberg@arm.com setDrainState(Drainable::Drained); 2829347SAndreas.Sandberg@arm.com return 0; 2839347SAndreas.Sandberg@arm.com } else { 2849347SAndreas.Sandberg@arm.com drainManager = dm; 2859347SAndreas.Sandberg@arm.com setDrainState(Drainable::Draining); 2869347SAndreas.Sandberg@arm.com return 1; 2879347SAndreas.Sandberg@arm.com } 2889347SAndreas.Sandberg@arm.com} 289