mshr_queue.cc revision 10679
12810SN/A/*
29725Sandreas.hansson@arm.com * Copyright (c) 2012-2013 ARM Limited
39347SAndreas.Sandberg@arm.com * All rights reserved.
49347SAndreas.Sandberg@arm.com *
59347SAndreas.Sandberg@arm.com * The license below extends only to copyright in the software and shall
69347SAndreas.Sandberg@arm.com * not be construed as granting a license to any other intellectual
79347SAndreas.Sandberg@arm.com * property including but not limited to intellectual property relating
89347SAndreas.Sandberg@arm.com * to a hardware implementation of the functionality of the software
99347SAndreas.Sandberg@arm.com * licensed hereunder.  You may use the software subject to the license
109347SAndreas.Sandberg@arm.com * terms below provided that you ensure that this notice is replicated
119347SAndreas.Sandberg@arm.com * unmodified and in its entirety in all distributions of the software,
129347SAndreas.Sandberg@arm.com * modified or unmodified, in source code or in binary form.
139347SAndreas.Sandberg@arm.com *
142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan
152810SN/A * All rights reserved.
162810SN/A *
172810SN/A * Redistribution and use in source and binary forms, with or without
182810SN/A * modification, are permitted provided that the following conditions are
192810SN/A * met: redistributions of source code must retain the above copyright
202810SN/A * notice, this list of conditions and the following disclaimer;
212810SN/A * redistributions in binary form must reproduce the above copyright
222810SN/A * notice, this list of conditions and the following disclaimer in the
232810SN/A * documentation and/or other materials provided with the distribution;
242810SN/A * neither the name of the copyright holders nor the names of its
252810SN/A * contributors may be used to endorse or promote products derived from
262810SN/A * this software without specific prior written permission.
272810SN/A *
282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
392810SN/A *
402810SN/A * Authors: Erik Hallnor
419347SAndreas.Sandberg@arm.com *          Andreas Sandberg
422810SN/A */
432810SN/A
442810SN/A/** @file
454626SN/A * Definition of MSHRQueue class functions.
462810SN/A */
472810SN/A
4810509SAli.Saidi@ARM.com#include "base/trace.hh"
495338Sstever@gmail.com#include "mem/cache/mshr_queue.hh"
5010509SAli.Saidi@ARM.com#include "debug/Drain.hh"
512810SN/A
522810SN/Ausing namespace std;
532810SN/A
545314SN/AMSHRQueue::MSHRQueue(const std::string &_label,
5510622Smitch.hayenga@arm.com                     int num_entries, int reserve, int demand_reserve,
5610622Smitch.hayenga@arm.com                     int _index)
579725Sandreas.hansson@arm.com    : label(_label), numEntries(num_entries + reserve - 1),
5810622Smitch.hayenga@arm.com      numReserve(reserve), demandReserve(demand_reserve),
5910622Smitch.hayenga@arm.com      registers(numEntries), drainManager(NULL), allocated(0),
6010622Smitch.hayenga@arm.com      inServiceEntries(0), index(_index)
612810SN/A{
624626SN/A    for (int i = 0; i < numEntries; ++i) {
634626SN/A        registers[i].queue = this;
642810SN/A        freeList.push_back(&registers[i]);
652810SN/A    }
662810SN/A}
672810SN/A
684626SN/AMSHR *
6910028SGiacomo.Gabrielli@arm.comMSHRQueue::findMatch(Addr addr, bool is_secure) const
702810SN/A{
712810SN/A    MSHR::ConstIterator i = allocatedList.begin();
722810SN/A    MSHR::ConstIterator end = allocatedList.end();
732810SN/A    for (; i != end; ++i) {
742810SN/A        MSHR *mshr = *i;
7510028SGiacomo.Gabrielli@arm.com        if (mshr->addr == addr && mshr->isSecure == is_secure) {
762810SN/A            return mshr;
772810SN/A        }
782810SN/A    }
792810SN/A    return NULL;
802810SN/A}
812810SN/A
822810SN/Abool
8310028SGiacomo.Gabrielli@arm.comMSHRQueue::findMatches(Addr addr, bool is_secure, vector<MSHR*>& matches) const
842810SN/A{
852810SN/A    // Need an empty vector
862810SN/A    assert(matches.empty());
872810SN/A    bool retval = false;
882810SN/A    MSHR::ConstIterator i = allocatedList.begin();
892810SN/A    MSHR::ConstIterator end = allocatedList.end();
902810SN/A    for (; i != end; ++i) {
912810SN/A        MSHR *mshr = *i;
9210028SGiacomo.Gabrielli@arm.com        if (mshr->addr == addr && mshr->isSecure == is_secure) {
932810SN/A            retval = true;
942810SN/A            matches.push_back(mshr);
952810SN/A        }
962810SN/A    }
972810SN/A    return retval;
984920SN/A}
992810SN/A
1004920SN/A
1014920SN/Abool
1024920SN/AMSHRQueue::checkFunctional(PacketPtr pkt, Addr blk_addr)
1034920SN/A{
1045314SN/A    pkt->pushLabel(label);
1054920SN/A    MSHR::ConstIterator i = allocatedList.begin();
1064920SN/A    MSHR::ConstIterator end = allocatedList.end();
1074920SN/A    for (; i != end; ++i) {
1084920SN/A        MSHR *mshr = *i;
1094920SN/A        if (mshr->addr == blk_addr && mshr->checkFunctional(pkt)) {
1105314SN/A            pkt->popLabel();
1114920SN/A            return true;
1124920SN/A        }
1134920SN/A    }
1145314SN/A    pkt->popLabel();
1154920SN/A    return false;
1162810SN/A}
1172810SN/A
1184920SN/A
1194626SN/AMSHR *
12010028SGiacomo.Gabrielli@arm.comMSHRQueue::findPending(Addr addr, int size, bool is_secure) const
1212810SN/A{
1224666SN/A    MSHR::ConstIterator i = readyList.begin();
1234666SN/A    MSHR::ConstIterator end = readyList.end();
1242810SN/A    for (; i != end; ++i) {
1252810SN/A        MSHR *mshr = *i;
12610028SGiacomo.Gabrielli@arm.com        if (mshr->isSecure == is_secure) {
12710028SGiacomo.Gabrielli@arm.com            if (mshr->addr < addr) {
12810028SGiacomo.Gabrielli@arm.com                if (mshr->addr + mshr->size > addr)
12910028SGiacomo.Gabrielli@arm.com                    return mshr;
13010028SGiacomo.Gabrielli@arm.com            } else {
13110028SGiacomo.Gabrielli@arm.com                if (addr + size > mshr->addr)
13210028SGiacomo.Gabrielli@arm.com                    return mshr;
1332810SN/A            }
1342810SN/A        }
1352810SN/A    }
1362810SN/A    return NULL;
1372810SN/A}
1382810SN/A
1394666SN/A
1404666SN/AMSHR::Iterator
1414666SN/AMSHRQueue::addToReadyList(MSHR *mshr)
1424666SN/A{
1434871SN/A    if (readyList.empty() || readyList.back()->readyTime <= mshr->readyTime) {
1444666SN/A        return readyList.insert(readyList.end(), mshr);
1454666SN/A    }
1464666SN/A
1474666SN/A    MSHR::Iterator i = readyList.begin();
1484666SN/A    MSHR::Iterator end = readyList.end();
1494666SN/A    for (; i != end; ++i) {
1504871SN/A        if ((*i)->readyTime > mshr->readyTime) {
1514666SN/A            return readyList.insert(i, mshr);
1524666SN/A        }
1534666SN/A    }
1544666SN/A    assert(false);
1554904SN/A    return end;  // keep stupid compilers happy
1564666SN/A}
1574666SN/A
1584666SN/A
1594626SN/AMSHR *
1604666SN/AMSHRQueue::allocate(Addr addr, int size, PacketPtr &pkt,
1614666SN/A                    Tick when, Counter order)
1622810SN/A{
1633149SN/A    assert(!freeList.empty());
1642810SN/A    MSHR *mshr = freeList.front();
1652810SN/A    assert(mshr->getNumTargets() == 0);
1662810SN/A    freeList.pop_front();
1672810SN/A
1684666SN/A    mshr->allocate(addr, size, pkt, when, order);
1692810SN/A    mshr->allocIter = allocatedList.insert(allocatedList.end(), mshr);
1704666SN/A    mshr->readyIter = addToReadyList(mshr);
1712810SN/A
1722810SN/A    allocated += 1;
1732810SN/A    return mshr;
1742810SN/A}
1752810SN/A
1762810SN/A
1772810SN/Avoid
1784626SN/AMSHRQueue::deallocate(MSHR *mshr)
1792810SN/A{
1802810SN/A    deallocateOne(mshr);
1812810SN/A}
1822810SN/A
1832810SN/AMSHR::Iterator
1844626SN/AMSHRQueue::deallocateOne(MSHR *mshr)
1852810SN/A{
1862810SN/A    MSHR::Iterator retval = allocatedList.erase(mshr->allocIter);
1872810SN/A    freeList.push_front(mshr);
1882810SN/A    allocated--;
1892810SN/A    if (mshr->inService) {
1904626SN/A        inServiceEntries--;
1912810SN/A    } else {
1924666SN/A        readyList.erase(mshr->readyIter);
1932810SN/A    }
1942810SN/A    mshr->deallocate();
1959347SAndreas.Sandberg@arm.com    if (drainManager && allocated == 0) {
1969347SAndreas.Sandberg@arm.com        // Notify the drain manager that we have completed draining if
1979347SAndreas.Sandberg@arm.com        // there are no other outstanding requests in this MSHR queue.
19810509SAli.Saidi@ARM.com        DPRINTF(Drain, "MSHRQueue now empty, signalling drained\n");
1999347SAndreas.Sandberg@arm.com        drainManager->signalDrainDone();
2009347SAndreas.Sandberg@arm.com        drainManager = NULL;
2019347SAndreas.Sandberg@arm.com        setDrainState(Drainable::Drained);
2029347SAndreas.Sandberg@arm.com    }
2032810SN/A    return retval;
2042810SN/A}
2052810SN/A
2062810SN/Avoid
2072810SN/AMSHRQueue::moveToFront(MSHR *mshr)
2082810SN/A{
2092810SN/A    if (!mshr->inService) {
2102810SN/A        assert(mshr == *(mshr->readyIter));
2114666SN/A        readyList.erase(mshr->readyIter);
2124666SN/A        mshr->readyIter = readyList.insert(readyList.begin(), mshr);
2132810SN/A    }
2142810SN/A}
2152810SN/A
2162810SN/Avoid
21710679Sandreas.hansson@arm.comMSHRQueue::markInService(MSHR *mshr, bool pending_dirty_resp)
2182810SN/A{
21910679Sandreas.hansson@arm.com    if (mshr->markInService(pending_dirty_resp)) {
2202810SN/A        deallocate(mshr);
2214908SN/A    } else {
2224908SN/A        readyList.erase(mshr->readyIter);
2234908SN/A        inServiceEntries += 1;
2242810SN/A    }
2252810SN/A}
2262810SN/A
2272810SN/Avoid
2284626SN/AMSHRQueue::markPending(MSHR *mshr)
2292810SN/A{
2304666SN/A    assert(mshr->inService);
2312810SN/A    mshr->inService = false;
2324626SN/A    --inServiceEntries;
2332810SN/A    /**
2342810SN/A     * @ todo might want to add rerequests to front of pending list for
2352810SN/A     * performance.
2362810SN/A     */
2374666SN/A    mshr->readyIter = addToReadyList(mshr);
2382810SN/A}
2392810SN/A
24010192Smitch.hayenga@arm.combool
24110192Smitch.hayenga@arm.comMSHRQueue::forceDeallocateTarget(MSHR *mshr)
24210192Smitch.hayenga@arm.com{
24310192Smitch.hayenga@arm.com    bool was_full = isFull();
24410192Smitch.hayenga@arm.com    assert(mshr->hasTargets());
24510192Smitch.hayenga@arm.com    // Pop the prefetch off of the target list
24610192Smitch.hayenga@arm.com    mshr->popTarget();
24710192Smitch.hayenga@arm.com    // Delete mshr if no remaining targets
24810192Smitch.hayenga@arm.com    if (!mshr->hasTargets() && !mshr->promoteDeferredTargets()) {
24910192Smitch.hayenga@arm.com        deallocateOne(mshr);
25010192Smitch.hayenga@arm.com    }
25110192Smitch.hayenga@arm.com
25210192Smitch.hayenga@arm.com    // Notify if MSHR queue no longer full
25310192Smitch.hayenga@arm.com    return was_full && !isFull();
25410192Smitch.hayenga@arm.com}
25510192Smitch.hayenga@arm.com
2562810SN/Avoid
2572813SN/AMSHRQueue::squash(int threadNum)
2582810SN/A{
2592810SN/A    MSHR::Iterator i = allocatedList.begin();
2602810SN/A    MSHR::Iterator end = allocatedList.end();
2612810SN/A    for (; i != end;) {
2622810SN/A        MSHR *mshr = *i;
2632813SN/A        if (mshr->threadNum == threadNum) {
2642810SN/A            while (mshr->hasTargets()) {
2652810SN/A                mshr->popTarget();
2665715Shsul@eecs.umich.edu                assert(0/*target->req->threadId()*/ == threadNum);
2672810SN/A            }
2682810SN/A            assert(!mshr->hasTargets());
2699725Sandreas.hansson@arm.com            assert(mshr->getNumTargets()==0);
2702810SN/A            if (!mshr->inService) {
2712810SN/A                i = deallocateOne(mshr);
2722810SN/A            } else {
2732810SN/A                //mshr->pkt->flags &= ~CACHE_LINE_FILL;
2742810SN/A                ++i;
2752810SN/A            }
2762810SN/A        } else {
2772810SN/A            ++i;
2782810SN/A        }
2792810SN/A    }
2802810SN/A}
2819347SAndreas.Sandberg@arm.com
2829347SAndreas.Sandberg@arm.comunsigned int
2839347SAndreas.Sandberg@arm.comMSHRQueue::drain(DrainManager *dm)
2849347SAndreas.Sandberg@arm.com{
2859347SAndreas.Sandberg@arm.com    if (allocated == 0) {
2869347SAndreas.Sandberg@arm.com        setDrainState(Drainable::Drained);
2879347SAndreas.Sandberg@arm.com        return 0;
2889347SAndreas.Sandberg@arm.com    } else {
2899347SAndreas.Sandberg@arm.com        drainManager = dm;
2909347SAndreas.Sandberg@arm.com        setDrainState(Drainable::Draining);
2919347SAndreas.Sandberg@arm.com        return 1;
2929347SAndreas.Sandberg@arm.com    }
2939347SAndreas.Sandberg@arm.com}
294