mshr.hh revision 5318
12810Srdreslin@umich.edu/* 22810Srdreslin@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 32810Srdreslin@umich.edu * All rights reserved. 42810Srdreslin@umich.edu * 52810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 62810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 72810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 82810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 92810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 102810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 112810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 122810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 132810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 142810Srdreslin@umich.edu * this software without specific prior written permission. 152810Srdreslin@umich.edu * 162810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * Authors: Erik Hallnor 292810Srdreslin@umich.edu */ 302810Srdreslin@umich.edu 314458Sstever@eecs.umich.edu/** 322810Srdreslin@umich.edu * @file 332810Srdreslin@umich.edu * Miss Status and Handling Register (MSHR) declaration. 342810Srdreslin@umich.edu */ 352810Srdreslin@umich.edu 362810Srdreslin@umich.edu#ifndef __MSHR_HH__ 372810Srdreslin@umich.edu#define __MSHR_HH__ 382810Srdreslin@umich.edu 392810Srdreslin@umich.edu#include <list> 402810Srdreslin@umich.edu 412810Srdreslin@umich.edu#include "base/printable.hh" 422810Srdreslin@umich.edu#include "mem/packet.hh" 432810Srdreslin@umich.edu 442810Srdreslin@umich.educlass CacheBlk; 453860Sstever@eecs.umich.educlass MSHRQueue; 464626Sstever@eecs.umich.edu 472810Srdreslin@umich.edu/** 484458Sstever@eecs.umich.edu * Miss Status and handling Register. This class keeps all the information 494458Sstever@eecs.umich.edu * needed to handle a cache miss including a list of target requests. 502813Srdreslin@umich.edu */ 513861Sstever@eecs.umich.educlass MSHR : public Packet::SenderState, public Printable 522810Srdreslin@umich.edu{ 532810Srdreslin@umich.edu 542810Srdreslin@umich.edu public: 552810Srdreslin@umich.edu 564672Sstever@eecs.umich.edu class Target { 572810Srdreslin@umich.edu public: 584672Sstever@eecs.umich.edu Tick recvTime; //!< Time when request was received (for stats) 592810Srdreslin@umich.edu Tick readyTime; //!< Time when request is ready to be serviced 602810Srdreslin@umich.edu Counter order; //!< Global order (for memory consistency mgmt) 612810Srdreslin@umich.edu PacketPtr pkt; //!< Pending request packet. 622810Srdreslin@umich.edu bool cpuSide; //!< Did request come from cpu side or mem side? 632810Srdreslin@umich.edu bool markedPending; //!< Did we mark upstream MSHR 643860Sstever@eecs.umich.edu //!< as downstreamPending? 653860Sstever@eecs.umich.edu 662810Srdreslin@umich.edu bool isCpuSide() const { return cpuSide; } 672810Srdreslin@umich.edu 683738Sstever@eecs.umich.edu Target(PacketPtr _pkt, Tick _readyTime, Counter _order, 692810Srdreslin@umich.edu bool _cpuSide, bool _markedPending) 702810Srdreslin@umich.edu : recvTime(curTick), readyTime(_readyTime), order(_order), 713738Sstever@eecs.umich.edu pkt(_pkt), cpuSide(_cpuSide), markedPending(_markedPending) 723738Sstever@eecs.umich.edu {} 733738Sstever@eecs.umich.edu }; 743738Sstever@eecs.umich.edu 754672Sstever@eecs.umich.edu class TargetList : public std::list<Target> { 763738Sstever@eecs.umich.edu /** Target list iterator. */ 773738Sstever@eecs.umich.edu typedef std::list<Target>::iterator Iterator; 783738Sstever@eecs.umich.edu typedef std::list<Target>::const_iterator ConstIterator; 793738Sstever@eecs.umich.edu 804672Sstever@eecs.umich.edu public: 814672Sstever@eecs.umich.edu bool needsExclusive; 823738Sstever@eecs.umich.edu bool hasUpgrade; 833738Sstever@eecs.umich.edu 844478Sstever@eecs.umich.edu TargetList(); 854478Sstever@eecs.umich.edu void resetFlags() { needsExclusive = hasUpgrade = false; } 864478Sstever@eecs.umich.edu bool isReset() { return !needsExclusive && !hasUpgrade; } 873738Sstever@eecs.umich.edu void add(PacketPtr pkt, Tick readyTime, Counter order, 883738Sstever@eecs.umich.edu bool cpuSide, bool markPending); 893738Sstever@eecs.umich.edu void replaceUpgrades(); 903738Sstever@eecs.umich.edu void clearDownstreamPending(); 913738Sstever@eecs.umich.edu bool checkFunctional(PacketPtr pkt); 923738Sstever@eecs.umich.edu void print(std::ostream &os, int verbosity, 933738Sstever@eecs.umich.edu const std::string &prefix) const; 943738Sstever@eecs.umich.edu }; 953738Sstever@eecs.umich.edu 963738Sstever@eecs.umich.edu /** A list of MSHRs. */ 973738Sstever@eecs.umich.edu typedef std::list<MSHR *> List; 984672Sstever@eecs.umich.edu /** MSHR list iterator. */ 993738Sstever@eecs.umich.edu typedef List::iterator Iterator; 1003738Sstever@eecs.umich.edu /** MSHR list const_iterator. */ 1013738Sstever@eecs.umich.edu typedef List::const_iterator ConstIterator; 1023738Sstever@eecs.umich.edu 1034672Sstever@eecs.umich.edu /** Pointer to queue containing this MSHR. */ 1044672Sstever@eecs.umich.edu MSHRQueue *queue; 1053738Sstever@eecs.umich.edu 1063738Sstever@eecs.umich.edu /** Cycle when ready to issue */ 1074626Sstever@eecs.umich.edu Tick readyTime; 1084626Sstever@eecs.umich.edu 1094626Sstever@eecs.umich.edu /** Order number assigned by the miss queue. */ 1104458Sstever@eecs.umich.edu Counter order; 1114478Sstever@eecs.umich.edu 1124478Sstever@eecs.umich.edu /** Address of the request. */ 1134478Sstever@eecs.umich.edu Addr addr; 1143738Sstever@eecs.umich.edu 1153738Sstever@eecs.umich.edu /** Size of the request. */ 1164458Sstever@eecs.umich.edu int size; 1174458Sstever@eecs.umich.edu 1183738Sstever@eecs.umich.edu /** True if the request has been sent to the bus. */ 1193738Sstever@eecs.umich.edu bool inService; 1203738Sstever@eecs.umich.edu 1214458Sstever@eecs.umich.edu /** True if we will be putting the returned block in the cache */ 1224626Sstever@eecs.umich.edu bool isCacheFill; 1234626Sstever@eecs.umich.edu 1243738Sstever@eecs.umich.edu /** True if we need to get an exclusive copy of the block. */ 1253738Sstever@eecs.umich.edu bool needsExclusive() const { return targets->needsExclusive; } 1262810Srdreslin@umich.edu 1272810Srdreslin@umich.edu /** True if the request is uncacheable */ 1284626Sstever@eecs.umich.edu bool _isUncacheable; 1292810Srdreslin@umich.edu 1303861Sstever@eecs.umich.edu bool downstreamPending; 1312810Srdreslin@umich.edu 1324671Sstever@eecs.umich.edu bool pendingInvalidate; 1334671Sstever@eecs.umich.edu bool pendingShared; 1344671Sstever@eecs.umich.edu 1352810Srdreslin@umich.edu /** Thread number of the miss. */ 1363860Sstever@eecs.umich.edu short threadNum; 1373860Sstever@eecs.umich.edu /** The number of currently allocated targets. */ 1383860Sstever@eecs.umich.edu short ntargets; 1393860Sstever@eecs.umich.edu 1403860Sstever@eecs.umich.edu 1413860Sstever@eecs.umich.edu /** Data buffer (if needed). Currently used only for pending 1423860Sstever@eecs.umich.edu * upgrade handling. */ 1433860Sstever@eecs.umich.edu uint8_t *data; 1443860Sstever@eecs.umich.edu 1453860Sstever@eecs.umich.edu /** 1463860Sstever@eecs.umich.edu * Pointer to this MSHR on the ready list. 1473860Sstever@eecs.umich.edu * @sa MissQueue, MSHRQueue::readyList 1483860Sstever@eecs.umich.edu */ 1494626Sstever@eecs.umich.edu Iterator readyIter; 1503860Sstever@eecs.umich.edu 1513860Sstever@eecs.umich.edu /** 1523860Sstever@eecs.umich.edu * Pointer to this MSHR on the allocated list. 1533860Sstever@eecs.umich.edu * @sa MissQueue, MSHRQueue::allocatedList 1543860Sstever@eecs.umich.edu */ 1553860Sstever@eecs.umich.edu Iterator allocIter; 1563860Sstever@eecs.umich.edu 1573860Sstever@eecs.umich.eduprivate: 1583860Sstever@eecs.umich.edu /** List of all requests that match the address */ 1593860Sstever@eecs.umich.edu TargetList *targets; 1603860Sstever@eecs.umich.edu 1614628Sstever@eecs.umich.edu TargetList *deferredTargets; 1624219Srdreslin@umich.edu 1634219Srdreslin@umich.edupublic: 1644219Srdreslin@umich.edu 1654219Srdreslin@umich.edu bool isUncacheable() { return _isUncacheable; } 1664626Sstever@eecs.umich.edu 1673860Sstever@eecs.umich.edu /** 1683860Sstever@eecs.umich.edu * Allocate a miss to this MSHR. 1693860Sstever@eecs.umich.edu * @param cmd The requesting command. 1703860Sstever@eecs.umich.edu * @param addr The address of the miss. 1713860Sstever@eecs.umich.edu * @param asid The address space id of the miss. 1723860Sstever@eecs.umich.edu * @param size The number of bytes to request. 1734626Sstever@eecs.umich.edu * @param pkt The original miss. 1743860Sstever@eecs.umich.edu */ 1753860Sstever@eecs.umich.edu void allocate(Addr addr, int size, PacketPtr pkt, 1763860Sstever@eecs.umich.edu Tick when, Counter _order); 1773860Sstever@eecs.umich.edu 1784626Sstever@eecs.umich.edu bool markInService(); 1794626Sstever@eecs.umich.edu 1803860Sstever@eecs.umich.edu void clearDownstreamPending(); 1814665Sstever@eecs.umich.edu 1824628Sstever@eecs.umich.edu /** 1834626Sstever@eecs.umich.edu * Mark this MSHR as free. 1844670Sstever@eecs.umich.edu */ 1854670Sstever@eecs.umich.edu void deallocate(); 1863860Sstever@eecs.umich.edu 1873860Sstever@eecs.umich.edu /** 1883860Sstever@eecs.umich.edu * Add a request to the list of targets. 1893860Sstever@eecs.umich.edu * @param target The target. 1903860Sstever@eecs.umich.edu */ 1913860Sstever@eecs.umich.edu void allocateTarget(PacketPtr target, Tick when, Counter order); 1924670Sstever@eecs.umich.edu bool handleSnoop(PacketPtr target, Counter order); 1934670Sstever@eecs.umich.edu 1943860Sstever@eecs.umich.edu /** A simple constructor. */ 1953860Sstever@eecs.umich.edu MSHR(); 1963860Sstever@eecs.umich.edu /** A simple destructor. */ 1973860Sstever@eecs.umich.edu ~MSHR(); 1983860Sstever@eecs.umich.edu 1993860Sstever@eecs.umich.edu /** 2003860Sstever@eecs.umich.edu * Returns the current number of allocated targets. 2013860Sstever@eecs.umich.edu * @return The current number of allocated targets. 2022810Srdreslin@umich.edu */ 2032810Srdreslin@umich.edu int getNumTargets() { return ntargets; } 2042810Srdreslin@umich.edu 2052810Srdreslin@umich.edu /** 2062810Srdreslin@umich.edu * Returns a pointer to the target list. 2072810Srdreslin@umich.edu * @return a pointer to the target list. 2082810Srdreslin@umich.edu */ 2093861Sstever@eecs.umich.edu TargetList *getTargetList() { return targets; } 2102810Srdreslin@umich.edu 2113860Sstever@eecs.umich.edu /** 2123860Sstever@eecs.umich.edu * Returns true if there are targets left. 2132810Srdreslin@umich.edu * @return true if there are targets 2144672Sstever@eecs.umich.edu */ 2153315Sstever@eecs.umich.edu bool hasTargets() { return !targets->empty(); } 2163861Sstever@eecs.umich.edu 2173860Sstever@eecs.umich.edu /** 2183860Sstever@eecs.umich.edu * Returns a reference to the first target. 2193860Sstever@eecs.umich.edu * @return A pointer to the first target. 2204672Sstever@eecs.umich.edu */ 2213315Sstever@eecs.umich.edu Target *getTarget() { assert(hasTargets()); return &targets->front(); } 2222813Srdreslin@umich.edu 2233860Sstever@eecs.umich.edu /** 2244626Sstever@eecs.umich.edu * Pop first target. 2252810Srdreslin@umich.edu */ 2262810Srdreslin@umich.edu void popTarget() 2272810Srdreslin@umich.edu { 2282810Srdreslin@umich.edu --ntargets; 2292810Srdreslin@umich.edu targets->pop_front(); 2302812Srdreslin@umich.edu } 2312810Srdreslin@umich.edu 2323738Sstever@eecs.umich.edu bool isSimpleForward() 2334190Ssaidi@eecs.umich.edu { 2342813Srdreslin@umich.edu if (getNumTargets() != 1) 2352810Srdreslin@umich.edu return false; 2362810Srdreslin@umich.edu Target *tgt = getTarget(); 2372810Srdreslin@umich.edu return tgt->isCpuSide() && !tgt->pkt->needsResponse(); 2382810Srdreslin@umich.edu } 2392982Sstever@eecs.umich.edu 2402810Srdreslin@umich.edu bool promoteDeferredTargets(); 2412810Srdreslin@umich.edu 2424626Sstever@eecs.umich.edu void handleFill(Packet *pkt, CacheBlk *blk); 2432810Srdreslin@umich.edu 2442810Srdreslin@umich.edu bool checkFunctional(PacketPtr pkt); 2454626Sstever@eecs.umich.edu 2464626Sstever@eecs.umich.edu /** 2474626Sstever@eecs.umich.edu * Prints the contents of this MSHR for debugging. 2482810Srdreslin@umich.edu */ 2494626Sstever@eecs.umich.edu void print(std::ostream &os, 2502810Srdreslin@umich.edu int verbosity = 0, 2512810Srdreslin@umich.edu const std::string &prefix = "") const; 2524626Sstever@eecs.umich.edu}; 2534626Sstever@eecs.umich.edu 2544626Sstever@eecs.umich.edu#endif //__MSHR_HH__ 2552810Srdreslin@umich.edu