mshr.hh revision 11741
1/* 2 * Copyright (c) 2012-2013, 2015-2016 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 */ 42 43/** 44 * @file 45 * Miss Status and Handling Register (MSHR) declaration. 46 */ 47 48#ifndef __MEM_CACHE_MSHR_HH__ 49#define __MEM_CACHE_MSHR_HH__ 50 51#include <list> 52 53#include "base/printable.hh" 54#include "mem/cache/queue_entry.hh" 55 56class Cache; 57 58/** 59 * Miss Status and handling Register. This class keeps all the information 60 * needed to handle a cache miss including a list of target requests. 61 * @sa \ref gem5MemorySystem "gem5 Memory System" 62 */ 63class MSHR : public QueueEntry, public Printable 64{ 65 66 /** 67 * Consider the queues friends to avoid making everything public. 68 */ 69 template<typename Entry> 70 friend class Queue; 71 friend class MSHRQueue; 72 73 private: 74 75 /** Flag set by downstream caches */ 76 bool downstreamPending; 77 78 /** 79 * Here we use one flag to track both if: 80 * 81 * 1. We are going to become owner or not, i.e., we will get the 82 * block in an ownership state (Owned or Modified) with BlkDirty 83 * set. This determines whether or not we are going to become the 84 * responder and ordering point for future requests that we snoop. 85 * 86 * 2. We know that we are going to get a writable block, i.e. we 87 * will get the block in writable state (Exclusive or Modified 88 * state) with BlkWritable set. That determines whether additional 89 * targets with needsWritable set will be able to be satisfied, or 90 * if not should be put on the deferred list to possibly wait for 91 * another request that does give us writable access. 92 * 93 * Condition 2 is actually just a shortcut that saves us from 94 * possibly building a deferred target list and calling 95 * promoteWritable() every time we get a writable block. Condition 96 * 1, tracking ownership, is what is important. However, we never 97 * receive ownership without marking the block dirty, and 98 * consequently use pendingModified to track both ownership and 99 * writability rather than having separate pendingDirty and 100 * pendingWritable flags. 101 */ 102 bool pendingModified; 103 104 /** Did we snoop an invalidate while waiting for data? */ 105 bool postInvalidate; 106 107 /** Did we snoop a read while waiting for data? */ 108 bool postDowngrade; 109 110 public: 111 112 /** True if the entry is just a simple forward from an upper level */ 113 bool isForward; 114 115 class Target { 116 public: 117 118 enum Source { 119 FromCPU, 120 FromSnoop, 121 FromPrefetcher 122 }; 123 124 const Tick recvTime; //!< Time when request was received (for stats) 125 const Tick readyTime; //!< Time when request is ready to be serviced 126 const Counter order; //!< Global order (for memory consistency mgmt) 127 const PacketPtr pkt; //!< Pending request packet. 128 const Source source; //!< Request from cpu, memory, or prefetcher? 129 const bool markedPending; //!< Did we mark upstream MSHR 130 //!< as downstreamPending? 131 const bool allocOnFill; //!< Should the response servicing this 132 //!< target list allocate in the cache? 133 134 Target(PacketPtr _pkt, Tick _readyTime, Counter _order, 135 Source _source, bool _markedPending, bool alloc_on_fill) 136 : recvTime(curTick()), readyTime(_readyTime), order(_order), 137 pkt(_pkt), source(_source), markedPending(_markedPending), 138 allocOnFill(alloc_on_fill) 139 {} 140 }; 141 142 class TargetList : public std::list<Target> { 143 144 public: 145 bool needsWritable; 146 bool hasUpgrade; 147 /** Set when the response should allocate on fill */ 148 bool allocOnFill; 149 150 TargetList(); 151 152 /** 153 * Use the provided packet and the source to update the 154 * flags of this TargetList. 155 * 156 * @param pkt Packet considered for the flag update 157 * @param source Indicates the source of the packet 158 * @param alloc_on_fill Whether the pkt would allocate on a fill 159 */ 160 void updateFlags(PacketPtr pkt, Target::Source source, 161 bool alloc_on_fill); 162 163 void resetFlags() { needsWritable = hasUpgrade = allocOnFill = false; } 164 165 /** 166 * Goes through the list of targets and uses them to populate 167 * the flags of this TargetList. When the function returns the 168 * flags are consistent with the properties of packets in the 169 * list. 170 */ 171 void populateFlags(); 172 173 /** 174 * Tests if the flags of this TargetList have their default 175 * values. 176 */ 177 bool isReset() const { 178 return !needsWritable && !hasUpgrade && !allocOnFill; 179 } 180 181 /** 182 * Add the specified packet in the TargetList. This function 183 * stores information related to the added packet and updates 184 * accordingly the flags. 185 * 186 * @param pkt Packet considered for adding 187 * @param readTime Tick at which the packet is processed by this cache 188 * @param order A counter giving a unique id to each target 189 * @param source Indicates the source agent of the packet 190 * @param markPending Set for deferred targets or pending MSHRs 191 * @param alloc_on_fill Whether it should allocate on a fill 192 */ 193 void add(PacketPtr pkt, Tick readyTime, Counter order, 194 Target::Source source, bool markPending, 195 bool alloc_on_fill); 196 197 /** 198 * Convert upgrades to the equivalent request if the cache line they 199 * refer to would have been invalid (Upgrade -> ReadEx, SC* -> Fail). 200 * Used to rejig ordering between targets waiting on an MSHR. */ 201 void replaceUpgrades(); 202 203 void clearDownstreamPending(); 204 bool checkFunctional(PacketPtr pkt); 205 void print(std::ostream &os, int verbosity, 206 const std::string &prefix) const; 207 }; 208 209 /** A list of MSHRs. */ 210 typedef std::list<MSHR *> List; 211 /** MSHR list iterator. */ 212 typedef List::iterator Iterator; 213 214 /** The pending* and post* flags are only valid if inService is 215 * true. Using the accessor functions lets us detect if these 216 * flags are accessed improperly. 217 */ 218 219 /** True if we need to get a writable copy of the block. */ 220 bool needsWritable() const { return targets.needsWritable; } 221 222 bool isPendingModified() const { 223 assert(inService); return pendingModified; 224 } 225 226 bool hasPostInvalidate() const { 227 assert(inService); return postInvalidate; 228 } 229 230 bool hasPostDowngrade() const { 231 assert(inService); return postDowngrade; 232 } 233 234 bool sendPacket(Cache &cache); 235 236 bool allocOnFill() const { 237 return targets.allocOnFill; 238 } 239 private: 240 241 /** 242 * Pointer to this MSHR on the ready list. 243 * @sa MissQueue, MSHRQueue::readyList 244 */ 245 Iterator readyIter; 246 247 /** 248 * Pointer to this MSHR on the allocated list. 249 * @sa MissQueue, MSHRQueue::allocatedList 250 */ 251 Iterator allocIter; 252 253 /** List of all requests that match the address */ 254 TargetList targets; 255 256 TargetList deferredTargets; 257 258 public: 259 260 /** 261 * Allocate a miss to this MSHR. 262 * @param blk_addr The address of the block. 263 * @param blk_size The number of bytes to request. 264 * @param pkt The original miss. 265 * @param when_ready When should the MSHR be ready to act upon. 266 * @param _order The logical order of this MSHR 267 * @param alloc_on_fill Should the cache allocate a block on fill 268 */ 269 void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt, 270 Tick when_ready, Counter _order, bool alloc_on_fill); 271 272 void markInService(bool pending_modified_resp); 273 274 void clearDownstreamPending(); 275 276 /** 277 * Mark this MSHR as free. 278 */ 279 void deallocate(); 280 281 /** 282 * Add a request to the list of targets. 283 * @param target The target. 284 */ 285 void allocateTarget(PacketPtr target, Tick when, Counter order, 286 bool alloc_on_fill); 287 bool handleSnoop(PacketPtr target, Counter order); 288 289 /** A simple constructor. */ 290 MSHR(); 291 292 /** 293 * Returns the current number of allocated targets. 294 * @return The current number of allocated targets. 295 */ 296 int getNumTargets() const 297 { return targets.size() + deferredTargets.size(); } 298 299 /** 300 * Returns true if there are targets left. 301 * @return true if there are targets 302 */ 303 bool hasTargets() const { return !targets.empty(); } 304 305 /** 306 * Returns a reference to the first target. 307 * @return A pointer to the first target. 308 */ 309 Target *getTarget() 310 { 311 assert(hasTargets()); 312 return &targets.front(); 313 } 314 315 /** 316 * Pop first target. 317 */ 318 void popTarget() 319 { 320 targets.pop_front(); 321 } 322 323 bool promoteDeferredTargets(); 324 325 void promoteWritable(); 326 327 bool checkFunctional(PacketPtr pkt); 328 329 /** 330 * Prints the contents of this MSHR for debugging. 331 */ 332 void print(std::ostream &os, 333 int verbosity = 0, 334 const std::string &prefix = "") const; 335 /** 336 * A no-args wrapper of print(std::ostream...) meant to be 337 * invoked from DPRINTFs avoiding string overheads in fast mode 338 * 339 * @return string with mshr fields + [deferred]targets 340 */ 341 std::string print() const; 342}; 343 344#endif // __MEM_CACHE_MSHR_HH__ 345