mshr.hh revision 11375 
1/*
2 * Copyright (c) 2012-2013, 2015-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Miss Status and Handling Register (MSHR) declaration.
46 */
47
48#ifndef __MEM_CACHE_MSHR_HH__
49#define __MEM_CACHE_MSHR_HH__
50
51#include <list>
52
53#include "base/printable.hh"
54#include "mem/cache/queue_entry.hh"
55
56class Cache;
57
58/**
59 * Miss Status and handling Register. This class keeps all the information
60 * needed to handle a cache miss including a list of target requests.
61 * @sa  \ref gem5MemorySystem "gem5 Memory System"
62 */
63class MSHR : public QueueEntry, public Printable
64{
65
66    /**
67     * Consider the queues friends to avoid making everything public.
68     */
69    template<typename Entry>
70    friend class Queue;
71    friend class MSHRQueue;
72
73  private:
74
75    /** Flag set by downstream caches */
76    bool downstreamPending;
77
78    /**
79     * Here we use one flag to track both if:
80     *
81     * 1. We are going to become owner or not, i.e., we will get the
82     * block in an ownership state (Owned or Modified) with BlkDirty
83     * set. This determines whether or not we are going to become the
84     * responder and ordering point for future requests that we snoop.
85     *
86     * 2. We know that we are going to get a writable block, i.e. we
87     * will get the block in writable state (Exclusive or Modified
88     * state) with BlkWritable set. That determines whether additional
89     * targets with needsWritable set will be able to be satisfied, or
90     * if not should be put on the deferred list to possibly wait for
91     * another request that does give us writable access.
92     *
93     * Condition 2 is actually just a shortcut that saves us from
94     * possibly building a deferred target list and calling
95     * promoteWritable() every time we get a writable block. Condition
96     * 1, tracking ownership, is what is important. However, we never
97     * receive ownership without marking the block dirty, and
98     * consequently use pendingModified to track both ownership and
99     * writability rather than having separate pendingDirty and
100     * pendingWritable flags.
101     */
102    bool pendingModified;
103
104    /** Did we snoop an invalidate while waiting for data? */
105    bool postInvalidate;
106
107    /** Did we snoop a read while waiting for data? */
108    bool postDowngrade;
109
110  public:
111
112    /** True if the entry is just a simple forward from an upper level */
113    bool isForward;
114
115    class Target {
116      public:
117
118        enum Source {
119            FromCPU,
120            FromSnoop,
121            FromPrefetcher
122        };
123
124        const Tick recvTime;  //!< Time when request was received (for stats)
125        const Tick readyTime; //!< Time when request is ready to be serviced
126        const Counter order;  //!< Global order (for memory consistency mgmt)
127        const PacketPtr pkt;  //!< Pending request packet.
128        const Source source;  //!< Request from cpu, memory, or prefetcher?
129        const bool markedPending; //!< Did we mark upstream MSHR
130                                  //!< as downstreamPending?
131
132        Target(PacketPtr _pkt, Tick _readyTime, Counter _order,
133               Source _source, bool _markedPending)
134            : recvTime(curTick()), readyTime(_readyTime), order(_order),
135              pkt(_pkt), source(_source), markedPending(_markedPending)
136        {}
137    };
138
139    class TargetList : public std::list<Target> {
140
141      public:
142        bool needsWritable;
143        bool hasUpgrade;
144
145        TargetList();
146        void resetFlags() { needsWritable = hasUpgrade = false; }
147        bool isReset() const { return !needsWritable && !hasUpgrade; }
148        void add(PacketPtr pkt, Tick readyTime, Counter order,
149                 Target::Source source, bool markPending);
150
151        /**
152         * Convert upgrades to the equivalent request if the cache line they
153         * refer to would have been invalid (Upgrade -> ReadEx, SC* -> Fail).
154         * Used to rejig ordering between targets waiting on an MSHR. */
155        void replaceUpgrades();
156
157        void clearDownstreamPending();
158        bool checkFunctional(PacketPtr pkt);
159        void print(std::ostream &os, int verbosity,
160                   const std::string &prefix) const;
161    };
162
163    /** A list of MSHRs. */
164    typedef std::list<MSHR *> List;
165    /** MSHR list iterator. */
166    typedef List::iterator Iterator;
167
168    /** Keep track of whether we should allocate on fill or not */
169    bool allocOnFill;
170
171    /** The pending* and post* flags are only valid if inService is
172     *  true.  Using the accessor functions lets us detect if these
173     *  flags are accessed improperly.
174     */
175
176    /** True if we need to get a writable copy of the block. */
177    bool needsWritable() const { return targets.needsWritable; }
178
179    bool isPendingModified() const {
180        assert(inService); return pendingModified;
181    }
182
183    bool hasPostInvalidate() const {
184        assert(inService); return postInvalidate;
185    }
186
187    bool hasPostDowngrade() const {
188        assert(inService); return postDowngrade;
189    }
190
191    bool sendPacket(Cache &cache);
192
193  private:
194
195    /**
196     * Pointer to this MSHR on the ready list.
197     * @sa MissQueue, MSHRQueue::readyList
198     */
199    Iterator readyIter;
200
201    /**
202     * Pointer to this MSHR on the allocated list.
203     * @sa MissQueue, MSHRQueue::allocatedList
204     */
205    Iterator allocIter;
206
207    /** List of all requests that match the address */
208    TargetList targets;
209
210    TargetList deferredTargets;
211
212  public:
213
214    /**
215     * Allocate a miss to this MSHR.
216     * @param blk_addr The address of the block.
217     * @param blk_size The number of bytes to request.
218     * @param pkt The original miss.
219     * @param when_ready When should the MSHR be ready to act upon.
220     * @param _order The logical order of this MSHR
221     * @param alloc_on_fill Should the cache allocate a block on fill
222     */
223    void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt,
224                  Tick when_ready, Counter _order, bool alloc_on_fill);
225
226    void markInService(bool pending_modified_resp);
227
228    void clearDownstreamPending();
229
230    /**
231     * Mark this MSHR as free.
232     */
233    void deallocate();
234
235    /**
236     * Add a request to the list of targets.
237     * @param target The target.
238     */
239    void allocateTarget(PacketPtr target, Tick when, Counter order,
240                        bool alloc_on_fill);
241    bool handleSnoop(PacketPtr target, Counter order);
242
243    /** A simple constructor. */
244    MSHR();
245
246    /**
247     * Returns the current number of allocated targets.
248     * @return The current number of allocated targets.
249     */
250    int getNumTargets() const
251    { return targets.size() + deferredTargets.size(); }
252
253    /**
254     * Returns true if there are targets left.
255     * @return true if there are targets
256     */
257    bool hasTargets() const { return !targets.empty(); }
258
259    /**
260     * Returns a reference to the first target.
261     * @return A pointer to the first target.
262     */
263    Target *getTarget()
264    {
265        assert(hasTargets());
266        return &targets.front();
267    }
268
269    /**
270     * Pop first target.
271     */
272    void popTarget()
273    {
274        targets.pop_front();
275    }
276
277    bool promoteDeferredTargets();
278
279    void promoteWritable();
280
281    bool checkFunctional(PacketPtr pkt);
282
283    /**
284     * Prints the contents of this MSHR for debugging.
285     */
286    void print(std::ostream &os,
287               int verbosity = 0,
288               const std::string &prefix = "") const;
289    /**
290     * A no-args wrapper of print(std::ostream...)  meant to be
291     * invoked from DPRINTFs avoiding string overheads in fast mode
292     *
293     * @return string with mshr fields + [deferred]targets
294     */
295    std::string print() const;
296};
297
298#endif // __MEM_CACHE_MSHR_HH__
299