mshr.hh revision 11357 
1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 */
42
43/**
44 * @file
45 * Miss Status and Handling Register (MSHR) declaration.
46 */
47
48#ifndef __MEM_CACHE_MSHR_HH__
49#define __MEM_CACHE_MSHR_HH__
50
51#include <list>
52
53#include "base/printable.hh"
54#include "mem/packet.hh"
55
56class CacheBlk;
57class MSHRQueue;
58
59/**
60 * Miss Status and handling Register. This class keeps all the information
61 * needed to handle a cache miss including a list of target requests.
62 * @sa  \ref gem5MemorySystem "gem5 Memory System"
63 */
64class MSHR : public Packet::SenderState, public Printable
65{
66
67    /**
68     * Consider the MSHRQueue a friend to avoid making everything public
69     */
70    friend class MSHRQueue;
71
72  private:
73
74    /** Cycle when ready to issue */
75    Tick readyTime;
76
77    /** True if the request is uncacheable */
78    bool _isUncacheable;
79
80    /** Flag set by downstream caches */
81    bool downstreamPending;
82
83    /**
84     * Here we use one flag to track both if:
85     *
86     * 1. We are going to become owner or not, i.e., we will get the
87     * block in an ownership state (Owned or Modified) with BlkDirty
88     * set. This determines whether or not we are going to become the
89     * responder and ordering point for future requests that we snoop.
90     *
91     * 2. We know that we are going to get a writable block, i.e. we
92     * will get the block in writable state (Exclusive or Modified
93     * state) with BlkWritable set. That determines whether additional
94     * targets with needsWritable set will be able to be satisfied, or
95     * if not should be put on the deferred list to possibly wait for
96     * another request that does give us writable access.
97     *
98     * Condition 2 is actually just a shortcut that saves us from
99     * possibly building a deferred target list and calling
100     * promoteWritable() every time we get a writable block. Condition
101     * 1, tracking ownership, is what is important. However, we never
102     * receive ownership without marking the block dirty, and
103     * consequently use pendingModified to track both ownership and
104     * writability rather than having separate pendingDirty and
105     * pendingWritable flags.
106     */
107    bool pendingModified;
108
109    /** Did we snoop an invalidate while waiting for data? */
110    bool postInvalidate;
111
112    /** Did we snoop a read while waiting for data? */
113    bool postDowngrade;
114
115  public:
116
117    class Target {
118      public:
119
120        enum Source {
121            FromCPU,
122            FromSnoop,
123            FromPrefetcher
124        };
125
126        const Tick recvTime;  //!< Time when request was received (for stats)
127        const Tick readyTime; //!< Time when request is ready to be serviced
128        const Counter order;  //!< Global order (for memory consistency mgmt)
129        const PacketPtr pkt;  //!< Pending request packet.
130        const Source source;  //!< Request from cpu, memory, or prefetcher?
131        const bool markedPending; //!< Did we mark upstream MSHR
132                                  //!< as downstreamPending?
133
134        Target(PacketPtr _pkt, Tick _readyTime, Counter _order,
135               Source _source, bool _markedPending)
136            : recvTime(curTick()), readyTime(_readyTime), order(_order),
137              pkt(_pkt), source(_source), markedPending(_markedPending)
138        {}
139    };
140
141    class TargetList : public std::list<Target> {
142
143      public:
144        bool needsWritable;
145        bool hasUpgrade;
146
147        TargetList();
148        void resetFlags() { needsWritable = hasUpgrade = false; }
149        bool isReset() const { return !needsWritable && !hasUpgrade; }
150        void add(PacketPtr pkt, Tick readyTime, Counter order,
151                 Target::Source source, bool markPending);
152
153        /**
154         * Convert upgrades to the equivalent request if the cache line they
155         * refer to would have been invalid (Upgrade -> ReadEx, SC* -> Fail).
156         * Used to rejig ordering between targets waiting on an MSHR. */
157        void replaceUpgrades();
158
159        void clearDownstreamPending();
160        bool checkFunctional(PacketPtr pkt);
161        void print(std::ostream &os, int verbosity,
162                   const std::string &prefix) const;
163    };
164
165    /** A list of MSHRs. */
166    typedef std::list<MSHR *> List;
167    /** MSHR list iterator. */
168    typedef List::iterator Iterator;
169    /** MSHR list const_iterator. */
170    typedef List::const_iterator ConstIterator;
171
172    /** Pointer to queue containing this MSHR. */
173    MSHRQueue *queue;
174
175    /** Order number assigned by the miss queue. */
176    Counter order;
177
178    /** Block aligned address of the MSHR. */
179    Addr blkAddr;
180
181    /** Block size of the cache. */
182    unsigned blkSize;
183
184    /** True if the request targets the secure memory space. */
185    bool isSecure;
186
187    /** True if the request has been sent to the bus. */
188    bool inService;
189
190    /** True if the request is just a simple forward from an upper level */
191    bool isForward;
192
193    /** Keep track of whether we should allocate on fill or not */
194    bool allocOnFill;
195
196    /** The pending* and post* flags are only valid if inService is
197     *  true.  Using the accessor functions lets us detect if these
198     *  flags are accessed improperly.
199     */
200
201    /** True if we need to get a writable copy of the block. */
202    bool needsWritable() const { return targets.needsWritable; }
203
204    bool isPendingModified() const {
205        assert(inService); return pendingModified;
206    }
207
208    bool hasPostInvalidate() const {
209        assert(inService); return postInvalidate;
210    }
211
212    bool hasPostDowngrade() const {
213        assert(inService); return postDowngrade;
214    }
215
216  private:
217
218    /** Data buffer (if needed).  Currently used only for pending
219     * upgrade handling. */
220    uint8_t *data;
221
222    /**
223     * Pointer to this MSHR on the ready list.
224     * @sa MissQueue, MSHRQueue::readyList
225     */
226    Iterator readyIter;
227
228    /**
229     * Pointer to this MSHR on the allocated list.
230     * @sa MissQueue, MSHRQueue::allocatedList
231     */
232    Iterator allocIter;
233
234    /** List of all requests that match the address */
235    TargetList targets;
236
237    TargetList deferredTargets;
238
239  public:
240
241    bool isUncacheable() const { return _isUncacheable; }
242
243    /**
244     * Allocate a miss to this MSHR.
245     * @param blk_addr The address of the block.
246     * @param blk_size The number of bytes to request.
247     * @param pkt The original miss.
248     * @param when_ready When should the MSHR be ready to act upon.
249     * @param _order The logical order of this MSHR
250     * @param alloc_on_fill Should the cache allocate a block on fill
251     */
252    void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt,
253                  Tick when_ready, Counter _order, bool alloc_on_fill);
254
255    bool markInService(bool pending_modified_resp);
256
257    void clearDownstreamPending();
258
259    /**
260     * Mark this MSHR as free.
261     */
262    void deallocate();
263
264    /**
265     * Add a request to the list of targets.
266     * @param target The target.
267     */
268    void allocateTarget(PacketPtr target, Tick when, Counter order,
269                        bool alloc_on_fill);
270    bool handleSnoop(PacketPtr target, Counter order);
271
272    /** A simple constructor. */
273    MSHR();
274
275    /**
276     * Returns the current number of allocated targets.
277     * @return The current number of allocated targets.
278     */
279    int getNumTargets() const
280    { return targets.size() + deferredTargets.size(); }
281
282    /**
283     * Returns true if there are targets left.
284     * @return true if there are targets
285     */
286    bool hasTargets() const { return !targets.empty(); }
287
288    /**
289     * Returns a reference to the first target.
290     * @return A pointer to the first target.
291     */
292    Target *getTarget()
293    {
294        assert(hasTargets());
295        return &targets.front();
296    }
297
298    /**
299     * Pop first target.
300     */
301    void popTarget()
302    {
303        targets.pop_front();
304    }
305
306    bool isForwardNoResponse() const
307    {
308        if (getNumTargets() != 1)
309            return false;
310        const Target *tgt = &targets.front();
311        return tgt->source == Target::FromCPU && !tgt->pkt->needsResponse();
312    }
313
314    bool promoteDeferredTargets();
315
316    void promoteWritable();
317
318    bool checkFunctional(PacketPtr pkt);
319
320    /**
321     * Prints the contents of this MSHR for debugging.
322     */
323    void print(std::ostream &os,
324               int verbosity = 0,
325               const std::string &prefix = "") const;
326    /**
327     * A no-args wrapper of print(std::ostream...)  meant to be
328     * invoked from DPRINTFs avoiding string overheads in fast mode
329     *
330     * @return string with mshr fields + [deferred]targets
331     */
332    std::string print() const;
333};
334
335#endif // __MEM_CACHE_MSHR_HH__
336