mshr.hh revision 5875
16184SN/A/* 210330Smitch.hayenga@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 38842Smrinmoy.ghosh@arm.com * All rights reserved. 48842Smrinmoy.ghosh@arm.com * 58842Smrinmoy.ghosh@arm.com * Redistribution and use in source and binary forms, with or without 68842Smrinmoy.ghosh@arm.com * modification, are permitted provided that the following conditions are 78842Smrinmoy.ghosh@arm.com * met: redistributions of source code must retain the above copyright 88842Smrinmoy.ghosh@arm.com * notice, this list of conditions and the following disclaimer; 98842Smrinmoy.ghosh@arm.com * redistributions in binary form must reproduce the above copyright 108842Smrinmoy.ghosh@arm.com * notice, this list of conditions and the following disclaimer in the 118842Smrinmoy.ghosh@arm.com * documentation and/or other materials provided with the distribution; 128842Smrinmoy.ghosh@arm.com * neither the name of the copyright holders nor the names of its 138842Smrinmoy.ghosh@arm.com * contributors may be used to endorse or promote products derived from 146184SN/A * this software without specific prior written permission. 156184SN/A * 166184SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176184SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186184SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196184SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206184SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216184SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226184SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236184SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246184SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256184SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266184SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276184SN/A * 286184SN/A * Authors: Erik Hallnor 296184SN/A */ 306184SN/A 316184SN/A/** 326184SN/A * @file 336184SN/A * Miss Status and Handling Register (MSHR) declaration. 346184SN/A */ 356184SN/A 366184SN/A#ifndef __MSHR_HH__ 376184SN/A#define __MSHR_HH__ 386184SN/A 396184SN/A#include <list> 406184SN/A 416184SN/A#include "base/printable.hh" 426184SN/A#include "mem/packet.hh" 4311793Sbrandon.potter@amd.com 4411793Sbrandon.potter@amd.comclass CacheBlk; 459360SE.Tomusk@sms.ed.ac.ukclass MSHRQueue; 466184SN/A 476184SN/A/** 4810785Sgope@wisc.edu * Miss Status and handling Register. This class keeps all the information 499480Snilay@cs.wisc.edu * needed to handle a cache miss including a list of target requests. 509691Satgutier@umich.edu */ 519480Snilay@cs.wisc.educlass MSHR : public Packet::SenderState, public Printable 529480Snilay@cs.wisc.edu{ 539691Satgutier@umich.edu 549480Snilay@cs.wisc.edu public: 559480Snilay@cs.wisc.edu 5611434Smitch.hayenga@arm.com class Target { 579691Satgutier@umich.edu public: 589691Satgutier@umich.edu 599691Satgutier@umich.edu enum Source { 609691Satgutier@umich.edu FromCPU, 619691Satgutier@umich.edu FromSnoop, 629480Snilay@cs.wisc.edu FromPrefetcher 6310785Sgope@wisc.edu }; 646184SN/A 659691Satgutier@umich.edu Tick recvTime; //!< Time when request was received (for stats) 669691Satgutier@umich.edu Tick readyTime; //!< Time when request is ready to be serviced 679691Satgutier@umich.edu Counter order; //!< Global order (for memory consistency mgmt) 689691Satgutier@umich.edu PacketPtr pkt; //!< Pending request packet. 699691Satgutier@umich.edu Source source; //!< Did request come from cpu, memory, or prefetcher? 709691Satgutier@umich.edu bool markedPending; //!< Did we mark upstream MSHR 719691Satgutier@umich.edu //!< as downstreamPending? 726184SN/A 739360SE.Tomusk@sms.ed.ac.uk Target(PacketPtr _pkt, Tick _readyTime, Counter _order, 746184SN/A Source _source, bool _markedPending) 756184SN/A : recvTime(curTick), readyTime(_readyTime), order(_order), 766184SN/A pkt(_pkt), source(_source), markedPending(_markedPending) 776184SN/A {} 786184SN/A }; 799360SE.Tomusk@sms.ed.ac.uk 806184SN/A class TargetList : public std::list<Target> { 816184SN/A /** Target list iterator. */ 826184SN/A typedef std::list<Target>::iterator Iterator; 836184SN/A typedef std::list<Target>::const_iterator ConstIterator; 846184SN/A 856184SN/A public: 866184SN/A bool needsExclusive; 876184SN/A bool hasUpgrade; 886184SN/A 896184SN/A TargetList(); 906184SN/A void resetFlags() { needsExclusive = hasUpgrade = false; } 916184SN/A bool isReset() { return !needsExclusive && !hasUpgrade; } 926184SN/A void add(PacketPtr pkt, Tick readyTime, Counter order, 936184SN/A Target::Source source, bool markPending); 946184SN/A void replaceUpgrades(); 956184SN/A void clearDownstreamPending(); 966184SN/A bool checkFunctional(PacketPtr pkt); 979360SE.Tomusk@sms.ed.ac.uk void print(std::ostream &os, int verbosity, 989360SE.Tomusk@sms.ed.ac.uk const std::string &prefix) const; 999360SE.Tomusk@sms.ed.ac.uk }; 1006184SN/A 1016184SN/A /** A list of MSHRs. */ 1026184SN/A typedef std::list<MSHR *> List; 1036184SN/A /** MSHR list iterator. */ 1046184SN/A typedef List::iterator Iterator; 1059360SE.Tomusk@sms.ed.ac.uk /** MSHR list const_iterator. */ 1069360SE.Tomusk@sms.ed.ac.uk typedef List::const_iterator ConstIterator; 1079360SE.Tomusk@sms.ed.ac.uk 1089360SE.Tomusk@sms.ed.ac.uk /** Pointer to queue containing this MSHR. */ 1096184SN/A MSHRQueue *queue; 1106184SN/A 1116184SN/A /** Cycle when ready to issue */ 1126184SN/A Tick readyTime; 1136184SN/A 1146184SN/A /** Order number assigned by the miss queue. */ 1159360SE.Tomusk@sms.ed.ac.uk Counter order; 1169360SE.Tomusk@sms.ed.ac.uk 1179360SE.Tomusk@sms.ed.ac.uk /** Address of the request. */ 1189360SE.Tomusk@sms.ed.ac.uk Addr addr; 1199360SE.Tomusk@sms.ed.ac.uk 1209360SE.Tomusk@sms.ed.ac.uk /** Size of the request. */ 1219360SE.Tomusk@sms.ed.ac.uk int size; 1229360SE.Tomusk@sms.ed.ac.uk 1239360SE.Tomusk@sms.ed.ac.uk /** True if the request has been sent to the bus. */ 1249360SE.Tomusk@sms.ed.ac.uk bool inService; 1259360SE.Tomusk@sms.ed.ac.uk 1269360SE.Tomusk@sms.ed.ac.uk /** True if the request is just a simple forward from an upper level */ 1279360SE.Tomusk@sms.ed.ac.uk bool isForward; 1289360SE.Tomusk@sms.ed.ac.uk 1299360SE.Tomusk@sms.ed.ac.uk /** True if we need to get an exclusive copy of the block. */ 1309360SE.Tomusk@sms.ed.ac.uk bool needsExclusive() const { return targets->needsExclusive; } 1319360SE.Tomusk@sms.ed.ac.uk 1329360SE.Tomusk@sms.ed.ac.uk /** True if the request is uncacheable */ 1339360SE.Tomusk@sms.ed.ac.uk bool _isUncacheable; 1349360SE.Tomusk@sms.ed.ac.uk 1359360SE.Tomusk@sms.ed.ac.uk bool downstreamPending; 1366184SN/A 1376184SN/A bool pendingInvalidate; 1386184SN/A bool pendingShared; 1396184SN/A 1406184SN/A /** Thread number of the miss. */ 1416184SN/A short threadNum; 1426184SN/A /** The number of currently allocated targets. */ 1436184SN/A short ntargets; 1446184SN/A 1456184SN/A 1466184SN/A /** Data buffer (if needed). Currently used only for pending 1476184SN/A * upgrade handling. */ 14811434Smitch.hayenga@arm.com uint8_t *data; 1496184SN/A 15011434Smitch.hayenga@arm.com /** 15111434Smitch.hayenga@arm.com * Pointer to this MSHR on the ready list. 1526184SN/A * @sa MissQueue, MSHRQueue::readyList 1536184SN/A */ 1546184SN/A Iterator readyIter; 1556184SN/A 15611434Smitch.hayenga@arm.com /** 1576184SN/A * Pointer to this MSHR on the allocated list. 15811434Smitch.hayenga@arm.com * @sa MissQueue, MSHRQueue::allocatedList 15911434Smitch.hayenga@arm.com */ 1606184SN/A Iterator allocIter; 1616184SN/A 1626184SN/Aprivate: 1636184SN/A /** List of all requests that match the address */ 1646184SN/A TargetList *targets; 1656184SN/A 1666184SN/A TargetList *deferredTargets; 1676184SN/A 1686184SN/Apublic: 1696184SN/A 1706184SN/A bool isUncacheable() { return _isUncacheable; } 1716184SN/A 1726184SN/A /** 1736184SN/A * Allocate a miss to this MSHR. 1746184SN/A * @param cmd The requesting command. 1756184SN/A * @param addr The address of the miss. 1766184SN/A * @param asid The address space id of the miss. 1776184SN/A * @param size The number of bytes to request. 1788842Smrinmoy.ghosh@arm.com * @param pkt The original miss. 1798842Smrinmoy.ghosh@arm.com */ 18011434Smitch.hayenga@arm.com void allocate(Addr addr, int size, PacketPtr pkt, 1818842Smrinmoy.ghosh@arm.com Tick when, Counter _order); 1828842Smrinmoy.ghosh@arm.com 1839360SE.Tomusk@sms.ed.ac.uk bool markInService(); 18411434Smitch.hayenga@arm.com 1858842Smrinmoy.ghosh@arm.com void clearDownstreamPending(); 1868842Smrinmoy.ghosh@arm.com 1879327Smrinmoy.ghosh@arm.com /** 1888842Smrinmoy.ghosh@arm.com * Mark this MSHR as free. 1898842Smrinmoy.ghosh@arm.com */ 1906184SN/A void deallocate(); 19111434Smitch.hayenga@arm.com 1926184SN/A /** 1936184SN/A * Add a request to the list of targets. 1946184SN/A * @param target The target. 1956184SN/A */ 1966184SN/A void allocateTarget(PacketPtr target, Tick when, Counter order); 1976184SN/A bool handleSnoop(PacketPtr target, Counter order); 1986184SN/A 1996184SN/A /** A simple constructor. */ 2006184SN/A MSHR(); 2016184SN/A /** A simple destructor. */ 2026184SN/A ~MSHR(); 2036184SN/A 2049360SE.Tomusk@sms.ed.ac.uk /** 2056184SN/A * Returns the current number of allocated targets. 2066184SN/A * @return The current number of allocated targets. 20711434Smitch.hayenga@arm.com */ 20811434Smitch.hayenga@arm.com int getNumTargets() const { return ntargets; } 2096184SN/A 2106184SN/A /** 21111434Smitch.hayenga@arm.com * Returns a pointer to the target list. 21211434Smitch.hayenga@arm.com * @return a pointer to the target list. 2136184SN/A */ 2146184SN/A TargetList *getTargetList() { return targets; } 2156184SN/A 21611434Smitch.hayenga@arm.com /** 2176184SN/A * Returns true if there are targets left. 2186184SN/A * @return true if there are targets 2196184SN/A */ 22011098Slukefahr@umich.edu bool hasTargets() const { return !targets->empty(); } 2218842Smrinmoy.ghosh@arm.com 2226184SN/A /** 2236184SN/A * Returns a reference to the first target. 2249360SE.Tomusk@sms.ed.ac.uk * @return A pointer to the first target. 2256184SN/A */ 22611782Sarthur.perais@inria.fr Target *getTarget() const 22711782Sarthur.perais@inria.fr { 2286184SN/A assert(hasTargets()); 2296184SN/A return &targets->front(); 23011434Smitch.hayenga@arm.com } 2318842Smrinmoy.ghosh@arm.com 2326184SN/A /** 2336184SN/A * Pop first target. 23411434Smitch.hayenga@arm.com */ 2358842Smrinmoy.ghosh@arm.com void popTarget() 2366184SN/A { 2376184SN/A --ntargets; 2386184SN/A targets->pop_front(); 2396184SN/A } 24011434Smitch.hayenga@arm.com 2418842Smrinmoy.ghosh@arm.com bool isForwardNoResponse() const 2426184SN/A { 2436184SN/A if (getNumTargets() != 1) 24411434Smitch.hayenga@arm.com return false; 2458842Smrinmoy.ghosh@arm.com Target *tgt = getTarget(); 2466184SN/A return tgt->source == Target::FromCPU && !tgt->pkt->needsResponse(); 2476184SN/A } 2486184SN/A 2496184SN/A bool promoteDeferredTargets(); 2506184SN/A 2516184SN/A void handleFill(Packet *pkt, CacheBlk *blk); 25211434Smitch.hayenga@arm.com 2536184SN/A bool checkFunctional(PacketPtr pkt); 2546184SN/A 2556184SN/A /** 25611434Smitch.hayenga@arm.com * Prints the contents of this MSHR for debugging. 2576184SN/A */ 2586184SN/A void print(std::ostream &os, 2598487SAli.Saidi@ARM.com int verbosity = 0, 26011098Slukefahr@umich.edu const std::string &prefix = "") const; 2618842Smrinmoy.ghosh@arm.com}; 2626184SN/A 2636184SN/A#endif //__MSHR_HH__ 26411434Smitch.hayenga@arm.com