mshr.hh revision 4908 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 */
30
31/**
32 * @file
33 * Miss Status and Handling Register (MSHR) declaration.
34 */
35
36#ifndef __MSHR_HH__
37#define __MSHR_HH__
38
39#include <list>
40
41#include "mem/packet.hh"
42
43class CacheBlk;
44class MSHRQueue;
45
46/**
47 * Miss Status and handling Register. This class keeps all the information
48 * needed to handle a cache miss including a list of target requests.
49 */
50class MSHR : public Packet::SenderState
51{
52
53  public:
54
55    class Target {
56      public:
57        Tick recvTime;  //!< Time when request was received (for stats)
58        Tick readyTime; //!< Time when request is ready to be serviced
59        Counter order;  //!< Global order (for memory consistency mgmt)
60        PacketPtr pkt;  //!< Pending request packet.
61        bool cpuSide;   //!< Did request come from cpu side or mem side?
62
63        bool isCpuSide() { return cpuSide; }
64
65        Target(PacketPtr _pkt, Tick _readyTime, Counter _order, bool _cpuSide)
66            : recvTime(curTick), readyTime(_readyTime), order(_order),
67              pkt(_pkt), cpuSide(_cpuSide)
68        {}
69    };
70
71    class TargetList : public std::list<Target> {
72        /** Target list iterator. */
73        typedef std::list<Target>::iterator Iterator;
74
75      public:
76        bool needsExclusive;
77        bool hasUpgrade;
78
79        TargetList();
80        void resetFlags() { needsExclusive = hasUpgrade = false; }
81        bool isReset()    { return !needsExclusive && !hasUpgrade; }
82        void add(PacketPtr pkt, Tick readyTime, Counter order, bool cpuSide);
83        void replaceUpgrades();
84        void clearDownstreamPending();
85    };
86
87    /** A list of MSHRs. */
88    typedef std::list<MSHR *> List;
89    /** MSHR list iterator. */
90    typedef List::iterator Iterator;
91    /** MSHR list const_iterator. */
92    typedef List::const_iterator ConstIterator;
93
94    /** Pointer to queue containing this MSHR. */
95    MSHRQueue *queue;
96
97    /** Cycle when ready to issue */
98    Tick readyTime;
99
100    /** Order number assigned by the miss queue. */
101    Counter order;
102
103    /** Address of the request. */
104    Addr addr;
105
106    /** Size of the request. */
107    int size;
108
109    /** True if the request has been sent to the bus. */
110    bool inService;
111
112    /** True if we will be putting the returned block in the cache */
113    bool isCacheFill;
114
115    /** True if we need to get an exclusive copy of the block. */
116    bool needsExclusive() { return targets->needsExclusive; }
117
118    /** True if the request is uncacheable */
119    bool _isUncacheable;
120
121    bool downstreamPending;
122
123    bool pendingInvalidate;
124    bool pendingShared;
125
126    /** Thread number of the miss. */
127    short threadNum;
128    /** The number of currently allocated targets. */
129    short ntargets;
130
131
132    /** Data buffer (if needed).  Currently used only for pending
133     * upgrade handling. */
134    uint8_t *data;
135
136    /**
137     * Pointer to this MSHR on the ready list.
138     * @sa MissQueue, MSHRQueue::readyList
139     */
140    Iterator readyIter;
141
142    /**
143     * Pointer to this MSHR on the allocated list.
144     * @sa MissQueue, MSHRQueue::allocatedList
145     */
146    Iterator allocIter;
147
148private:
149    /** List of all requests that match the address */
150    TargetList *targets;
151
152    TargetList *deferredTargets;
153
154public:
155
156    bool isUncacheable() { return _isUncacheable; }
157
158    /**
159     * Allocate a miss to this MSHR.
160     * @param cmd The requesting command.
161     * @param addr The address of the miss.
162     * @param asid The address space id of the miss.
163     * @param size The number of bytes to request.
164     * @param pkt  The original miss.
165     */
166    void allocate(Addr addr, int size, PacketPtr pkt,
167                  Tick when, Counter _order);
168
169    bool markInService();
170
171    /**
172     * Mark this MSHR as free.
173     */
174    void deallocate();
175
176    /**
177     * Add a request to the list of targets.
178     * @param target The target.
179     */
180    void allocateTarget(PacketPtr target, Tick when, Counter order);
181    bool handleSnoop(PacketPtr target, Counter order);
182
183    /** A simple constructor. */
184    MSHR();
185    /** A simple destructor. */
186    ~MSHR();
187
188    /**
189     * Returns the current number of allocated targets.
190     * @return The current number of allocated targets.
191     */
192    int getNumTargets() { return ntargets; }
193
194    /**
195     * Returns a pointer to the target list.
196     * @return a pointer to the target list.
197     */
198    TargetList *getTargetList() { return targets; }
199
200    /**
201     * Returns true if there are targets left.
202     * @return true if there are targets
203     */
204    bool hasTargets() { return !targets->empty(); }
205
206    /**
207     * Returns a reference to the first target.
208     * @return A pointer to the first target.
209     */
210    Target *getTarget() { assert(hasTargets());  return &targets->front(); }
211
212    /**
213     * Pop first target.
214     */
215    void popTarget()
216    {
217        --ntargets;
218        targets->pop_front();
219    }
220
221    bool isSimpleForward()
222    {
223        if (getNumTargets() != 1)
224            return false;
225        Target *tgt = getTarget();
226        return tgt->isCpuSide() && !tgt->pkt->needsResponse();
227    }
228
229    bool promoteDeferredTargets();
230
231    void handleFill(Packet *pkt, CacheBlk *blk);
232
233    /**
234     * Prints the contents of this MSHR to stderr.
235     */
236    void dump();
237};
238
239#endif //__MSHR_HH__
240