mshr.hh revision 4666 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 */
30
31/**
32 * @file
33 * Miss Status and Handling Register (MSHR) declaration.
34 */
35
36#ifndef __MSHR_HH__
37#define __MSHR_HH__
38
39#include <list>
40
41#include "mem/packet.hh"
42
43class CacheBlk;
44class MSHRQueue;
45
46/**
47 * Miss Status and handling Register. This class keeps all the information
48 * needed to handle a cache miss including a list of target requests.
49 */
50class MSHR : public Packet::SenderState
51{
52
53  public:
54
55    class Target {
56      public:
57        Tick time;      //!< Time when request was received (for stats)
58        Counter order;  //!< Global order (for memory consistency mgmt)
59        PacketPtr pkt;  //!< Pending request packet.
60        bool cpuSide;   //!< Did request come from cpu side or mem side?
61
62        bool isCpuSide() { return cpuSide; }
63
64        Target(PacketPtr _pkt, Tick _time, Counter _order, bool _cpuSide)
65            : time(_time), order(_order), pkt(_pkt), cpuSide(_cpuSide)
66        {}
67    };
68
69    /** Defines the Data structure of the MSHR targetlist. */
70    typedef std::list<Target> TargetList;
71    /** Target list iterator. */
72    typedef std::list<Target>::iterator TargetListIterator;
73    /** A list of MSHRs. */
74    typedef std::list<MSHR *> List;
75    /** MSHR list iterator. */
76    typedef List::iterator Iterator;
77    /** MSHR list const_iterator. */
78    typedef List::const_iterator ConstIterator;
79
80    /** Pointer to queue containing this MSHR. */
81    MSHRQueue *queue;
82
83    /** Cycle when ready to issue */
84    Tick readyTick;
85
86    /** Order number assigned by the miss queue. */
87    Counter order;
88
89    /** Address of the request. */
90    Addr addr;
91
92    /** Size of the request. */
93    int size;
94
95    /** True if the request has been sent to the bus. */
96    bool inService;
97
98    /** True if we will be putting the returned block in the cache */
99    bool isCacheFill;
100    /** True if we need to get an exclusive copy of the block. */
101    bool needsExclusive;
102
103    /** True if the request is uncacheable */
104    bool _isUncacheable;
105
106    bool deferredNeedsExclusive;
107    bool pendingInvalidate;
108
109    /** Thread number of the miss. */
110    short threadNum;
111    /** The number of currently allocated targets. */
112    short ntargets;
113
114    /**
115     * Pointer to this MSHR on the ready list.
116     * @sa MissQueue, MSHRQueue::readyList
117     */
118    Iterator readyIter;
119
120    /**
121     * Pointer to this MSHR on the allocated list.
122     * @sa MissQueue, MSHRQueue::allocatedList
123     */
124    Iterator allocIter;
125
126private:
127    /** List of all requests that match the address */
128    TargetList targets;
129
130    TargetList deferredTargets;
131
132public:
133
134    bool isUncacheable() { return _isUncacheable; }
135
136    /**
137     * Allocate a miss to this MSHR.
138     * @param cmd The requesting command.
139     * @param addr The address of the miss.
140     * @param asid The address space id of the miss.
141     * @param size The number of bytes to request.
142     * @param pkt  The original miss.
143     */
144    void allocate(Addr addr, int size, PacketPtr pkt,
145                  Tick when, Counter _order);
146
147    /**
148     * Mark this MSHR as free.
149     */
150    void deallocate();
151
152    /**
153     * Add a request to the list of targets.
154     * @param target The target.
155     */
156    void allocateTarget(PacketPtr target, Tick when, Counter order);
157    void allocateSnoopTarget(PacketPtr target, Tick when, Counter order);
158
159    /** A simple constructor. */
160    MSHR();
161    /** A simple destructor. */
162    ~MSHR();
163
164    /**
165     * Returns the current number of allocated targets.
166     * @return The current number of allocated targets.
167     */
168    int getNumTargets() { return ntargets; }
169
170    /**
171     * Returns a pointer to the target list.
172     * @return a pointer to the target list.
173     */
174    TargetList* getTargetList() { return &targets; }
175
176    /**
177     * Returns a reference to the first target.
178     * @return A pointer to the first target.
179     */
180    Target *getTarget() { return &targets.front(); }
181
182    /**
183     * Pop first target.
184     */
185    void popTarget()
186    {
187        --ntargets;
188        targets.pop_front();
189    }
190
191    /**
192     * Returns true if there are targets left.
193     * @return true if there are targets
194     */
195    bool hasTargets() { return !targets.empty(); }
196
197    bool isSimpleForward()
198    {
199        if (getNumTargets() != 1)
200            return false;
201        Target *tgt = getTarget();
202        return tgt->isCpuSide() && !tgt->pkt->needsResponse();
203    }
204
205    bool promoteDeferredTargets();
206
207    /**
208     * Prints the contents of this MSHR to stderr.
209     */
210    void dump();
211};
212
213#endif //__MSHR_HH__
214