cache.hh revision 8914
12810Srdreslin@umich.edu/* 28702Sandreas.hansson@arm.com * Copyright (c) 2012 ARM Limited 38702Sandreas.hansson@arm.com * All rights reserved. 48702Sandreas.hansson@arm.com * 58702Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68702Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78702Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88702Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98702Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108702Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118702Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128702Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138702Sandreas.hansson@arm.com * 142810Srdreslin@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 152810Srdreslin@umich.edu * All rights reserved. 162810Srdreslin@umich.edu * 172810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 182810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 192810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 202810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 212810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 222810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 232810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 242810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 252810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 262810Srdreslin@umich.edu * this software without specific prior written permission. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810Srdreslin@umich.edu * 402810Srdreslin@umich.edu * Authors: Erik Hallnor 412810Srdreslin@umich.edu * Dave Greene 422810Srdreslin@umich.edu * Steve Reinhardt 434458Sstever@eecs.umich.edu * Ron Dreslinski 448856Sandreas.hansson@arm.com * Andreas Hansson 452810Srdreslin@umich.edu */ 462810Srdreslin@umich.edu 472810Srdreslin@umich.edu/** 482810Srdreslin@umich.edu * @file 492810Srdreslin@umich.edu * Describes a cache based on template policies. 502810Srdreslin@umich.edu */ 512810Srdreslin@umich.edu 522810Srdreslin@umich.edu#ifndef __CACHE_HH__ 532810Srdreslin@umich.edu#define __CACHE_HH__ 542810Srdreslin@umich.edu 552810Srdreslin@umich.edu#include "base/misc.hh" // fatal, panic, and warn 565338Sstever@gmail.com#include "mem/cache/base.hh" 575338Sstever@gmail.com#include "mem/cache/blk.hh" 585338Sstever@gmail.com#include "mem/cache/mshr.hh" 594458Sstever@eecs.umich.edu#include "sim/eventq.hh" 604458Sstever@eecs.umich.edu 612813Srdreslin@umich.edu//Forward decleration 623861Sstever@eecs.umich.educlass BasePrefetcher; 632810Srdreslin@umich.edu 642810Srdreslin@umich.edu/** 652810Srdreslin@umich.edu * A template-policy based cache. The behavior of the cache can be altered by 662810Srdreslin@umich.edu * supplying different template policies. TagStore handles all tag and data 674672Sstever@eecs.umich.edu * storage @sa TagStore. 682810Srdreslin@umich.edu */ 694672Sstever@eecs.umich.edutemplate <class TagStore> 702810Srdreslin@umich.educlass Cache : public BaseCache 712810Srdreslin@umich.edu{ 722810Srdreslin@umich.edu public: 732810Srdreslin@umich.edu /** Define the type of cache block to use. */ 742810Srdreslin@umich.edu typedef typename TagStore::BlkType BlkType; 753860Sstever@eecs.umich.edu /** A typedef for a list of BlkType pointers. */ 763860Sstever@eecs.umich.edu typedef typename TagStore::BlkList BlkList; 772810Srdreslin@umich.edu 782810Srdreslin@umich.edu protected: 792810Srdreslin@umich.edu 808856Sandreas.hansson@arm.com /** 818856Sandreas.hansson@arm.com * The CPU-side port extends the base cache slave port with access 828856Sandreas.hansson@arm.com * functions for functional, atomic and timing requests. 838856Sandreas.hansson@arm.com */ 848856Sandreas.hansson@arm.com class CpuSidePort : public CacheSlavePort 853738Sstever@eecs.umich.edu { 868856Sandreas.hansson@arm.com private: 873738Sstever@eecs.umich.edu 888856Sandreas.hansson@arm.com // a pointer to our specific cache implementation 898856Sandreas.hansson@arm.com Cache<TagStore> *cache; 903738Sstever@eecs.umich.edu 918856Sandreas.hansson@arm.com protected: 924478Sstever@eecs.umich.edu 933738Sstever@eecs.umich.edu virtual bool recvTiming(PacketPtr pkt); 943738Sstever@eecs.umich.edu 953738Sstever@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 963738Sstever@eecs.umich.edu 973738Sstever@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 988856Sandreas.hansson@arm.com 998856Sandreas.hansson@arm.com virtual unsigned deviceBlockSize() const 1008856Sandreas.hansson@arm.com { return cache->getBlockSize(); } 1018856Sandreas.hansson@arm.com 1028856Sandreas.hansson@arm.com virtual AddrRangeList getAddrRanges(); 1038856Sandreas.hansson@arm.com 1048856Sandreas.hansson@arm.com public: 1058856Sandreas.hansson@arm.com 1068856Sandreas.hansson@arm.com CpuSidePort(const std::string &_name, Cache<TagStore> *_cache, 1078856Sandreas.hansson@arm.com const std::string &_label); 1088856Sandreas.hansson@arm.com 1093738Sstever@eecs.umich.edu }; 1103738Sstever@eecs.umich.edu 1118856Sandreas.hansson@arm.com /** 1128914Sandreas.hansson@arm.com * Override the default behaviour of sendDeferredPacket to enable 1138914Sandreas.hansson@arm.com * the memory-side cache port to also send requests based on the 1148914Sandreas.hansson@arm.com * current MSHR status. This queue has a pointer to our specific 1158914Sandreas.hansson@arm.com * cache implementation and is used by the MemSidePort. 1168914Sandreas.hansson@arm.com */ 1178914Sandreas.hansson@arm.com class MemSidePacketQueue : public PacketQueue 1188914Sandreas.hansson@arm.com { 1198914Sandreas.hansson@arm.com 1208914Sandreas.hansson@arm.com protected: 1218914Sandreas.hansson@arm.com 1228914Sandreas.hansson@arm.com Cache<TagStore> &cache; 1238914Sandreas.hansson@arm.com 1248914Sandreas.hansson@arm.com public: 1258914Sandreas.hansson@arm.com 1268914Sandreas.hansson@arm.com MemSidePacketQueue(Cache<TagStore> &cache, Port &port, 1278914Sandreas.hansson@arm.com const std::string &label) : 1288914Sandreas.hansson@arm.com PacketQueue(cache, port, label), cache(cache) { } 1298914Sandreas.hansson@arm.com 1308914Sandreas.hansson@arm.com /** 1318914Sandreas.hansson@arm.com * Override the normal sendDeferredPacket and do not only 1328914Sandreas.hansson@arm.com * consider the transmit list (used for responses), but also 1338914Sandreas.hansson@arm.com * requests. 1348914Sandreas.hansson@arm.com */ 1358914Sandreas.hansson@arm.com virtual void sendDeferredPacket(); 1368914Sandreas.hansson@arm.com 1378914Sandreas.hansson@arm.com }; 1388914Sandreas.hansson@arm.com 1398914Sandreas.hansson@arm.com /** 1408856Sandreas.hansson@arm.com * The memory-side port extends the base cache master port with 1418856Sandreas.hansson@arm.com * access functions for functional, atomic and timing snoops. 1428856Sandreas.hansson@arm.com */ 1438856Sandreas.hansson@arm.com class MemSidePort : public CacheMasterPort 1443738Sstever@eecs.umich.edu { 1458856Sandreas.hansson@arm.com private: 1463738Sstever@eecs.umich.edu 1478914Sandreas.hansson@arm.com /** The cache-specific queue. */ 1488914Sandreas.hansson@arm.com MemSidePacketQueue _queue; 1498914Sandreas.hansson@arm.com 1508856Sandreas.hansson@arm.com // a pointer to our specific cache implementation 1518856Sandreas.hansson@arm.com Cache<TagStore> *cache; 1523738Sstever@eecs.umich.edu 1538856Sandreas.hansson@arm.com protected: 1544478Sstever@eecs.umich.edu 1553738Sstever@eecs.umich.edu virtual bool recvTiming(PacketPtr pkt); 1563738Sstever@eecs.umich.edu 1573738Sstever@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 1583738Sstever@eecs.umich.edu 1593738Sstever@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 1604458Sstever@eecs.umich.edu 1618856Sandreas.hansson@arm.com virtual unsigned deviceBlockSize() const 1628856Sandreas.hansson@arm.com { return cache->getBlockSize(); } 1638856Sandreas.hansson@arm.com 1648856Sandreas.hansson@arm.com public: 1658856Sandreas.hansson@arm.com 1668856Sandreas.hansson@arm.com MemSidePort(const std::string &_name, Cache<TagStore> *_cache, 1678856Sandreas.hansson@arm.com const std::string &_label); 1683738Sstever@eecs.umich.edu }; 1693738Sstever@eecs.umich.edu 1702810Srdreslin@umich.edu /** Tag and data Storage */ 1712810Srdreslin@umich.edu TagStore *tags; 1724626Sstever@eecs.umich.edu 1732810Srdreslin@umich.edu /** Prefetcher */ 1743861Sstever@eecs.umich.edu BasePrefetcher *prefetcher; 1752810Srdreslin@umich.edu 1764671Sstever@eecs.umich.edu /** Temporary cache block for occasional transitory use */ 1774671Sstever@eecs.umich.edu BlkType *tempBlock; 1784671Sstever@eecs.umich.edu 1792810Srdreslin@umich.edu /** 1805707Shsul@eecs.umich.edu * This cache should allocate a block on a line-sized write miss. 1813860Sstever@eecs.umich.edu */ 1823860Sstever@eecs.umich.edu const bool doFastWrites; 1833860Sstever@eecs.umich.edu 1845875Ssteve.reinhardt@amd.com /** 1855875Ssteve.reinhardt@amd.com * Notify the prefetcher on every access, not just misses. 1865875Ssteve.reinhardt@amd.com */ 1875875Ssteve.reinhardt@amd.com const bool prefetchOnAccess; 1883860Sstever@eecs.umich.edu 1893860Sstever@eecs.umich.edu /** 1903860Sstever@eecs.umich.edu * Does all the processing necessary to perform the provided request. 1913860Sstever@eecs.umich.edu * @param pkt The memory request to perform. 1923860Sstever@eecs.umich.edu * @param lat The latency of the access. 1933860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 1943860Sstever@eecs.umich.edu * @param update True if the replacement data should be updated. 1955707Shsul@eecs.umich.edu * @return Boolean indicating whether the request was satisfied. 1963860Sstever@eecs.umich.edu */ 1975388Sstever@gmail.com bool access(PacketPtr pkt, BlkType *&blk, 1985388Sstever@gmail.com int &lat, PacketList &writebacks); 1994219Srdreslin@umich.edu 2004219Srdreslin@umich.edu /** 2014219Srdreslin@umich.edu *Handle doing the Compare and Swap function for SPARC. 2024219Srdreslin@umich.edu */ 2034626Sstever@eecs.umich.edu void cmpAndSwap(BlkType *blk, PacketPtr pkt); 2043860Sstever@eecs.umich.edu 2053860Sstever@eecs.umich.edu /** 2065350Sstever@gmail.com * Find a block frame for new block at address addr, assuming that 2075350Sstever@gmail.com * the block is not currently in the cache. Append writebacks if 2085350Sstever@gmail.com * any to provided packet list. Return free block frame. May 2095350Sstever@gmail.com * return NULL if there are no replaceable blocks at the moment. 2105350Sstever@gmail.com */ 2115350Sstever@gmail.com BlkType *allocateBlock(Addr addr, PacketList &writebacks); 2125350Sstever@gmail.com 2135350Sstever@gmail.com /** 2143860Sstever@eecs.umich.edu * Populates a cache block and handles all outstanding requests for the 2153860Sstever@eecs.umich.edu * satisfied fill request. This version takes two memory requests. One 2163860Sstever@eecs.umich.edu * contains the fill data, the other is an optional target to satisfy. 2174626Sstever@eecs.umich.edu * @param pkt The memory request with the fill data. 2183860Sstever@eecs.umich.edu * @param blk The cache block if it already exists. 2193860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 2203860Sstever@eecs.umich.edu * @return Pointer to the new cache block. 2213860Sstever@eecs.umich.edu */ 2224626Sstever@eecs.umich.edu BlkType *handleFill(PacketPtr pkt, BlkType *blk, 2234626Sstever@eecs.umich.edu PacketList &writebacks); 2243860Sstever@eecs.umich.edu 2257667Ssteve.reinhardt@amd.com void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk, 2267667Ssteve.reinhardt@amd.com bool deferred_response = false, 2277667Ssteve.reinhardt@amd.com bool pending_downgrade = false); 2284628Sstever@eecs.umich.edu bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk); 2294626Sstever@eecs.umich.edu 2304670Sstever@eecs.umich.edu void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data, 2315319Sstever@gmail.com bool already_copied, bool pending_inval); 2323860Sstever@eecs.umich.edu 2333860Sstever@eecs.umich.edu /** 2343860Sstever@eecs.umich.edu * Sets the blk to the new state. 2353860Sstever@eecs.umich.edu * @param blk The cache block being snooped. 2363860Sstever@eecs.umich.edu * @param new_state The new coherence state for the block. 2373860Sstever@eecs.umich.edu */ 2384670Sstever@eecs.umich.edu void handleSnoop(PacketPtr ptk, BlkType *blk, 2395319Sstever@gmail.com bool is_timing, bool is_deferred, bool pending_inval); 2403860Sstever@eecs.umich.edu 2413860Sstever@eecs.umich.edu /** 2423860Sstever@eecs.umich.edu * Create a writeback request for the given block. 2433860Sstever@eecs.umich.edu * @param blk The block to writeback. 2443860Sstever@eecs.umich.edu * @return The writeback request for the block. 2453860Sstever@eecs.umich.edu */ 2463860Sstever@eecs.umich.edu PacketPtr writebackBlk(BlkType *blk); 2473860Sstever@eecs.umich.edu 2482810Srdreslin@umich.edu public: 2492810Srdreslin@umich.edu /** Instantiates a basic cache object. */ 2508831Smrinmoy.ghosh@arm.com Cache(const Params *p, TagStore *tags); 2512810Srdreslin@umich.edu 2523738Sstever@eecs.umich.edu virtual Port *getPort(const std::string &if_name, int idx = -1); 2532813Srdreslin@umich.edu 2542810Srdreslin@umich.edu void regStats(); 2552810Srdreslin@umich.edu 2562810Srdreslin@umich.edu /** 2572810Srdreslin@umich.edu * Performs the access specified by the request. 2582982Sstever@eecs.umich.edu * @param pkt The request to perform. 2592810Srdreslin@umich.edu * @return The result of the access. 2602810Srdreslin@umich.edu */ 2614626Sstever@eecs.umich.edu bool timingAccess(PacketPtr pkt); 2622810Srdreslin@umich.edu 2632810Srdreslin@umich.edu /** 2644626Sstever@eecs.umich.edu * Performs the access specified by the request. 2654626Sstever@eecs.umich.edu * @param pkt The request to perform. 2664626Sstever@eecs.umich.edu * @return The result of the access. 2672810Srdreslin@umich.edu */ 2684626Sstever@eecs.umich.edu Tick atomicAccess(PacketPtr pkt); 2692810Srdreslin@umich.edu 2702810Srdreslin@umich.edu /** 2714626Sstever@eecs.umich.edu * Performs the access specified by the request. 2724626Sstever@eecs.umich.edu * @param pkt The request to perform. 2738702Sandreas.hansson@arm.com * @param fromCpuSide from the CPU side port or the memory side port 2742810Srdreslin@umich.edu */ 2758702Sandreas.hansson@arm.com void functionalAccess(PacketPtr pkt, bool fromCpuSide); 2763293Srdreslin@umich.edu 2773293Srdreslin@umich.edu /** 2782810Srdreslin@umich.edu * Handles a response (cache line fill/write ack) from the bus. 2792982Sstever@eecs.umich.edu * @param pkt The request being responded to. 2802810Srdreslin@umich.edu */ 2814626Sstever@eecs.umich.edu void handleResponse(PacketPtr pkt); 2822810Srdreslin@umich.edu 2832810Srdreslin@umich.edu /** 2842810Srdreslin@umich.edu * Snoops bus transactions to maintain coherence. 2852982Sstever@eecs.umich.edu * @param pkt The current bus transaction. 2862810Srdreslin@umich.edu */ 2874626Sstever@eecs.umich.edu void snoopTiming(PacketPtr pkt); 2882810Srdreslin@umich.edu 2894626Sstever@eecs.umich.edu /** 2904626Sstever@eecs.umich.edu * Snoop for the provided request in the cache and return the estimated 2914626Sstever@eecs.umich.edu * time of completion. 2924626Sstever@eecs.umich.edu * @param pkt The memory request to snoop 2934626Sstever@eecs.umich.edu * @return The estimated completion time. 2944626Sstever@eecs.umich.edu */ 2954626Sstever@eecs.umich.edu Tick snoopAtomic(PacketPtr pkt); 2962810Srdreslin@umich.edu 2972810Srdreslin@umich.edu /** 2982982Sstever@eecs.umich.edu * Squash all requests associated with specified thread. 2992810Srdreslin@umich.edu * intended for use by I-cache. 3002982Sstever@eecs.umich.edu * @param threadNum The thread to squash. 3012810Srdreslin@umich.edu */ 3024626Sstever@eecs.umich.edu void squash(int threadNum); 3034626Sstever@eecs.umich.edu 3044626Sstever@eecs.umich.edu /** 3055365Sstever@gmail.com * Generate an appropriate downstream bus request packet for the 3065365Sstever@gmail.com * given parameters. 3075365Sstever@gmail.com * @param cpu_pkt The upstream request that needs to be satisfied. 3085365Sstever@gmail.com * @param blk The block currently in the cache corresponding to 3095365Sstever@gmail.com * cpu_pkt (NULL if none). 3105365Sstever@gmail.com * @param needsExclusive Indicates that an exclusive copy is required 3115365Sstever@gmail.com * even if the request in cpu_pkt doesn't indicate that. 3125365Sstever@gmail.com * @return A new Packet containing the request, or NULL if the 3135365Sstever@gmail.com * current request in cpu_pkt should just be forwarded on. 3144626Sstever@eecs.umich.edu */ 3154628Sstever@eecs.umich.edu PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk, 3164628Sstever@eecs.umich.edu bool needsExclusive); 3175365Sstever@gmail.com 3185365Sstever@gmail.com /** 3195365Sstever@gmail.com * Return the next MSHR to service, either a pending miss from the 3205365Sstever@gmail.com * mshrQueue, a buffered write from the write buffer, or something 3215365Sstever@gmail.com * from the prefetcher. This function is responsible for 3225365Sstever@gmail.com * prioritizing among those sources on the fly. 3235365Sstever@gmail.com */ 3244626Sstever@eecs.umich.edu MSHR *getNextMSHR(); 3255365Sstever@gmail.com 3265365Sstever@gmail.com /** 3275365Sstever@gmail.com * Selects an outstanding request to service. Called when the 3285365Sstever@gmail.com * cache gets granted the downstream bus in timing mode. 3295365Sstever@gmail.com * @return The request to service, NULL if none found. 3305365Sstever@gmail.com */ 3314628Sstever@eecs.umich.edu PacketPtr getTimingPacket(); 3324626Sstever@eecs.umich.edu 3334626Sstever@eecs.umich.edu /** 3344626Sstever@eecs.umich.edu * Marks a request as in service (sent on the bus). This can have side 3354626Sstever@eecs.umich.edu * effect since storage for no response commands is deallocated once they 3364626Sstever@eecs.umich.edu * are successfully sent. 3374626Sstever@eecs.umich.edu * @param pkt The request that was sent on the bus. 3384626Sstever@eecs.umich.edu */ 3397667Ssteve.reinhardt@amd.com void markInService(MSHR *mshr, PacketPtr pkt = 0); 3404626Sstever@eecs.umich.edu 3414626Sstever@eecs.umich.edu /** 3424626Sstever@eecs.umich.edu * Perform the given writeback request. 3434626Sstever@eecs.umich.edu * @param pkt The writeback request. 3444626Sstever@eecs.umich.edu */ 3454626Sstever@eecs.umich.edu void doWriteback(PacketPtr pkt); 3464626Sstever@eecs.umich.edu 3474626Sstever@eecs.umich.edu /** 3484626Sstever@eecs.umich.edu * Return whether there are any outstanding misses. 3494626Sstever@eecs.umich.edu */ 3504626Sstever@eecs.umich.edu bool outstandingMisses() const 3512810Srdreslin@umich.edu { 3524626Sstever@eecs.umich.edu return mshrQueue.allocated != 0; 3532810Srdreslin@umich.edu } 3542810Srdreslin@umich.edu 3554626Sstever@eecs.umich.edu CacheBlk *findBlock(Addr addr) { 3564626Sstever@eecs.umich.edu return tags->findBlock(addr); 3572810Srdreslin@umich.edu } 3582810Srdreslin@umich.edu 3593861Sstever@eecs.umich.edu bool inCache(Addr addr) { 3603861Sstever@eecs.umich.edu return (tags->findBlock(addr) != 0); 3613861Sstever@eecs.umich.edu } 3623861Sstever@eecs.umich.edu 3633861Sstever@eecs.umich.edu bool inMissQueue(Addr addr) { 3644626Sstever@eecs.umich.edu return (mshrQueue.findMatch(addr) != 0); 3653861Sstever@eecs.umich.edu } 3665875Ssteve.reinhardt@amd.com 3675875Ssteve.reinhardt@amd.com /** 3685875Ssteve.reinhardt@amd.com * Find next request ready time from among possible sources. 3695875Ssteve.reinhardt@amd.com */ 3705875Ssteve.reinhardt@amd.com Tick nextMSHRReadyTime(); 3712810Srdreslin@umich.edu}; 3722810Srdreslin@umich.edu 3732810Srdreslin@umich.edu#endif // __CACHE_HH__ 374