cache.hh revision 4672
12810Srdreslin@umich.edu/* 22810Srdreslin@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 32810Srdreslin@umich.edu * All rights reserved. 42810Srdreslin@umich.edu * 52810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 62810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 72810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 82810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 92810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 102810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 112810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 122810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 132810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 142810Srdreslin@umich.edu * this software without specific prior written permission. 152810Srdreslin@umich.edu * 162810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * Authors: Erik Hallnor 292810Srdreslin@umich.edu * Dave Greene 302810Srdreslin@umich.edu * Steve Reinhardt 314458Sstever@eecs.umich.edu * Ron Dreslinski 322810Srdreslin@umich.edu */ 332810Srdreslin@umich.edu 342810Srdreslin@umich.edu/** 352810Srdreslin@umich.edu * @file 362810Srdreslin@umich.edu * Describes a cache based on template policies. 372810Srdreslin@umich.edu */ 382810Srdreslin@umich.edu 392810Srdreslin@umich.edu#ifndef __CACHE_HH__ 402810Srdreslin@umich.edu#define __CACHE_HH__ 412810Srdreslin@umich.edu 422810Srdreslin@umich.edu#include "base/misc.hh" // fatal, panic, and warn 432810Srdreslin@umich.edu 442810Srdreslin@umich.edu#include "mem/cache/base_cache.hh" 453860Sstever@eecs.umich.edu#include "mem/cache/cache_blk.hh" 464626Sstever@eecs.umich.edu#include "mem/cache/miss/mshr.hh" 472810Srdreslin@umich.edu 484458Sstever@eecs.umich.edu#include "sim/eventq.hh" 494458Sstever@eecs.umich.edu 502813Srdreslin@umich.edu//Forward decleration 513861Sstever@eecs.umich.educlass BasePrefetcher; 522810Srdreslin@umich.edu 532810Srdreslin@umich.edu/** 542810Srdreslin@umich.edu * A template-policy based cache. The behavior of the cache can be altered by 552810Srdreslin@umich.edu * supplying different template policies. TagStore handles all tag and data 564672Sstever@eecs.umich.edu * storage @sa TagStore. 572810Srdreslin@umich.edu */ 584672Sstever@eecs.umich.edutemplate <class TagStore> 592810Srdreslin@umich.educlass Cache : public BaseCache 602810Srdreslin@umich.edu{ 612810Srdreslin@umich.edu public: 622810Srdreslin@umich.edu /** Define the type of cache block to use. */ 632810Srdreslin@umich.edu typedef typename TagStore::BlkType BlkType; 643860Sstever@eecs.umich.edu /** A typedef for a list of BlkType pointers. */ 653860Sstever@eecs.umich.edu typedef typename TagStore::BlkList BlkList; 662810Srdreslin@umich.edu 672810Srdreslin@umich.edu bool prefetchAccess; 683738Sstever@eecs.umich.edu 692810Srdreslin@umich.edu protected: 702810Srdreslin@umich.edu 713738Sstever@eecs.umich.edu class CpuSidePort : public CachePort 723738Sstever@eecs.umich.edu { 733738Sstever@eecs.umich.edu public: 743738Sstever@eecs.umich.edu CpuSidePort(const std::string &_name, 754672Sstever@eecs.umich.edu Cache<TagStore> *_cache); 763738Sstever@eecs.umich.edu 773738Sstever@eecs.umich.edu // BaseCache::CachePort just has a BaseCache *; this function 783738Sstever@eecs.umich.edu // lets us get back the type info we lost when we stored the 793738Sstever@eecs.umich.edu // cache pointer there. 804672Sstever@eecs.umich.edu Cache<TagStore> *myCache() { 814672Sstever@eecs.umich.edu return static_cast<Cache<TagStore> *>(cache); 823738Sstever@eecs.umich.edu } 833738Sstever@eecs.umich.edu 844478Sstever@eecs.umich.edu virtual void getDeviceAddressRanges(AddrRangeList &resp, 854478Sstever@eecs.umich.edu bool &snoop); 864478Sstever@eecs.umich.edu 873738Sstever@eecs.umich.edu virtual bool recvTiming(PacketPtr pkt); 883738Sstever@eecs.umich.edu 893738Sstever@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 903738Sstever@eecs.umich.edu 913738Sstever@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 923738Sstever@eecs.umich.edu }; 933738Sstever@eecs.umich.edu 943738Sstever@eecs.umich.edu class MemSidePort : public CachePort 953738Sstever@eecs.umich.edu { 963738Sstever@eecs.umich.edu public: 973738Sstever@eecs.umich.edu MemSidePort(const std::string &_name, 984672Sstever@eecs.umich.edu Cache<TagStore> *_cache); 993738Sstever@eecs.umich.edu 1003738Sstever@eecs.umich.edu // BaseCache::CachePort just has a BaseCache *; this function 1013738Sstever@eecs.umich.edu // lets us get back the type info we lost when we stored the 1023738Sstever@eecs.umich.edu // cache pointer there. 1034672Sstever@eecs.umich.edu Cache<TagStore> *myCache() { 1044672Sstever@eecs.umich.edu return static_cast<Cache<TagStore> *>(cache); 1053738Sstever@eecs.umich.edu } 1063738Sstever@eecs.umich.edu 1074626Sstever@eecs.umich.edu void sendPacket(); 1084626Sstever@eecs.umich.edu 1094626Sstever@eecs.umich.edu void processSendEvent(); 1104458Sstever@eecs.umich.edu 1114478Sstever@eecs.umich.edu virtual void getDeviceAddressRanges(AddrRangeList &resp, 1124478Sstever@eecs.umich.edu bool &snoop); 1134478Sstever@eecs.umich.edu 1143738Sstever@eecs.umich.edu virtual bool recvTiming(PacketPtr pkt); 1153738Sstever@eecs.umich.edu 1164458Sstever@eecs.umich.edu virtual void recvRetry(); 1174458Sstever@eecs.umich.edu 1183738Sstever@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 1193738Sstever@eecs.umich.edu 1203738Sstever@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 1214458Sstever@eecs.umich.edu 1224626Sstever@eecs.umich.edu typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent> 1234626Sstever@eecs.umich.edu SendEvent; 1243738Sstever@eecs.umich.edu }; 1253738Sstever@eecs.umich.edu 1262810Srdreslin@umich.edu /** Tag and data Storage */ 1272810Srdreslin@umich.edu TagStore *tags; 1284626Sstever@eecs.umich.edu 1292810Srdreslin@umich.edu /** Prefetcher */ 1303861Sstever@eecs.umich.edu BasePrefetcher *prefetcher; 1312810Srdreslin@umich.edu 1324671Sstever@eecs.umich.edu /** Temporary cache block for occasional transitory use */ 1334671Sstever@eecs.umich.edu BlkType *tempBlock; 1344671Sstever@eecs.umich.edu 1352810Srdreslin@umich.edu /** 1363860Sstever@eecs.umich.edu * Can this cache should allocate a block on a line-sized write miss. 1373860Sstever@eecs.umich.edu */ 1383860Sstever@eecs.umich.edu const bool doFastWrites; 1393860Sstever@eecs.umich.edu 1403860Sstever@eecs.umich.edu const bool prefetchMiss; 1413860Sstever@eecs.umich.edu 1423860Sstever@eecs.umich.edu /** 1433860Sstever@eecs.umich.edu * Handle a replacement for the given request. 1443860Sstever@eecs.umich.edu * @param blk A pointer to the block, usually NULL 1453860Sstever@eecs.umich.edu * @param pkt The memory request to satisfy. 1463860Sstever@eecs.umich.edu * @param new_state The new state of the block. 1473860Sstever@eecs.umich.edu * @param writebacks A list to store any generated writebacks. 1483860Sstever@eecs.umich.edu */ 1494626Sstever@eecs.umich.edu BlkType* doReplacement(BlkType *blk, PacketPtr pkt, 1503860Sstever@eecs.umich.edu CacheBlk::State new_state, PacketList &writebacks); 1513860Sstever@eecs.umich.edu 1523860Sstever@eecs.umich.edu /** 1533860Sstever@eecs.umich.edu * Does all the processing necessary to perform the provided request. 1543860Sstever@eecs.umich.edu * @param pkt The memory request to perform. 1553860Sstever@eecs.umich.edu * @param lat The latency of the access. 1563860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 1573860Sstever@eecs.umich.edu * @param update True if the replacement data should be updated. 1583860Sstever@eecs.umich.edu * @return Pointer to the cache block touched by the request. NULL if it 1593860Sstever@eecs.umich.edu * was a miss. 1603860Sstever@eecs.umich.edu */ 1614628Sstever@eecs.umich.edu bool access(PacketPtr pkt, BlkType *&blk, int &lat); 1624219Srdreslin@umich.edu 1634219Srdreslin@umich.edu /** 1644219Srdreslin@umich.edu *Handle doing the Compare and Swap function for SPARC. 1654219Srdreslin@umich.edu */ 1664626Sstever@eecs.umich.edu void cmpAndSwap(BlkType *blk, PacketPtr pkt); 1673860Sstever@eecs.umich.edu 1683860Sstever@eecs.umich.edu /** 1693860Sstever@eecs.umich.edu * Populates a cache block and handles all outstanding requests for the 1703860Sstever@eecs.umich.edu * satisfied fill request. This version takes two memory requests. One 1713860Sstever@eecs.umich.edu * contains the fill data, the other is an optional target to satisfy. 1723860Sstever@eecs.umich.edu * Used for Cache::probe. 1734626Sstever@eecs.umich.edu * @param pkt The memory request with the fill data. 1743860Sstever@eecs.umich.edu * @param blk The cache block if it already exists. 1753860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 1763860Sstever@eecs.umich.edu * @return Pointer to the new cache block. 1773860Sstever@eecs.umich.edu */ 1784626Sstever@eecs.umich.edu BlkType *handleFill(PacketPtr pkt, BlkType *blk, 1794626Sstever@eecs.umich.edu PacketList &writebacks); 1803860Sstever@eecs.umich.edu 1814665Sstever@eecs.umich.edu void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk); 1824628Sstever@eecs.umich.edu bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk); 1834626Sstever@eecs.umich.edu 1844670Sstever@eecs.umich.edu void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data, 1854670Sstever@eecs.umich.edu bool already_copied); 1863860Sstever@eecs.umich.edu 1873860Sstever@eecs.umich.edu /** 1883860Sstever@eecs.umich.edu * Sets the blk to the new state. 1893860Sstever@eecs.umich.edu * @param blk The cache block being snooped. 1903860Sstever@eecs.umich.edu * @param new_state The new coherence state for the block. 1913860Sstever@eecs.umich.edu */ 1924670Sstever@eecs.umich.edu void handleSnoop(PacketPtr ptk, BlkType *blk, 1934670Sstever@eecs.umich.edu bool is_timing, bool is_deferred); 1943860Sstever@eecs.umich.edu 1953860Sstever@eecs.umich.edu /** 1963860Sstever@eecs.umich.edu * Create a writeback request for the given block. 1973860Sstever@eecs.umich.edu * @param blk The block to writeback. 1983860Sstever@eecs.umich.edu * @return The writeback request for the block. 1993860Sstever@eecs.umich.edu */ 2003860Sstever@eecs.umich.edu PacketPtr writebackBlk(BlkType *blk); 2013860Sstever@eecs.umich.edu 2022810Srdreslin@umich.edu public: 2032810Srdreslin@umich.edu 2042810Srdreslin@umich.edu class Params 2052810Srdreslin@umich.edu { 2062810Srdreslin@umich.edu public: 2072810Srdreslin@umich.edu TagStore *tags; 2082810Srdreslin@umich.edu BaseCache::Params baseParams; 2093861Sstever@eecs.umich.edu BasePrefetcher*prefetcher; 2102810Srdreslin@umich.edu bool prefetchAccess; 2113860Sstever@eecs.umich.edu const bool doFastWrites; 2123860Sstever@eecs.umich.edu const bool prefetchMiss; 2132810Srdreslin@umich.edu 2144672Sstever@eecs.umich.edu Params(TagStore *_tags, 2153315Sstever@eecs.umich.edu BaseCache::Params params, 2163861Sstever@eecs.umich.edu BasePrefetcher *_prefetcher, 2173860Sstever@eecs.umich.edu bool prefetch_access, int hit_latency, 2183860Sstever@eecs.umich.edu bool do_fast_writes, 2193860Sstever@eecs.umich.edu bool prefetch_miss) 2204672Sstever@eecs.umich.edu : tags(_tags), 2213315Sstever@eecs.umich.edu baseParams(params), 2222813Srdreslin@umich.edu prefetcher(_prefetcher), prefetchAccess(prefetch_access), 2233860Sstever@eecs.umich.edu doFastWrites(do_fast_writes), 2244626Sstever@eecs.umich.edu prefetchMiss(prefetch_miss) 2252810Srdreslin@umich.edu { 2262810Srdreslin@umich.edu } 2272810Srdreslin@umich.edu }; 2282810Srdreslin@umich.edu 2292810Srdreslin@umich.edu /** Instantiates a basic cache object. */ 2302812Srdreslin@umich.edu Cache(const std::string &_name, Params ¶ms); 2312810Srdreslin@umich.edu 2323738Sstever@eecs.umich.edu virtual Port *getPort(const std::string &if_name, int idx = -1); 2334190Ssaidi@eecs.umich.edu virtual void deletePortRefs(Port *p); 2342813Srdreslin@umich.edu 2352810Srdreslin@umich.edu void regStats(); 2362810Srdreslin@umich.edu 2372810Srdreslin@umich.edu /** 2382810Srdreslin@umich.edu * Performs the access specified by the request. 2392982Sstever@eecs.umich.edu * @param pkt The request to perform. 2402810Srdreslin@umich.edu * @return The result of the access. 2412810Srdreslin@umich.edu */ 2424626Sstever@eecs.umich.edu bool timingAccess(PacketPtr pkt); 2432810Srdreslin@umich.edu 2442810Srdreslin@umich.edu /** 2454626Sstever@eecs.umich.edu * Performs the access specified by the request. 2464626Sstever@eecs.umich.edu * @param pkt The request to perform. 2474626Sstever@eecs.umich.edu * @return The result of the access. 2482810Srdreslin@umich.edu */ 2494626Sstever@eecs.umich.edu Tick atomicAccess(PacketPtr pkt); 2502810Srdreslin@umich.edu 2512810Srdreslin@umich.edu /** 2524626Sstever@eecs.umich.edu * Performs the access specified by the request. 2534626Sstever@eecs.umich.edu * @param pkt The request to perform. 2544626Sstever@eecs.umich.edu * @return The result of the access. 2552810Srdreslin@umich.edu */ 2564626Sstever@eecs.umich.edu void functionalAccess(PacketPtr pkt, CachePort *otherSidePort); 2573293Srdreslin@umich.edu 2583293Srdreslin@umich.edu /** 2592810Srdreslin@umich.edu * Handles a response (cache line fill/write ack) from the bus. 2602982Sstever@eecs.umich.edu * @param pkt The request being responded to. 2612810Srdreslin@umich.edu */ 2624626Sstever@eecs.umich.edu void handleResponse(PacketPtr pkt); 2632810Srdreslin@umich.edu 2642810Srdreslin@umich.edu /** 2652810Srdreslin@umich.edu * Snoops bus transactions to maintain coherence. 2662982Sstever@eecs.umich.edu * @param pkt The current bus transaction. 2672810Srdreslin@umich.edu */ 2684626Sstever@eecs.umich.edu void snoopTiming(PacketPtr pkt); 2692810Srdreslin@umich.edu 2704626Sstever@eecs.umich.edu /** 2714626Sstever@eecs.umich.edu * Snoop for the provided request in the cache and return the estimated 2724626Sstever@eecs.umich.edu * time of completion. 2734626Sstever@eecs.umich.edu * @param pkt The memory request to snoop 2744626Sstever@eecs.umich.edu * @return The estimated completion time. 2754626Sstever@eecs.umich.edu */ 2764626Sstever@eecs.umich.edu Tick snoopAtomic(PacketPtr pkt); 2772810Srdreslin@umich.edu 2782810Srdreslin@umich.edu /** 2792982Sstever@eecs.umich.edu * Squash all requests associated with specified thread. 2802810Srdreslin@umich.edu * intended for use by I-cache. 2812982Sstever@eecs.umich.edu * @param threadNum The thread to squash. 2822810Srdreslin@umich.edu */ 2834626Sstever@eecs.umich.edu void squash(int threadNum); 2844626Sstever@eecs.umich.edu 2854626Sstever@eecs.umich.edu /** 2864626Sstever@eecs.umich.edu * Selects a outstanding request to service. 2874626Sstever@eecs.umich.edu * @return The request to service, NULL if none found. 2884626Sstever@eecs.umich.edu */ 2894628Sstever@eecs.umich.edu PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk, 2904628Sstever@eecs.umich.edu bool needsExclusive); 2914626Sstever@eecs.umich.edu MSHR *getNextMSHR(); 2924628Sstever@eecs.umich.edu PacketPtr getTimingPacket(); 2934626Sstever@eecs.umich.edu 2944626Sstever@eecs.umich.edu /** 2954626Sstever@eecs.umich.edu * Marks a request as in service (sent on the bus). This can have side 2964626Sstever@eecs.umich.edu * effect since storage for no response commands is deallocated once they 2974626Sstever@eecs.umich.edu * are successfully sent. 2984626Sstever@eecs.umich.edu * @param pkt The request that was sent on the bus. 2994626Sstever@eecs.umich.edu */ 3004626Sstever@eecs.umich.edu void markInService(MSHR *mshr); 3014626Sstever@eecs.umich.edu 3024626Sstever@eecs.umich.edu /** 3034626Sstever@eecs.umich.edu * Perform the given writeback request. 3044626Sstever@eecs.umich.edu * @param pkt The writeback request. 3054626Sstever@eecs.umich.edu */ 3064626Sstever@eecs.umich.edu void doWriteback(PacketPtr pkt); 3074626Sstever@eecs.umich.edu 3084626Sstever@eecs.umich.edu /** 3094626Sstever@eecs.umich.edu * Return whether there are any outstanding misses. 3104626Sstever@eecs.umich.edu */ 3114626Sstever@eecs.umich.edu bool outstandingMisses() const 3122810Srdreslin@umich.edu { 3134626Sstever@eecs.umich.edu return mshrQueue.allocated != 0; 3142810Srdreslin@umich.edu } 3152810Srdreslin@umich.edu 3164626Sstever@eecs.umich.edu CacheBlk *findBlock(Addr addr) { 3174626Sstever@eecs.umich.edu return tags->findBlock(addr); 3182810Srdreslin@umich.edu } 3192810Srdreslin@umich.edu 3203861Sstever@eecs.umich.edu bool inCache(Addr addr) { 3213861Sstever@eecs.umich.edu return (tags->findBlock(addr) != 0); 3223861Sstever@eecs.umich.edu } 3233861Sstever@eecs.umich.edu 3243861Sstever@eecs.umich.edu bool inMissQueue(Addr addr) { 3254626Sstever@eecs.umich.edu return (mshrQueue.findMatch(addr) != 0); 3263861Sstever@eecs.umich.edu } 3272810Srdreslin@umich.edu}; 3282810Srdreslin@umich.edu 3292810Srdreslin@umich.edu#endif // __CACHE_HH__ 330