cache.hh revision 4665
12810Srdreslin@umich.edu/* 22810Srdreslin@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 32810Srdreslin@umich.edu * All rights reserved. 42810Srdreslin@umich.edu * 52810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 62810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 72810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 82810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 92810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 102810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 112810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 122810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 132810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 142810Srdreslin@umich.edu * this software without specific prior written permission. 152810Srdreslin@umich.edu * 162810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * Authors: Erik Hallnor 292810Srdreslin@umich.edu * Dave Greene 302810Srdreslin@umich.edu * Steve Reinhardt 314458Sstever@eecs.umich.edu * Ron Dreslinski 322810Srdreslin@umich.edu */ 332810Srdreslin@umich.edu 342810Srdreslin@umich.edu/** 352810Srdreslin@umich.edu * @file 362810Srdreslin@umich.edu * Describes a cache based on template policies. 372810Srdreslin@umich.edu */ 382810Srdreslin@umich.edu 392810Srdreslin@umich.edu#ifndef __CACHE_HH__ 402810Srdreslin@umich.edu#define __CACHE_HH__ 412810Srdreslin@umich.edu 423860Sstever@eecs.umich.edu#include "base/compression/base.hh" 432810Srdreslin@umich.edu#include "base/misc.hh" // fatal, panic, and warn 442810Srdreslin@umich.edu#include "cpu/smt.hh" // SMT_MAX_THREADS 452810Srdreslin@umich.edu 462810Srdreslin@umich.edu#include "mem/cache/base_cache.hh" 473860Sstever@eecs.umich.edu#include "mem/cache/cache_blk.hh" 484626Sstever@eecs.umich.edu#include "mem/cache/miss/mshr.hh" 492810Srdreslin@umich.edu 504458Sstever@eecs.umich.edu#include "sim/eventq.hh" 514458Sstever@eecs.umich.edu 522813Srdreslin@umich.edu//Forward decleration 533861Sstever@eecs.umich.educlass BasePrefetcher; 542810Srdreslin@umich.edu 552810Srdreslin@umich.edu/** 562810Srdreslin@umich.edu * A template-policy based cache. The behavior of the cache can be altered by 572810Srdreslin@umich.edu * supplying different template policies. TagStore handles all tag and data 582810Srdreslin@umich.edu * storage @sa TagStore. Buffering handles all misses and writes/writebacks 592810Srdreslin@umich.edu * @sa MissQueue. Coherence handles all coherence policy details @sa 602810Srdreslin@umich.edu * UniCoherence, SimpleMultiCoherence. 612810Srdreslin@umich.edu */ 623719Sstever@eecs.umich.edutemplate <class TagStore, class Coherence> 632810Srdreslin@umich.educlass Cache : public BaseCache 642810Srdreslin@umich.edu{ 652810Srdreslin@umich.edu public: 662810Srdreslin@umich.edu /** Define the type of cache block to use. */ 672810Srdreslin@umich.edu typedef typename TagStore::BlkType BlkType; 683860Sstever@eecs.umich.edu /** A typedef for a list of BlkType pointers. */ 693860Sstever@eecs.umich.edu typedef typename TagStore::BlkList BlkList; 702810Srdreslin@umich.edu 712810Srdreslin@umich.edu bool prefetchAccess; 723738Sstever@eecs.umich.edu 732810Srdreslin@umich.edu protected: 742810Srdreslin@umich.edu 753738Sstever@eecs.umich.edu class CpuSidePort : public CachePort 763738Sstever@eecs.umich.edu { 773738Sstever@eecs.umich.edu public: 783738Sstever@eecs.umich.edu CpuSidePort(const std::string &_name, 793738Sstever@eecs.umich.edu Cache<TagStore,Coherence> *_cache); 803738Sstever@eecs.umich.edu 813738Sstever@eecs.umich.edu // BaseCache::CachePort just has a BaseCache *; this function 823738Sstever@eecs.umich.edu // lets us get back the type info we lost when we stored the 833738Sstever@eecs.umich.edu // cache pointer there. 843738Sstever@eecs.umich.edu Cache<TagStore,Coherence> *myCache() { 853738Sstever@eecs.umich.edu return static_cast<Cache<TagStore,Coherence> *>(cache); 863738Sstever@eecs.umich.edu } 873738Sstever@eecs.umich.edu 884478Sstever@eecs.umich.edu virtual void getDeviceAddressRanges(AddrRangeList &resp, 894478Sstever@eecs.umich.edu bool &snoop); 904478Sstever@eecs.umich.edu 913738Sstever@eecs.umich.edu virtual bool recvTiming(PacketPtr pkt); 923738Sstever@eecs.umich.edu 933738Sstever@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 943738Sstever@eecs.umich.edu 953738Sstever@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 963738Sstever@eecs.umich.edu }; 973738Sstever@eecs.umich.edu 983738Sstever@eecs.umich.edu class MemSidePort : public CachePort 993738Sstever@eecs.umich.edu { 1003738Sstever@eecs.umich.edu public: 1013738Sstever@eecs.umich.edu MemSidePort(const std::string &_name, 1023738Sstever@eecs.umich.edu Cache<TagStore,Coherence> *_cache); 1033738Sstever@eecs.umich.edu 1043738Sstever@eecs.umich.edu // BaseCache::CachePort just has a BaseCache *; this function 1053738Sstever@eecs.umich.edu // lets us get back the type info we lost when we stored the 1063738Sstever@eecs.umich.edu // cache pointer there. 1073738Sstever@eecs.umich.edu Cache<TagStore,Coherence> *myCache() { 1083738Sstever@eecs.umich.edu return static_cast<Cache<TagStore,Coherence> *>(cache); 1093738Sstever@eecs.umich.edu } 1103738Sstever@eecs.umich.edu 1114626Sstever@eecs.umich.edu void sendPacket(); 1124626Sstever@eecs.umich.edu 1134626Sstever@eecs.umich.edu void processSendEvent(); 1144458Sstever@eecs.umich.edu 1154478Sstever@eecs.umich.edu virtual void getDeviceAddressRanges(AddrRangeList &resp, 1164478Sstever@eecs.umich.edu bool &snoop); 1174478Sstever@eecs.umich.edu 1183738Sstever@eecs.umich.edu virtual bool recvTiming(PacketPtr pkt); 1193738Sstever@eecs.umich.edu 1204458Sstever@eecs.umich.edu virtual void recvRetry(); 1214458Sstever@eecs.umich.edu 1223738Sstever@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 1233738Sstever@eecs.umich.edu 1243738Sstever@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 1254458Sstever@eecs.umich.edu 1264626Sstever@eecs.umich.edu typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent> 1274626Sstever@eecs.umich.edu SendEvent; 1283738Sstever@eecs.umich.edu }; 1293738Sstever@eecs.umich.edu 1302810Srdreslin@umich.edu /** Tag and data Storage */ 1312810Srdreslin@umich.edu TagStore *tags; 1324626Sstever@eecs.umich.edu 1332810Srdreslin@umich.edu /** Coherence protocol. */ 1342810Srdreslin@umich.edu Coherence *coherence; 1352810Srdreslin@umich.edu 1362810Srdreslin@umich.edu /** Prefetcher */ 1373861Sstever@eecs.umich.edu BasePrefetcher *prefetcher; 1382810Srdreslin@umich.edu 1392810Srdreslin@umich.edu /** 1403860Sstever@eecs.umich.edu * Can this cache should allocate a block on a line-sized write miss. 1413860Sstever@eecs.umich.edu */ 1423860Sstever@eecs.umich.edu const bool doFastWrites; 1433860Sstever@eecs.umich.edu 1443860Sstever@eecs.umich.edu const bool prefetchMiss; 1453860Sstever@eecs.umich.edu 1463860Sstever@eecs.umich.edu /** 1473860Sstever@eecs.umich.edu * Handle a replacement for the given request. 1483860Sstever@eecs.umich.edu * @param blk A pointer to the block, usually NULL 1493860Sstever@eecs.umich.edu * @param pkt The memory request to satisfy. 1503860Sstever@eecs.umich.edu * @param new_state The new state of the block. 1513860Sstever@eecs.umich.edu * @param writebacks A list to store any generated writebacks. 1523860Sstever@eecs.umich.edu */ 1534626Sstever@eecs.umich.edu BlkType* doReplacement(BlkType *blk, PacketPtr pkt, 1543860Sstever@eecs.umich.edu CacheBlk::State new_state, PacketList &writebacks); 1553860Sstever@eecs.umich.edu 1563860Sstever@eecs.umich.edu /** 1573860Sstever@eecs.umich.edu * Does all the processing necessary to perform the provided request. 1583860Sstever@eecs.umich.edu * @param pkt The memory request to perform. 1593860Sstever@eecs.umich.edu * @param lat The latency of the access. 1603860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 1613860Sstever@eecs.umich.edu * @param update True if the replacement data should be updated. 1623860Sstever@eecs.umich.edu * @return Pointer to the cache block touched by the request. NULL if it 1633860Sstever@eecs.umich.edu * was a miss. 1643860Sstever@eecs.umich.edu */ 1654628Sstever@eecs.umich.edu bool access(PacketPtr pkt, BlkType *&blk, int &lat); 1664219Srdreslin@umich.edu 1674219Srdreslin@umich.edu /** 1684219Srdreslin@umich.edu *Handle doing the Compare and Swap function for SPARC. 1694219Srdreslin@umich.edu */ 1704626Sstever@eecs.umich.edu void cmpAndSwap(BlkType *blk, PacketPtr pkt); 1713860Sstever@eecs.umich.edu 1723860Sstever@eecs.umich.edu /** 1733860Sstever@eecs.umich.edu * Populates a cache block and handles all outstanding requests for the 1743860Sstever@eecs.umich.edu * satisfied fill request. This version takes two memory requests. One 1753860Sstever@eecs.umich.edu * contains the fill data, the other is an optional target to satisfy. 1763860Sstever@eecs.umich.edu * Used for Cache::probe. 1774626Sstever@eecs.umich.edu * @param pkt The memory request with the fill data. 1783860Sstever@eecs.umich.edu * @param blk The cache block if it already exists. 1793860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 1803860Sstever@eecs.umich.edu * @return Pointer to the new cache block. 1813860Sstever@eecs.umich.edu */ 1824626Sstever@eecs.umich.edu BlkType *handleFill(PacketPtr pkt, BlkType *blk, 1834626Sstever@eecs.umich.edu PacketList &writebacks); 1843860Sstever@eecs.umich.edu 1854665Sstever@eecs.umich.edu void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk); 1864628Sstever@eecs.umich.edu bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk); 1874626Sstever@eecs.umich.edu 1884626Sstever@eecs.umich.edu void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data); 1893860Sstever@eecs.umich.edu 1903860Sstever@eecs.umich.edu /** 1913860Sstever@eecs.umich.edu * Sets the blk to the new state. 1923860Sstever@eecs.umich.edu * @param blk The cache block being snooped. 1933860Sstever@eecs.umich.edu * @param new_state The new coherence state for the block. 1943860Sstever@eecs.umich.edu */ 1954626Sstever@eecs.umich.edu void handleSnoop(PacketPtr ptk, BlkType *blk, bool is_timing); 1963860Sstever@eecs.umich.edu 1973860Sstever@eecs.umich.edu /** 1983860Sstever@eecs.umich.edu * Create a writeback request for the given block. 1993860Sstever@eecs.umich.edu * @param blk The block to writeback. 2003860Sstever@eecs.umich.edu * @return The writeback request for the block. 2013860Sstever@eecs.umich.edu */ 2023860Sstever@eecs.umich.edu PacketPtr writebackBlk(BlkType *blk); 2033860Sstever@eecs.umich.edu 2042810Srdreslin@umich.edu public: 2052810Srdreslin@umich.edu 2062810Srdreslin@umich.edu class Params 2072810Srdreslin@umich.edu { 2082810Srdreslin@umich.edu public: 2092810Srdreslin@umich.edu TagStore *tags; 2102810Srdreslin@umich.edu Coherence *coherence; 2112810Srdreslin@umich.edu BaseCache::Params baseParams; 2123861Sstever@eecs.umich.edu BasePrefetcher*prefetcher; 2132810Srdreslin@umich.edu bool prefetchAccess; 2143860Sstever@eecs.umich.edu const bool doFastWrites; 2153860Sstever@eecs.umich.edu const bool prefetchMiss; 2162810Srdreslin@umich.edu 2174626Sstever@eecs.umich.edu Params(TagStore *_tags, Coherence *coh, 2183315Sstever@eecs.umich.edu BaseCache::Params params, 2193861Sstever@eecs.umich.edu BasePrefetcher *_prefetcher, 2203860Sstever@eecs.umich.edu bool prefetch_access, int hit_latency, 2213860Sstever@eecs.umich.edu bool do_fast_writes, 2223860Sstever@eecs.umich.edu bool prefetch_miss) 2234626Sstever@eecs.umich.edu : tags(_tags), coherence(coh), 2243315Sstever@eecs.umich.edu baseParams(params), 2252813Srdreslin@umich.edu prefetcher(_prefetcher), prefetchAccess(prefetch_access), 2263860Sstever@eecs.umich.edu doFastWrites(do_fast_writes), 2274626Sstever@eecs.umich.edu prefetchMiss(prefetch_miss) 2282810Srdreslin@umich.edu { 2292810Srdreslin@umich.edu } 2302810Srdreslin@umich.edu }; 2312810Srdreslin@umich.edu 2322810Srdreslin@umich.edu /** Instantiates a basic cache object. */ 2332812Srdreslin@umich.edu Cache(const std::string &_name, Params ¶ms); 2342810Srdreslin@umich.edu 2353738Sstever@eecs.umich.edu virtual Port *getPort(const std::string &if_name, int idx = -1); 2364190Ssaidi@eecs.umich.edu virtual void deletePortRefs(Port *p); 2372813Srdreslin@umich.edu 2382810Srdreslin@umich.edu void regStats(); 2392810Srdreslin@umich.edu 2402810Srdreslin@umich.edu /** 2412810Srdreslin@umich.edu * Performs the access specified by the request. 2422982Sstever@eecs.umich.edu * @param pkt The request to perform. 2432810Srdreslin@umich.edu * @return The result of the access. 2442810Srdreslin@umich.edu */ 2454626Sstever@eecs.umich.edu bool timingAccess(PacketPtr pkt); 2462810Srdreslin@umich.edu 2472810Srdreslin@umich.edu /** 2484626Sstever@eecs.umich.edu * Performs the access specified by the request. 2494626Sstever@eecs.umich.edu * @param pkt The request to perform. 2504626Sstever@eecs.umich.edu * @return The result of the access. 2512810Srdreslin@umich.edu */ 2524626Sstever@eecs.umich.edu Tick atomicAccess(PacketPtr pkt); 2532810Srdreslin@umich.edu 2542810Srdreslin@umich.edu /** 2554626Sstever@eecs.umich.edu * Performs the access specified by the request. 2564626Sstever@eecs.umich.edu * @param pkt The request to perform. 2574626Sstever@eecs.umich.edu * @return The result of the access. 2582810Srdreslin@umich.edu */ 2594626Sstever@eecs.umich.edu void functionalAccess(PacketPtr pkt, CachePort *otherSidePort); 2603293Srdreslin@umich.edu 2613293Srdreslin@umich.edu /** 2622810Srdreslin@umich.edu * Handles a response (cache line fill/write ack) from the bus. 2632982Sstever@eecs.umich.edu * @param pkt The request being responded to. 2642810Srdreslin@umich.edu */ 2654626Sstever@eecs.umich.edu void handleResponse(PacketPtr pkt); 2662810Srdreslin@umich.edu 2672810Srdreslin@umich.edu /** 2682810Srdreslin@umich.edu * Snoops bus transactions to maintain coherence. 2692982Sstever@eecs.umich.edu * @param pkt The current bus transaction. 2702810Srdreslin@umich.edu */ 2714626Sstever@eecs.umich.edu void snoopTiming(PacketPtr pkt); 2722810Srdreslin@umich.edu 2734626Sstever@eecs.umich.edu /** 2744626Sstever@eecs.umich.edu * Snoop for the provided request in the cache and return the estimated 2754626Sstever@eecs.umich.edu * time of completion. 2764626Sstever@eecs.umich.edu * @param pkt The memory request to snoop 2774626Sstever@eecs.umich.edu * @return The estimated completion time. 2784626Sstever@eecs.umich.edu */ 2794626Sstever@eecs.umich.edu Tick snoopAtomic(PacketPtr pkt); 2802810Srdreslin@umich.edu 2812810Srdreslin@umich.edu /** 2822982Sstever@eecs.umich.edu * Squash all requests associated with specified thread. 2832810Srdreslin@umich.edu * intended for use by I-cache. 2842982Sstever@eecs.umich.edu * @param threadNum The thread to squash. 2852810Srdreslin@umich.edu */ 2864626Sstever@eecs.umich.edu void squash(int threadNum); 2874626Sstever@eecs.umich.edu 2884626Sstever@eecs.umich.edu /** 2894626Sstever@eecs.umich.edu * Selects a outstanding request to service. 2904626Sstever@eecs.umich.edu * @return The request to service, NULL if none found. 2914626Sstever@eecs.umich.edu */ 2924628Sstever@eecs.umich.edu PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk, 2934628Sstever@eecs.umich.edu bool needsExclusive); 2944626Sstever@eecs.umich.edu MSHR *getNextMSHR(); 2954628Sstever@eecs.umich.edu PacketPtr getTimingPacket(); 2964626Sstever@eecs.umich.edu 2974626Sstever@eecs.umich.edu /** 2984626Sstever@eecs.umich.edu * Marks a request as in service (sent on the bus). This can have side 2994626Sstever@eecs.umich.edu * effect since storage for no response commands is deallocated once they 3004626Sstever@eecs.umich.edu * are successfully sent. 3014626Sstever@eecs.umich.edu * @param pkt The request that was sent on the bus. 3024626Sstever@eecs.umich.edu */ 3034626Sstever@eecs.umich.edu void markInService(MSHR *mshr); 3044626Sstever@eecs.umich.edu 3054626Sstever@eecs.umich.edu /** 3064626Sstever@eecs.umich.edu * Perform the given writeback request. 3074626Sstever@eecs.umich.edu * @param pkt The writeback request. 3084626Sstever@eecs.umich.edu */ 3094626Sstever@eecs.umich.edu void doWriteback(PacketPtr pkt); 3104626Sstever@eecs.umich.edu 3114626Sstever@eecs.umich.edu /** 3124626Sstever@eecs.umich.edu * Return whether there are any outstanding misses. 3134626Sstever@eecs.umich.edu */ 3144626Sstever@eecs.umich.edu bool outstandingMisses() const 3152810Srdreslin@umich.edu { 3164626Sstever@eecs.umich.edu return mshrQueue.allocated != 0; 3172810Srdreslin@umich.edu } 3182810Srdreslin@umich.edu 3194626Sstever@eecs.umich.edu CacheBlk *findBlock(Addr addr) { 3204626Sstever@eecs.umich.edu return tags->findBlock(addr); 3212810Srdreslin@umich.edu } 3222810Srdreslin@umich.edu 3233861Sstever@eecs.umich.edu bool inCache(Addr addr) { 3243861Sstever@eecs.umich.edu return (tags->findBlock(addr) != 0); 3253861Sstever@eecs.umich.edu } 3263861Sstever@eecs.umich.edu 3273861Sstever@eecs.umich.edu bool inMissQueue(Addr addr) { 3284626Sstever@eecs.umich.edu return (mshrQueue.findMatch(addr) != 0); 3293861Sstever@eecs.umich.edu } 3302810Srdreslin@umich.edu}; 3312810Srdreslin@umich.edu 3322810Srdreslin@umich.edu#endif // __CACHE_HH__ 333