cache.hh revision 3861
12810Srdreslin@umich.edu/* 22810Srdreslin@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 32810Srdreslin@umich.edu * All rights reserved. 42810Srdreslin@umich.edu * 52810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 62810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 72810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 82810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 92810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 102810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 112810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 122810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 132810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 142810Srdreslin@umich.edu * this software without specific prior written permission. 152810Srdreslin@umich.edu * 162810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * Authors: Erik Hallnor 292810Srdreslin@umich.edu * Dave Greene 302810Srdreslin@umich.edu * Steve Reinhardt 312810Srdreslin@umich.edu */ 322810Srdreslin@umich.edu 332810Srdreslin@umich.edu/** 342810Srdreslin@umich.edu * @file 352810Srdreslin@umich.edu * Describes a cache based on template policies. 362810Srdreslin@umich.edu */ 372810Srdreslin@umich.edu 382810Srdreslin@umich.edu#ifndef __CACHE_HH__ 392810Srdreslin@umich.edu#define __CACHE_HH__ 402810Srdreslin@umich.edu 413860Sstever@eecs.umich.edu#include "base/compression/base.hh" 422810Srdreslin@umich.edu#include "base/misc.hh" // fatal, panic, and warn 432810Srdreslin@umich.edu#include "cpu/smt.hh" // SMT_MAX_THREADS 442810Srdreslin@umich.edu 452810Srdreslin@umich.edu#include "mem/cache/base_cache.hh" 463860Sstever@eecs.umich.edu#include "mem/cache/cache_blk.hh" 473719Sstever@eecs.umich.edu#include "mem/cache/miss/miss_buffer.hh" 482810Srdreslin@umich.edu 492813Srdreslin@umich.edu//Forward decleration 502813Srdreslin@umich.educlass MSHR; 513861Sstever@eecs.umich.educlass BasePrefetcher; 522810Srdreslin@umich.edu 532810Srdreslin@umich.edu/** 542810Srdreslin@umich.edu * A template-policy based cache. The behavior of the cache can be altered by 552810Srdreslin@umich.edu * supplying different template policies. TagStore handles all tag and data 562810Srdreslin@umich.edu * storage @sa TagStore. Buffering handles all misses and writes/writebacks 572810Srdreslin@umich.edu * @sa MissQueue. Coherence handles all coherence policy details @sa 582810Srdreslin@umich.edu * UniCoherence, SimpleMultiCoherence. 592810Srdreslin@umich.edu */ 603719Sstever@eecs.umich.edutemplate <class TagStore, class Coherence> 612810Srdreslin@umich.educlass Cache : public BaseCache 622810Srdreslin@umich.edu{ 632810Srdreslin@umich.edu public: 642810Srdreslin@umich.edu /** Define the type of cache block to use. */ 652810Srdreslin@umich.edu typedef typename TagStore::BlkType BlkType; 663860Sstever@eecs.umich.edu /** A typedef for a list of BlkType pointers. */ 673860Sstever@eecs.umich.edu typedef typename TagStore::BlkList BlkList; 682810Srdreslin@umich.edu 692810Srdreslin@umich.edu bool prefetchAccess; 703738Sstever@eecs.umich.edu 712810Srdreslin@umich.edu protected: 722810Srdreslin@umich.edu 733738Sstever@eecs.umich.edu class CpuSidePort : public CachePort 743738Sstever@eecs.umich.edu { 753738Sstever@eecs.umich.edu public: 763738Sstever@eecs.umich.edu CpuSidePort(const std::string &_name, 773738Sstever@eecs.umich.edu Cache<TagStore,Coherence> *_cache); 783738Sstever@eecs.umich.edu 793738Sstever@eecs.umich.edu // BaseCache::CachePort just has a BaseCache *; this function 803738Sstever@eecs.umich.edu // lets us get back the type info we lost when we stored the 813738Sstever@eecs.umich.edu // cache pointer there. 823738Sstever@eecs.umich.edu Cache<TagStore,Coherence> *myCache() { 833738Sstever@eecs.umich.edu return static_cast<Cache<TagStore,Coherence> *>(cache); 843738Sstever@eecs.umich.edu } 853738Sstever@eecs.umich.edu 863738Sstever@eecs.umich.edu virtual bool recvTiming(PacketPtr pkt); 873738Sstever@eecs.umich.edu 883738Sstever@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 893738Sstever@eecs.umich.edu 903738Sstever@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 913738Sstever@eecs.umich.edu }; 923738Sstever@eecs.umich.edu 933738Sstever@eecs.umich.edu class MemSidePort : public CachePort 943738Sstever@eecs.umich.edu { 953738Sstever@eecs.umich.edu public: 963738Sstever@eecs.umich.edu MemSidePort(const std::string &_name, 973738Sstever@eecs.umich.edu Cache<TagStore,Coherence> *_cache); 983738Sstever@eecs.umich.edu 993738Sstever@eecs.umich.edu // BaseCache::CachePort just has a BaseCache *; this function 1003738Sstever@eecs.umich.edu // lets us get back the type info we lost when we stored the 1013738Sstever@eecs.umich.edu // cache pointer there. 1023738Sstever@eecs.umich.edu Cache<TagStore,Coherence> *myCache() { 1033738Sstever@eecs.umich.edu return static_cast<Cache<TagStore,Coherence> *>(cache); 1043738Sstever@eecs.umich.edu } 1053738Sstever@eecs.umich.edu 1063738Sstever@eecs.umich.edu virtual bool recvTiming(PacketPtr pkt); 1073738Sstever@eecs.umich.edu 1083738Sstever@eecs.umich.edu virtual Tick recvAtomic(PacketPtr pkt); 1093738Sstever@eecs.umich.edu 1103738Sstever@eecs.umich.edu virtual void recvFunctional(PacketPtr pkt); 1113738Sstever@eecs.umich.edu }; 1123738Sstever@eecs.umich.edu 1132810Srdreslin@umich.edu /** Tag and data Storage */ 1142810Srdreslin@umich.edu TagStore *tags; 1152810Srdreslin@umich.edu /** Miss and Writeback handler */ 1163719Sstever@eecs.umich.edu MissBuffer *missQueue; 1172810Srdreslin@umich.edu /** Coherence protocol. */ 1182810Srdreslin@umich.edu Coherence *coherence; 1192810Srdreslin@umich.edu 1202810Srdreslin@umich.edu /** Prefetcher */ 1213861Sstever@eecs.umich.edu BasePrefetcher *prefetcher; 1222810Srdreslin@umich.edu 1232810Srdreslin@umich.edu /** 1242810Srdreslin@umich.edu * The clock ratio of the outgoing bus. 1252810Srdreslin@umich.edu * Used for calculating critical word first. 1262810Srdreslin@umich.edu */ 1272810Srdreslin@umich.edu int busRatio; 1282810Srdreslin@umich.edu 1292810Srdreslin@umich.edu /** 1302810Srdreslin@umich.edu * The bus width in bytes of the outgoing bus. 1312810Srdreslin@umich.edu * Used for calculating critical word first. 1322810Srdreslin@umich.edu */ 1332810Srdreslin@umich.edu int busWidth; 1342810Srdreslin@umich.edu 1352813Srdreslin@umich.edu /** 1362813Srdreslin@umich.edu * The latency of a hit in this device. 1372813Srdreslin@umich.edu */ 1382813Srdreslin@umich.edu int hitLatency; 1392813Srdreslin@umich.edu 1402810Srdreslin@umich.edu /** 1412810Srdreslin@umich.edu * A permanent mem req to always be used to cause invalidations. 1422810Srdreslin@umich.edu * Used to append to target list, to cause an invalidation. 1432810Srdreslin@umich.edu */ 1443349Sbinkertn@umich.edu PacketPtr invalidatePkt; 1453208Srdreslin@umich.edu Request *invalidateReq; 1462810Srdreslin@umich.edu 1473860Sstever@eecs.umich.edu /** 1483860Sstever@eecs.umich.edu * Policy class for performing compression. 1493860Sstever@eecs.umich.edu */ 1503860Sstever@eecs.umich.edu CompressionAlgorithm *compressionAlg; 1513860Sstever@eecs.umich.edu 1523860Sstever@eecs.umich.edu /** 1533860Sstever@eecs.umich.edu * The block size of this cache. Set to value in the Tags object. 1543860Sstever@eecs.umich.edu */ 1553860Sstever@eecs.umich.edu const int16_t blkSize; 1563860Sstever@eecs.umich.edu 1573860Sstever@eecs.umich.edu /** 1583860Sstever@eecs.umich.edu * Can this cache should allocate a block on a line-sized write miss. 1593860Sstever@eecs.umich.edu */ 1603860Sstever@eecs.umich.edu const bool doFastWrites; 1613860Sstever@eecs.umich.edu 1623860Sstever@eecs.umich.edu const bool prefetchMiss; 1633860Sstever@eecs.umich.edu 1643860Sstever@eecs.umich.edu /** 1653860Sstever@eecs.umich.edu * Can the data can be stored in a compressed form. 1663860Sstever@eecs.umich.edu */ 1673860Sstever@eecs.umich.edu const bool storeCompressed; 1683860Sstever@eecs.umich.edu 1693860Sstever@eecs.umich.edu /** 1703860Sstever@eecs.umich.edu * Do we need to compress blocks on writebacks (i.e. because 1713860Sstever@eecs.umich.edu * writeback bus is compressed but storage is not)? 1723860Sstever@eecs.umich.edu */ 1733860Sstever@eecs.umich.edu const bool compressOnWriteback; 1743860Sstever@eecs.umich.edu 1753860Sstever@eecs.umich.edu /** 1763860Sstever@eecs.umich.edu * The latency of a compression operation. 1773860Sstever@eecs.umich.edu */ 1783860Sstever@eecs.umich.edu const int16_t compLatency; 1793860Sstever@eecs.umich.edu 1803860Sstever@eecs.umich.edu /** 1813860Sstever@eecs.umich.edu * Should we use an adaptive compression scheme. 1823860Sstever@eecs.umich.edu */ 1833860Sstever@eecs.umich.edu const bool adaptiveCompression; 1843860Sstever@eecs.umich.edu 1853860Sstever@eecs.umich.edu /** 1863860Sstever@eecs.umich.edu * Do writebacks need to be compressed (i.e. because writeback bus 1873860Sstever@eecs.umich.edu * is compressed), whether or not they're already compressed for 1883860Sstever@eecs.umich.edu * storage. 1893860Sstever@eecs.umich.edu */ 1903860Sstever@eecs.umich.edu const bool writebackCompressed; 1913860Sstever@eecs.umich.edu 1923860Sstever@eecs.umich.edu /** 1933860Sstever@eecs.umich.edu * Compare the internal block data to the fast access block data. 1943860Sstever@eecs.umich.edu * @param blk The cache block to check. 1953860Sstever@eecs.umich.edu * @return True if the data is the same. 1963860Sstever@eecs.umich.edu */ 1973860Sstever@eecs.umich.edu bool verifyData(BlkType *blk); 1983860Sstever@eecs.umich.edu 1993860Sstever@eecs.umich.edu /** 2003860Sstever@eecs.umich.edu * Update the internal data of the block. The data to write is assumed to 2013860Sstever@eecs.umich.edu * be in the fast access data. 2023860Sstever@eecs.umich.edu * @param blk The block with the data to update. 2033860Sstever@eecs.umich.edu * @param writebacks A list to store any generated writebacks. 2043860Sstever@eecs.umich.edu * @param compress_block True if we should compress this block 2053860Sstever@eecs.umich.edu */ 2063860Sstever@eecs.umich.edu void updateData(BlkType *blk, PacketList &writebacks, bool compress_block); 2073860Sstever@eecs.umich.edu 2083860Sstever@eecs.umich.edu /** 2093860Sstever@eecs.umich.edu * Handle a replacement for the given request. 2103860Sstever@eecs.umich.edu * @param blk A pointer to the block, usually NULL 2113860Sstever@eecs.umich.edu * @param pkt The memory request to satisfy. 2123860Sstever@eecs.umich.edu * @param new_state The new state of the block. 2133860Sstever@eecs.umich.edu * @param writebacks A list to store any generated writebacks. 2143860Sstever@eecs.umich.edu */ 2153860Sstever@eecs.umich.edu BlkType* doReplacement(BlkType *blk, PacketPtr &pkt, 2163860Sstever@eecs.umich.edu CacheBlk::State new_state, PacketList &writebacks); 2173860Sstever@eecs.umich.edu 2183860Sstever@eecs.umich.edu /** 2193860Sstever@eecs.umich.edu * Does all the processing necessary to perform the provided request. 2203860Sstever@eecs.umich.edu * @param pkt The memory request to perform. 2213860Sstever@eecs.umich.edu * @param lat The latency of the access. 2223860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 2233860Sstever@eecs.umich.edu * @param update True if the replacement data should be updated. 2243860Sstever@eecs.umich.edu * @return Pointer to the cache block touched by the request. NULL if it 2253860Sstever@eecs.umich.edu * was a miss. 2263860Sstever@eecs.umich.edu */ 2273860Sstever@eecs.umich.edu BlkType* handleAccess(PacketPtr &pkt, int & lat, 2283860Sstever@eecs.umich.edu PacketList & writebacks, bool update = true); 2293860Sstever@eecs.umich.edu 2303860Sstever@eecs.umich.edu /** 2313860Sstever@eecs.umich.edu * Populates a cache block and handles all outstanding requests for the 2323860Sstever@eecs.umich.edu * satisfied fill request. This version takes an MSHR pointer and uses its 2333860Sstever@eecs.umich.edu * request to fill the cache block, while repsonding to its targets. 2343860Sstever@eecs.umich.edu * @param blk The cache block if it already exists. 2353860Sstever@eecs.umich.edu * @param mshr The MSHR that contains the fill data and targets to satisfy. 2363860Sstever@eecs.umich.edu * @param new_state The state of the new cache block. 2373860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 2383860Sstever@eecs.umich.edu * @return Pointer to the new cache block. 2393860Sstever@eecs.umich.edu */ 2403860Sstever@eecs.umich.edu BlkType* handleFill(BlkType *blk, MSHR * mshr, CacheBlk::State new_state, 2413860Sstever@eecs.umich.edu PacketList & writebacks, PacketPtr pkt); 2423860Sstever@eecs.umich.edu 2433860Sstever@eecs.umich.edu /** 2443860Sstever@eecs.umich.edu * Populates a cache block and handles all outstanding requests for the 2453860Sstever@eecs.umich.edu * satisfied fill request. This version takes two memory requests. One 2463860Sstever@eecs.umich.edu * contains the fill data, the other is an optional target to satisfy. 2473860Sstever@eecs.umich.edu * Used for Cache::probe. 2483860Sstever@eecs.umich.edu * @param blk The cache block if it already exists. 2493860Sstever@eecs.umich.edu * @param pkt The memory request with the fill data. 2503860Sstever@eecs.umich.edu * @param new_state The state of the new cache block. 2513860Sstever@eecs.umich.edu * @param writebacks List for any writebacks that need to be performed. 2523860Sstever@eecs.umich.edu * @param target The memory request to perform after the fill. 2533860Sstever@eecs.umich.edu * @return Pointer to the new cache block. 2543860Sstever@eecs.umich.edu */ 2553860Sstever@eecs.umich.edu BlkType* handleFill(BlkType *blk, PacketPtr &pkt, 2563860Sstever@eecs.umich.edu CacheBlk::State new_state, 2573860Sstever@eecs.umich.edu PacketList & writebacks, PacketPtr target = NULL); 2583860Sstever@eecs.umich.edu 2593860Sstever@eecs.umich.edu /** 2603860Sstever@eecs.umich.edu * Sets the blk to the new state and handles the given request. 2613860Sstever@eecs.umich.edu * @param blk The cache block being snooped. 2623860Sstever@eecs.umich.edu * @param new_state The new coherence state for the block. 2633860Sstever@eecs.umich.edu * @param pkt The request to satisfy 2643860Sstever@eecs.umich.edu */ 2653860Sstever@eecs.umich.edu void handleSnoop(BlkType *blk, CacheBlk::State new_state, 2663860Sstever@eecs.umich.edu PacketPtr &pkt); 2673860Sstever@eecs.umich.edu 2683860Sstever@eecs.umich.edu /** 2693860Sstever@eecs.umich.edu * Sets the blk to the new state. 2703860Sstever@eecs.umich.edu * @param blk The cache block being snooped. 2713860Sstever@eecs.umich.edu * @param new_state The new coherence state for the block. 2723860Sstever@eecs.umich.edu */ 2733860Sstever@eecs.umich.edu void handleSnoop(BlkType *blk, CacheBlk::State new_state); 2743860Sstever@eecs.umich.edu 2753860Sstever@eecs.umich.edu /** 2763860Sstever@eecs.umich.edu * Create a writeback request for the given block. 2773860Sstever@eecs.umich.edu * @param blk The block to writeback. 2783860Sstever@eecs.umich.edu * @return The writeback request for the block. 2793860Sstever@eecs.umich.edu */ 2803860Sstever@eecs.umich.edu PacketPtr writebackBlk(BlkType *blk); 2813860Sstever@eecs.umich.edu 2823860Sstever@eecs.umich.edu BlkType* findBlock(Addr addr) 2833860Sstever@eecs.umich.edu { 2843860Sstever@eecs.umich.edu return tags->findBlock(addr); 2853860Sstever@eecs.umich.edu } 2863860Sstever@eecs.umich.edu 2873860Sstever@eecs.umich.edu BlkType* findBlock(PacketPtr &pkt) 2883860Sstever@eecs.umich.edu { 2893860Sstever@eecs.umich.edu return tags->findBlock(pkt->getAddr()); 2903860Sstever@eecs.umich.edu } 2913860Sstever@eecs.umich.edu 2923860Sstever@eecs.umich.edu void invalidateBlk(CacheBlk *blk) 2933860Sstever@eecs.umich.edu { 2943860Sstever@eecs.umich.edu tags->invalidateBlk(tags->regenerateBlkAddr(blk->tag, blk->set)); 2953860Sstever@eecs.umich.edu } 2963860Sstever@eecs.umich.edu 2972810Srdreslin@umich.edu public: 2982810Srdreslin@umich.edu 2992810Srdreslin@umich.edu class Params 3002810Srdreslin@umich.edu { 3012810Srdreslin@umich.edu public: 3022810Srdreslin@umich.edu TagStore *tags; 3033719Sstever@eecs.umich.edu MissBuffer *missQueue; 3042810Srdreslin@umich.edu Coherence *coherence; 3052810Srdreslin@umich.edu BaseCache::Params baseParams; 3063861Sstever@eecs.umich.edu BasePrefetcher*prefetcher; 3072810Srdreslin@umich.edu bool prefetchAccess; 3082813Srdreslin@umich.edu int hitLatency; 3093860Sstever@eecs.umich.edu CompressionAlgorithm *compressionAlg; 3103860Sstever@eecs.umich.edu const int16_t blkSize; 3113860Sstever@eecs.umich.edu const bool doFastWrites; 3123860Sstever@eecs.umich.edu const bool prefetchMiss; 3133860Sstever@eecs.umich.edu const bool storeCompressed; 3143860Sstever@eecs.umich.edu const bool compressOnWriteback; 3153860Sstever@eecs.umich.edu const int16_t compLatency; 3163860Sstever@eecs.umich.edu const bool adaptiveCompression; 3173860Sstever@eecs.umich.edu const bool writebackCompressed; 3182810Srdreslin@umich.edu 3193719Sstever@eecs.umich.edu Params(TagStore *_tags, MissBuffer *mq, Coherence *coh, 3203315Sstever@eecs.umich.edu BaseCache::Params params, 3213861Sstever@eecs.umich.edu BasePrefetcher *_prefetcher, 3223860Sstever@eecs.umich.edu bool prefetch_access, int hit_latency, 3233860Sstever@eecs.umich.edu bool do_fast_writes, 3243860Sstever@eecs.umich.edu bool store_compressed, bool adaptive_compression, 3253860Sstever@eecs.umich.edu bool writeback_compressed, 3263860Sstever@eecs.umich.edu CompressionAlgorithm *_compressionAlg, int comp_latency, 3273860Sstever@eecs.umich.edu bool prefetch_miss) 3283315Sstever@eecs.umich.edu : tags(_tags), missQueue(mq), coherence(coh), 3293315Sstever@eecs.umich.edu baseParams(params), 3302813Srdreslin@umich.edu prefetcher(_prefetcher), prefetchAccess(prefetch_access), 3313860Sstever@eecs.umich.edu hitLatency(hit_latency), 3323860Sstever@eecs.umich.edu compressionAlg(_compressionAlg), 3333860Sstever@eecs.umich.edu blkSize(_tags->getBlockSize()), 3343860Sstever@eecs.umich.edu doFastWrites(do_fast_writes), 3353860Sstever@eecs.umich.edu prefetchMiss(prefetch_miss), 3363860Sstever@eecs.umich.edu storeCompressed(store_compressed), 3373860Sstever@eecs.umich.edu compressOnWriteback(!store_compressed && writeback_compressed), 3383860Sstever@eecs.umich.edu compLatency(comp_latency), 3393860Sstever@eecs.umich.edu adaptiveCompression(adaptive_compression), 3403860Sstever@eecs.umich.edu writebackCompressed(writeback_compressed) 3412810Srdreslin@umich.edu { 3422810Srdreslin@umich.edu } 3432810Srdreslin@umich.edu }; 3442810Srdreslin@umich.edu 3452810Srdreslin@umich.edu /** Instantiates a basic cache object. */ 3462812Srdreslin@umich.edu Cache(const std::string &_name, Params ¶ms); 3472810Srdreslin@umich.edu 3483738Sstever@eecs.umich.edu virtual Port *getPort(const std::string &if_name, int idx = -1); 3492813Srdreslin@umich.edu 3502825Srdreslin@umich.edu virtual void recvStatusChange(Port::Status status, bool isCpuSide); 3512813Srdreslin@umich.edu 3522810Srdreslin@umich.edu void regStats(); 3532810Srdreslin@umich.edu 3542810Srdreslin@umich.edu /** 3552810Srdreslin@umich.edu * Performs the access specified by the request. 3562982Sstever@eecs.umich.edu * @param pkt The request to perform. 3572810Srdreslin@umich.edu * @return The result of the access. 3582810Srdreslin@umich.edu */ 3593349Sbinkertn@umich.edu bool access(PacketPtr &pkt); 3602810Srdreslin@umich.edu 3612810Srdreslin@umich.edu /** 3622810Srdreslin@umich.edu * Selects a request to send on the bus. 3632810Srdreslin@umich.edu * @return The memory request to service. 3642810Srdreslin@umich.edu */ 3653349Sbinkertn@umich.edu virtual PacketPtr getPacket(); 3662810Srdreslin@umich.edu 3672810Srdreslin@umich.edu /** 3682810Srdreslin@umich.edu * Was the request was sent successfully? 3692982Sstever@eecs.umich.edu * @param pkt The request. 3702810Srdreslin@umich.edu * @param success True if the request was sent successfully. 3712810Srdreslin@umich.edu */ 3723349Sbinkertn@umich.edu virtual void sendResult(PacketPtr &pkt, MSHR* mshr, bool success); 3732810Srdreslin@umich.edu 3742810Srdreslin@umich.edu /** 3753293Srdreslin@umich.edu * Was the CSHR request was sent successfully? 3763293Srdreslin@umich.edu * @param pkt The request. 3773293Srdreslin@umich.edu * @param success True if the request was sent successfully. 3783293Srdreslin@umich.edu */ 3793349Sbinkertn@umich.edu virtual void sendCoherenceResult(PacketPtr &pkt, MSHR* cshr, bool success); 3803293Srdreslin@umich.edu 3813293Srdreslin@umich.edu /** 3822810Srdreslin@umich.edu * Handles a response (cache line fill/write ack) from the bus. 3832982Sstever@eecs.umich.edu * @param pkt The request being responded to. 3842810Srdreslin@umich.edu */ 3853349Sbinkertn@umich.edu void handleResponse(PacketPtr &pkt); 3862810Srdreslin@umich.edu 3872810Srdreslin@umich.edu /** 3882810Srdreslin@umich.edu * Selects a coherence message to forward to lower levels of the hierarchy. 3892810Srdreslin@umich.edu * @return The coherence message to forward. 3902810Srdreslin@umich.edu */ 3913349Sbinkertn@umich.edu virtual PacketPtr getCoherencePacket(); 3922810Srdreslin@umich.edu 3932810Srdreslin@umich.edu /** 3942810Srdreslin@umich.edu * Snoops bus transactions to maintain coherence. 3952982Sstever@eecs.umich.edu * @param pkt The current bus transaction. 3962810Srdreslin@umich.edu */ 3973349Sbinkertn@umich.edu void snoop(PacketPtr &pkt); 3982810Srdreslin@umich.edu 3993349Sbinkertn@umich.edu void snoopResponse(PacketPtr &pkt); 4002810Srdreslin@umich.edu 4012810Srdreslin@umich.edu /** 4022810Srdreslin@umich.edu * Invalidates the block containing address if found. 4032810Srdreslin@umich.edu * @param addr The address to look for. 4042810Srdreslin@umich.edu * @param asid The address space ID of the address. 4052810Srdreslin@umich.edu * @todo Is this function necessary? 4062810Srdreslin@umich.edu */ 4072991Srdreslin@umich.edu void invalidateBlk(Addr addr); 4082810Srdreslin@umich.edu 4092810Srdreslin@umich.edu /** 4102982Sstever@eecs.umich.edu * Squash all requests associated with specified thread. 4112810Srdreslin@umich.edu * intended for use by I-cache. 4122982Sstever@eecs.umich.edu * @param threadNum The thread to squash. 4132810Srdreslin@umich.edu */ 4142811Srdreslin@umich.edu void squash(int threadNum) 4152810Srdreslin@umich.edu { 4162811Srdreslin@umich.edu missQueue->squash(threadNum); 4172810Srdreslin@umich.edu } 4182810Srdreslin@umich.edu 4192810Srdreslin@umich.edu /** 4202810Srdreslin@umich.edu * Return the number of outstanding misses in a Cache. 4212810Srdreslin@umich.edu * Default returns 0. 4222810Srdreslin@umich.edu * 4232810Srdreslin@umich.edu * @retval unsigned The number of missing still outstanding. 4242810Srdreslin@umich.edu */ 4252810Srdreslin@umich.edu unsigned outstandingMisses() const 4262810Srdreslin@umich.edu { 4272810Srdreslin@umich.edu return missQueue->getMisses(); 4282810Srdreslin@umich.edu } 4292810Srdreslin@umich.edu 4302810Srdreslin@umich.edu /** 4312810Srdreslin@umich.edu * Perform the access specified in the request and return the estimated 4322810Srdreslin@umich.edu * time of completion. This function can either update the hierarchy state 4332810Srdreslin@umich.edu * or just perform the access wherever the data is found depending on the 4342810Srdreslin@umich.edu * state of the update flag. 4352982Sstever@eecs.umich.edu * @param pkt The memory request to satisfy 4362810Srdreslin@umich.edu * @param update If true, update the hierarchy, otherwise just perform the 4372810Srdreslin@umich.edu * request. 4382810Srdreslin@umich.edu * @return The estimated completion time. 4392810Srdreslin@umich.edu */ 4403349Sbinkertn@umich.edu Tick probe(PacketPtr &pkt, bool update, CachePort * otherSidePort); 4412810Srdreslin@umich.edu 4422810Srdreslin@umich.edu /** 4432810Srdreslin@umich.edu * Snoop for the provided request in the cache and return the estimated 4442810Srdreslin@umich.edu * time of completion. 4452810Srdreslin@umich.edu * @todo Can a snoop probe not change state? 4462982Sstever@eecs.umich.edu * @param pkt The memory request to satisfy 4472810Srdreslin@umich.edu * @param update If true, update the hierarchy, otherwise just perform the 4482810Srdreslin@umich.edu * request. 4492810Srdreslin@umich.edu * @return The estimated completion time. 4502810Srdreslin@umich.edu */ 4513349Sbinkertn@umich.edu Tick snoopProbe(PacketPtr &pkt); 4523861Sstever@eecs.umich.edu 4533861Sstever@eecs.umich.edu bool inCache(Addr addr) { 4543861Sstever@eecs.umich.edu return (tags->findBlock(addr) != 0); 4553861Sstever@eecs.umich.edu } 4563861Sstever@eecs.umich.edu 4573861Sstever@eecs.umich.edu bool inMissQueue(Addr addr) { 4583861Sstever@eecs.umich.edu return (missQueue->findMSHR(addr) != 0); 4593861Sstever@eecs.umich.edu } 4602810Srdreslin@umich.edu}; 4612810Srdreslin@umich.edu 4622810Srdreslin@umich.edu#endif // __CACHE_HH__ 463