cache.cc revision 12500
12810Srdreslin@umich.edu/* 212500Snikos.nikoleris@arm.com * Copyright (c) 2010-2018 ARM Limited 311051Sandreas.hansson@arm.com * All rights reserved. 411051Sandreas.hansson@arm.com * 511051Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 611051Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 711051Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 811051Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 911051Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 1011051Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 1111051Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 1211051Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 1311051Sandreas.hansson@arm.com * 1411051Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1511051Sandreas.hansson@arm.com * Copyright (c) 2010,2015 Advanced Micro Devices, Inc. 162810Srdreslin@umich.edu * All rights reserved. 172810Srdreslin@umich.edu * 182810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 192810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 202810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 212810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 222810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 232810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 242810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 252810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 262810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 272810Srdreslin@umich.edu * this software without specific prior written permission. 282810Srdreslin@umich.edu * 292810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402810Srdreslin@umich.edu * 412810Srdreslin@umich.edu * Authors: Erik Hallnor 4211051Sandreas.hansson@arm.com * Dave Greene 4311051Sandreas.hansson@arm.com * Nathan Binkert 442810Srdreslin@umich.edu * Steve Reinhardt 4511051Sandreas.hansson@arm.com * Ron Dreslinski 4611051Sandreas.hansson@arm.com * Andreas Sandberg 4712349Snikos.nikoleris@arm.com * Nikos Nikoleris 482810Srdreslin@umich.edu */ 492810Srdreslin@umich.edu 502810Srdreslin@umich.edu/** 512810Srdreslin@umich.edu * @file 5211051Sandreas.hansson@arm.com * Cache definitions. 532810Srdreslin@umich.edu */ 542810Srdreslin@umich.edu 5511051Sandreas.hansson@arm.com#include "mem/cache/cache.hh" 562810Srdreslin@umich.edu 5712334Sgabeblack@google.com#include "base/logging.hh" 5811051Sandreas.hansson@arm.com#include "base/types.hh" 5911051Sandreas.hansson@arm.com#include "debug/Cache.hh" 6011051Sandreas.hansson@arm.com#include "debug/CachePort.hh" 6111051Sandreas.hansson@arm.com#include "debug/CacheTags.hh" 6211288Ssteve.reinhardt@amd.com#include "debug/CacheVerbose.hh" 6311051Sandreas.hansson@arm.com#include "mem/cache/blk.hh" 6411051Sandreas.hansson@arm.com#include "mem/cache/mshr.hh" 6511051Sandreas.hansson@arm.com#include "mem/cache/prefetch/base.hh" 6611051Sandreas.hansson@arm.com#include "sim/sim_exit.hh" 6711051Sandreas.hansson@arm.com 6811053Sandreas.hansson@arm.comCache::Cache(const CacheParams *p) 6911053Sandreas.hansson@arm.com : BaseCache(p, p->system->cacheLineSize()), 7011051Sandreas.hansson@arm.com tags(p->tags), 7111051Sandreas.hansson@arm.com prefetcher(p->prefetcher), 7211051Sandreas.hansson@arm.com doFastWrites(true), 7311197Sandreas.hansson@arm.com prefetchOnAccess(p->prefetch_on_access), 7411197Sandreas.hansson@arm.com clusivity(p->clusivity), 7511199Sandreas.hansson@arm.com writebackClean(p->writeback_clean), 7611197Sandreas.hansson@arm.com tempBlockWriteback(nullptr), 7712084Sspwilson2@wisc.edu writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); }, 7812084Sspwilson2@wisc.edu name(), false, 7911197Sandreas.hansson@arm.com EventBase::Delayed_Writeback_Pri) 8011051Sandreas.hansson@arm.com{ 8111051Sandreas.hansson@arm.com tempBlock = new CacheBlk(); 8211051Sandreas.hansson@arm.com tempBlock->data = new uint8_t[blkSize]; 8311051Sandreas.hansson@arm.com 8411051Sandreas.hansson@arm.com cpuSidePort = new CpuSidePort(p->name + ".cpu_side", this, 8511051Sandreas.hansson@arm.com "CpuSidePort"); 8611051Sandreas.hansson@arm.com memSidePort = new MemSidePort(p->name + ".mem_side", this, 8711051Sandreas.hansson@arm.com "MemSidePort"); 8811051Sandreas.hansson@arm.com 8911051Sandreas.hansson@arm.com tags->setCache(this); 9011051Sandreas.hansson@arm.com if (prefetcher) 9111051Sandreas.hansson@arm.com prefetcher->setCache(this); 9211051Sandreas.hansson@arm.com} 9311051Sandreas.hansson@arm.com 9411051Sandreas.hansson@arm.comCache::~Cache() 9511051Sandreas.hansson@arm.com{ 9611051Sandreas.hansson@arm.com delete [] tempBlock->data; 9711051Sandreas.hansson@arm.com delete tempBlock; 9811051Sandreas.hansson@arm.com 9911051Sandreas.hansson@arm.com delete cpuSidePort; 10011051Sandreas.hansson@arm.com delete memSidePort; 10111051Sandreas.hansson@arm.com} 10211051Sandreas.hansson@arm.com 10311051Sandreas.hansson@arm.comvoid 10411051Sandreas.hansson@arm.comCache::regStats() 10511051Sandreas.hansson@arm.com{ 10611051Sandreas.hansson@arm.com BaseCache::regStats(); 10711051Sandreas.hansson@arm.com} 10811051Sandreas.hansson@arm.com 10911051Sandreas.hansson@arm.comvoid 11011051Sandreas.hansson@arm.comCache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt) 11111051Sandreas.hansson@arm.com{ 11211051Sandreas.hansson@arm.com assert(pkt->isRequest()); 11311051Sandreas.hansson@arm.com 11411051Sandreas.hansson@arm.com uint64_t overwrite_val; 11511051Sandreas.hansson@arm.com bool overwrite_mem; 11611051Sandreas.hansson@arm.com uint64_t condition_val64; 11711051Sandreas.hansson@arm.com uint32_t condition_val32; 11811051Sandreas.hansson@arm.com 11911051Sandreas.hansson@arm.com int offset = tags->extractBlkOffset(pkt->getAddr()); 12011051Sandreas.hansson@arm.com uint8_t *blk_data = blk->data + offset; 12111051Sandreas.hansson@arm.com 12211051Sandreas.hansson@arm.com assert(sizeof(uint64_t) >= pkt->getSize()); 12311051Sandreas.hansson@arm.com 12411051Sandreas.hansson@arm.com overwrite_mem = true; 12511051Sandreas.hansson@arm.com // keep a copy of our possible write value, and copy what is at the 12611051Sandreas.hansson@arm.com // memory address into the packet 12711051Sandreas.hansson@arm.com pkt->writeData((uint8_t *)&overwrite_val); 12811051Sandreas.hansson@arm.com pkt->setData(blk_data); 12911051Sandreas.hansson@arm.com 13011051Sandreas.hansson@arm.com if (pkt->req->isCondSwap()) { 13111051Sandreas.hansson@arm.com if (pkt->getSize() == sizeof(uint64_t)) { 13211051Sandreas.hansson@arm.com condition_val64 = pkt->req->getExtraData(); 13311051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val64, blk_data, 13411051Sandreas.hansson@arm.com sizeof(uint64_t)); 13511051Sandreas.hansson@arm.com } else if (pkt->getSize() == sizeof(uint32_t)) { 13611051Sandreas.hansson@arm.com condition_val32 = (uint32_t)pkt->req->getExtraData(); 13711051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val32, blk_data, 13811051Sandreas.hansson@arm.com sizeof(uint32_t)); 13911051Sandreas.hansson@arm.com } else 14011051Sandreas.hansson@arm.com panic("Invalid size for conditional read/write\n"); 14111051Sandreas.hansson@arm.com } 14211051Sandreas.hansson@arm.com 14311051Sandreas.hansson@arm.com if (overwrite_mem) { 14411051Sandreas.hansson@arm.com std::memcpy(blk_data, &overwrite_val, pkt->getSize()); 14511051Sandreas.hansson@arm.com blk->status |= BlkDirty; 14611051Sandreas.hansson@arm.com } 14711051Sandreas.hansson@arm.com} 14811051Sandreas.hansson@arm.com 14911051Sandreas.hansson@arm.com 15011051Sandreas.hansson@arm.comvoid 15111601Sandreas.hansson@arm.comCache::satisfyRequest(PacketPtr pkt, CacheBlk *blk, 15211601Sandreas.hansson@arm.com bool deferred_response, bool pending_downgrade) 15311051Sandreas.hansson@arm.com{ 15411051Sandreas.hansson@arm.com assert(pkt->isRequest()); 15511051Sandreas.hansson@arm.com 15611051Sandreas.hansson@arm.com assert(blk && blk->isValid()); 15711051Sandreas.hansson@arm.com // Occasionally this is not true... if we are a lower-level cache 15811051Sandreas.hansson@arm.com // satisfying a string of Read and ReadEx requests from 15911051Sandreas.hansson@arm.com // upper-level caches, a Read will mark the block as shared but we 16011051Sandreas.hansson@arm.com // can satisfy a following ReadEx anyway since we can rely on the 16111051Sandreas.hansson@arm.com // Read requester(s) to have buffered the ReadEx snoop and to 16211051Sandreas.hansson@arm.com // invalidate their blocks after receiving them. 16311284Sandreas.hansson@arm.com // assert(!pkt->needsWritable() || blk->isWritable()); 16411051Sandreas.hansson@arm.com assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize); 16511051Sandreas.hansson@arm.com 16611051Sandreas.hansson@arm.com // Check RMW operations first since both isRead() and 16711051Sandreas.hansson@arm.com // isWrite() will be true for them 16811051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::SwapReq) { 16911051Sandreas.hansson@arm.com cmpAndSwap(blk, pkt); 17011051Sandreas.hansson@arm.com } else if (pkt->isWrite()) { 17111284Sandreas.hansson@arm.com // we have the block in a writable state and can go ahead, 17211284Sandreas.hansson@arm.com // note that the line may be also be considered writable in 17311284Sandreas.hansson@arm.com // downstream caches along the path to memory, but always 17411284Sandreas.hansson@arm.com // Exclusive, and never Modified 17511051Sandreas.hansson@arm.com assert(blk->isWritable()); 17611284Sandreas.hansson@arm.com // Write or WriteLine at the first cache with block in writable state 17711051Sandreas.hansson@arm.com if (blk->checkWrite(pkt)) { 17811051Sandreas.hansson@arm.com pkt->writeDataToBlock(blk->data, blkSize); 17911051Sandreas.hansson@arm.com } 18011284Sandreas.hansson@arm.com // Always mark the line as dirty (and thus transition to the 18111284Sandreas.hansson@arm.com // Modified state) even if we are a failed StoreCond so we 18211284Sandreas.hansson@arm.com // supply data to any snoops that have appended themselves to 18311284Sandreas.hansson@arm.com // this cache before knowing the store will fail. 18411051Sandreas.hansson@arm.com blk->status |= BlkDirty; 18511744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s for %s (write)\n", __func__, pkt->print()); 18611051Sandreas.hansson@arm.com } else if (pkt->isRead()) { 18711051Sandreas.hansson@arm.com if (pkt->isLLSC()) { 18811051Sandreas.hansson@arm.com blk->trackLoadLocked(pkt); 18911051Sandreas.hansson@arm.com } 19011286Sandreas.hansson@arm.com 19111286Sandreas.hansson@arm.com // all read responses have a data payload 19211286Sandreas.hansson@arm.com assert(pkt->hasRespData()); 19311051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 19411286Sandreas.hansson@arm.com 19511600Sandreas.hansson@arm.com // determine if this read is from a (coherent) cache or not 19611600Sandreas.hansson@arm.com if (pkt->fromCache()) { 19711051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 19811051Sandreas.hansson@arm.com // special handling for coherent block requests from 19911051Sandreas.hansson@arm.com // upper-level caches 20011284Sandreas.hansson@arm.com if (pkt->needsWritable()) { 20111051Sandreas.hansson@arm.com // sanity check 20211051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::ReadExReq || 20311051Sandreas.hansson@arm.com pkt->cmd == MemCmd::SCUpgradeFailReq); 20411602Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 20511051Sandreas.hansson@arm.com 20611051Sandreas.hansson@arm.com // if we have a dirty copy, make sure the recipient 20711284Sandreas.hansson@arm.com // keeps it marked dirty (in the modified state) 20811051Sandreas.hansson@arm.com if (blk->isDirty()) { 20911284Sandreas.hansson@arm.com pkt->setCacheResponding(); 21011602Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 21111051Sandreas.hansson@arm.com } 21211051Sandreas.hansson@arm.com } else if (blk->isWritable() && !pending_downgrade && 21311284Sandreas.hansson@arm.com !pkt->hasSharers() && 21411051Sandreas.hansson@arm.com pkt->cmd != MemCmd::ReadCleanReq) { 21511284Sandreas.hansson@arm.com // we can give the requester a writable copy on a read 21611284Sandreas.hansson@arm.com // request if: 21711284Sandreas.hansson@arm.com // - we have a writable copy at this level (& below) 21811051Sandreas.hansson@arm.com // - we don't have a pending snoop from below 21911051Sandreas.hansson@arm.com // signaling another read request 22011051Sandreas.hansson@arm.com // - no other cache above has a copy (otherwise it 22111284Sandreas.hansson@arm.com // would have set hasSharers flag when 22211284Sandreas.hansson@arm.com // snooping the packet) 22311284Sandreas.hansson@arm.com // - the read has explicitly asked for a clean 22411284Sandreas.hansson@arm.com // copy of the line 22511051Sandreas.hansson@arm.com if (blk->isDirty()) { 22611051Sandreas.hansson@arm.com // special considerations if we're owner: 22711051Sandreas.hansson@arm.com if (!deferred_response) { 22811284Sandreas.hansson@arm.com // respond with the line in Modified state 22911284Sandreas.hansson@arm.com // (cacheResponding set, hasSharers not set) 23011284Sandreas.hansson@arm.com pkt->setCacheResponding(); 23111197Sandreas.hansson@arm.com 23211601Sandreas.hansson@arm.com // if this cache is mostly inclusive, we 23311601Sandreas.hansson@arm.com // keep the block in the Exclusive state, 23411601Sandreas.hansson@arm.com // and pass it upwards as Modified 23511601Sandreas.hansson@arm.com // (writable and dirty), hence we have 23611601Sandreas.hansson@arm.com // multiple caches, all on the same path 23711601Sandreas.hansson@arm.com // towards memory, all considering the 23811601Sandreas.hansson@arm.com // same block writable, but only one 23911601Sandreas.hansson@arm.com // considering it Modified 24011197Sandreas.hansson@arm.com 24111601Sandreas.hansson@arm.com // we get away with multiple caches (on 24211601Sandreas.hansson@arm.com // the same path to memory) considering 24311601Sandreas.hansson@arm.com // the block writeable as we always enter 24411601Sandreas.hansson@arm.com // the cache hierarchy through a cache, 24511601Sandreas.hansson@arm.com // and first snoop upwards in all other 24611601Sandreas.hansson@arm.com // branches 24711601Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 24811051Sandreas.hansson@arm.com } else { 24911051Sandreas.hansson@arm.com // if we're responding after our own miss, 25011051Sandreas.hansson@arm.com // there's a window where the recipient didn't 25111051Sandreas.hansson@arm.com // know it was getting ownership and may not 25211051Sandreas.hansson@arm.com // have responded to snoops correctly, so we 25311284Sandreas.hansson@arm.com // have to respond with a shared line 25411284Sandreas.hansson@arm.com pkt->setHasSharers(); 25511051Sandreas.hansson@arm.com } 25611051Sandreas.hansson@arm.com } 25711051Sandreas.hansson@arm.com } else { 25811051Sandreas.hansson@arm.com // otherwise only respond with a shared copy 25911284Sandreas.hansson@arm.com pkt->setHasSharers(); 26011051Sandreas.hansson@arm.com } 26111051Sandreas.hansson@arm.com } 26211602Sandreas.hansson@arm.com } else if (pkt->isUpgrade()) { 26311602Sandreas.hansson@arm.com // sanity check 26411602Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 26511602Sandreas.hansson@arm.com 26611602Sandreas.hansson@arm.com if (blk->isDirty()) { 26711602Sandreas.hansson@arm.com // we were in the Owned state, and a cache above us that 26811602Sandreas.hansson@arm.com // has the line in Shared state needs to be made aware 26911602Sandreas.hansson@arm.com // that the data it already has is in fact dirty 27011602Sandreas.hansson@arm.com pkt->setCacheResponding(); 27111602Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 27211602Sandreas.hansson@arm.com } 27311051Sandreas.hansson@arm.com } else { 27411602Sandreas.hansson@arm.com assert(pkt->isInvalidate()); 27511197Sandreas.hansson@arm.com invalidateBlock(blk); 27611744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s for %s (invalidation)\n", __func__, 27711744Snikos.nikoleris@arm.com pkt->print()); 27811051Sandreas.hansson@arm.com } 27911051Sandreas.hansson@arm.com} 28011051Sandreas.hansson@arm.com 28111051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 28211051Sandreas.hansson@arm.com// 28311051Sandreas.hansson@arm.com// Access path: requests coming in from the CPU side 28411051Sandreas.hansson@arm.com// 28511051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 28611051Sandreas.hansson@arm.com 28711051Sandreas.hansson@arm.combool 28811051Sandreas.hansson@arm.comCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 28911051Sandreas.hansson@arm.com PacketList &writebacks) 29011051Sandreas.hansson@arm.com{ 29111051Sandreas.hansson@arm.com // sanity check 29211051Sandreas.hansson@arm.com assert(pkt->isRequest()); 29311051Sandreas.hansson@arm.com 29411051Sandreas.hansson@arm.com chatty_assert(!(isReadOnly && pkt->isWrite()), 29511051Sandreas.hansson@arm.com "Should never see a write in a read-only cache %s\n", 29611051Sandreas.hansson@arm.com name()); 29711051Sandreas.hansson@arm.com 29811744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s for %s\n", __func__, pkt->print()); 29911051Sandreas.hansson@arm.com 30011051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 30111744Snikos.nikoleris@arm.com DPRINTF(Cache, "uncacheable: %s\n", pkt->print()); 30211051Sandreas.hansson@arm.com 30311051Sandreas.hansson@arm.com // flush and invalidate any existing block 30411051Sandreas.hansson@arm.com CacheBlk *old_blk(tags->findBlock(pkt->getAddr(), pkt->isSecure())); 30511051Sandreas.hansson@arm.com if (old_blk && old_blk->isValid()) { 30611199Sandreas.hansson@arm.com if (old_blk->isDirty() || writebackClean) 30711051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(old_blk)); 30811051Sandreas.hansson@arm.com else 30911051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(old_blk)); 31011867Snikos.nikoleris@arm.com invalidateBlock(old_blk); 31111051Sandreas.hansson@arm.com } 31211051Sandreas.hansson@arm.com 31311484Snikos.nikoleris@arm.com blk = nullptr; 31411051Sandreas.hansson@arm.com // lookupLatency is the latency in case the request is uncacheable. 31511051Sandreas.hansson@arm.com lat = lookupLatency; 31611051Sandreas.hansson@arm.com return false; 31711051Sandreas.hansson@arm.com } 31811051Sandreas.hansson@arm.com 31911051Sandreas.hansson@arm.com // Here lat is the value passed as parameter to accessBlock() function 32011051Sandreas.hansson@arm.com // that can modify its value. 32111870Snikos.nikoleris@arm.com blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat); 32211051Sandreas.hansson@arm.com 32311744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s %s\n", pkt->print(), 32411051Sandreas.hansson@arm.com blk ? "hit " + blk->print() : "miss"); 32511051Sandreas.hansson@arm.com 32612349Snikos.nikoleris@arm.com if (pkt->req->isCacheMaintenance()) { 32712349Snikos.nikoleris@arm.com // A cache maintenance operation is always forwarded to the 32812349Snikos.nikoleris@arm.com // memory below even if the block is found in dirty state. 32912349Snikos.nikoleris@arm.com 33012349Snikos.nikoleris@arm.com // We defer any changes to the state of the block until we 33112349Snikos.nikoleris@arm.com // create and mark as in service the mshr for the downstream 33212349Snikos.nikoleris@arm.com // packet. 33312349Snikos.nikoleris@arm.com return false; 33412349Snikos.nikoleris@arm.com } 33511051Sandreas.hansson@arm.com 33611199Sandreas.hansson@arm.com if (pkt->isEviction()) { 33711051Sandreas.hansson@arm.com // We check for presence of block in above caches before issuing 33811051Sandreas.hansson@arm.com // Writeback or CleanEvict to write buffer. Therefore the only 33911051Sandreas.hansson@arm.com // possible cases can be of a CleanEvict packet coming from above 34011051Sandreas.hansson@arm.com // encountering a Writeback generated in this cache peer cache and 34111051Sandreas.hansson@arm.com // waiting in the write buffer. Cases of upper level peer caches 34211051Sandreas.hansson@arm.com // generating CleanEvict and Writeback or simply CleanEvict and 34311051Sandreas.hansson@arm.com // CleanEvict almost simultaneously will be caught by snoops sent out 34411051Sandreas.hansson@arm.com // by crossbar. 34511375Sandreas.hansson@arm.com WriteQueueEntry *wb_entry = writeBuffer.findMatch(pkt->getAddr(), 34611375Sandreas.hansson@arm.com pkt->isSecure()); 34711375Sandreas.hansson@arm.com if (wb_entry) { 34811199Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 34911199Sandreas.hansson@arm.com PacketPtr wbPkt = wb_entry->getTarget()->pkt; 35011199Sandreas.hansson@arm.com assert(wbPkt->isWriteback()); 35111199Sandreas.hansson@arm.com 35211199Sandreas.hansson@arm.com if (pkt->isCleanEviction()) { 35311199Sandreas.hansson@arm.com // The CleanEvict and WritebackClean snoops into other 35411199Sandreas.hansson@arm.com // peer caches of the same level while traversing the 35511199Sandreas.hansson@arm.com // crossbar. If a copy of the block is found, the 35611199Sandreas.hansson@arm.com // packet is deleted in the crossbar. Hence, none of 35711199Sandreas.hansson@arm.com // the other upper level caches connected to this 35811199Sandreas.hansson@arm.com // cache have the block, so we can clear the 35911199Sandreas.hansson@arm.com // BLOCK_CACHED flag in the Writeback if set and 36011199Sandreas.hansson@arm.com // discard the CleanEvict by returning true. 36111199Sandreas.hansson@arm.com wbPkt->clearBlockCached(); 36211199Sandreas.hansson@arm.com return true; 36311199Sandreas.hansson@arm.com } else { 36411199Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::WritebackDirty); 36511199Sandreas.hansson@arm.com // Dirty writeback from above trumps our clean 36611199Sandreas.hansson@arm.com // writeback... discard here 36711199Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 36811375Sandreas.hansson@arm.com markInService(wb_entry); 36911199Sandreas.hansson@arm.com delete wbPkt; 37011199Sandreas.hansson@arm.com } 37111051Sandreas.hansson@arm.com } 37211051Sandreas.hansson@arm.com } 37311051Sandreas.hansson@arm.com 37411051Sandreas.hansson@arm.com // Writeback handling is special case. We can write the block into 37511051Sandreas.hansson@arm.com // the cache without having a writeable copy (or any copy at all). 37611199Sandreas.hansson@arm.com if (pkt->isWriteback()) { 37711051Sandreas.hansson@arm.com assert(blkSize == pkt->getSize()); 37811199Sandreas.hansson@arm.com 37911199Sandreas.hansson@arm.com // we could get a clean writeback while we are having 38011199Sandreas.hansson@arm.com // outstanding accesses to a block, do the simple thing for 38111199Sandreas.hansson@arm.com // now and drop the clean writeback so that we do not upset 38211199Sandreas.hansson@arm.com // any ordering/decisions about ownership already taken 38311199Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WritebackClean && 38411199Sandreas.hansson@arm.com mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) { 38511199Sandreas.hansson@arm.com DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, " 38611199Sandreas.hansson@arm.com "dropping\n", pkt->getAddr()); 38711199Sandreas.hansson@arm.com return true; 38811199Sandreas.hansson@arm.com } 38911199Sandreas.hansson@arm.com 39011484Snikos.nikoleris@arm.com if (blk == nullptr) { 39111051Sandreas.hansson@arm.com // need to do a replacement 39211051Sandreas.hansson@arm.com blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), writebacks); 39311484Snikos.nikoleris@arm.com if (blk == nullptr) { 39411051Sandreas.hansson@arm.com // no replaceable block available: give up, fwd to next level. 39511051Sandreas.hansson@arm.com incMissCount(pkt); 39611051Sandreas.hansson@arm.com return false; 39711051Sandreas.hansson@arm.com } 39811051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 39911051Sandreas.hansson@arm.com 40011051Sandreas.hansson@arm.com blk->status = (BlkValid | BlkReadable); 40111051Sandreas.hansson@arm.com if (pkt->isSecure()) { 40211051Sandreas.hansson@arm.com blk->status |= BlkSecure; 40311051Sandreas.hansson@arm.com } 40411051Sandreas.hansson@arm.com } 40511199Sandreas.hansson@arm.com // only mark the block dirty if we got a writeback command, 40611199Sandreas.hansson@arm.com // and leave it as is for a clean writeback 40711199Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WritebackDirty) { 40812500Snikos.nikoleris@arm.com assert(!blk->isDirty()); 40911199Sandreas.hansson@arm.com blk->status |= BlkDirty; 41011199Sandreas.hansson@arm.com } 41111284Sandreas.hansson@arm.com // if the packet does not have sharers, it is passing 41211284Sandreas.hansson@arm.com // writable, and we got the writeback in Modified or Exclusive 41311284Sandreas.hansson@arm.com // state, if not we are in the Owned or Shared state 41411284Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 41511051Sandreas.hansson@arm.com blk->status |= BlkWritable; 41611051Sandreas.hansson@arm.com } 41711051Sandreas.hansson@arm.com // nothing else to do; writeback doesn't expect response 41811051Sandreas.hansson@arm.com assert(!pkt->needsResponse()); 41911051Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 42011051Sandreas.hansson@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 42111051Sandreas.hansson@arm.com incHitCount(pkt); 42211051Sandreas.hansson@arm.com return true; 42311051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::CleanEvict) { 42411484Snikos.nikoleris@arm.com if (blk != nullptr) { 42511051Sandreas.hansson@arm.com // Found the block in the tags, need to stop CleanEvict from 42611051Sandreas.hansson@arm.com // propagating further down the hierarchy. Returning true will 42711051Sandreas.hansson@arm.com // treat the CleanEvict like a satisfied write request and delete 42811051Sandreas.hansson@arm.com // it. 42911051Sandreas.hansson@arm.com return true; 43011051Sandreas.hansson@arm.com } 43111051Sandreas.hansson@arm.com // We didn't find the block here, propagate the CleanEvict further 43211051Sandreas.hansson@arm.com // down the memory hierarchy. Returning false will treat the CleanEvict 43311051Sandreas.hansson@arm.com // like a Writeback which could not find a replaceable block so has to 43411051Sandreas.hansson@arm.com // go to next level. 43511051Sandreas.hansson@arm.com return false; 43612345Snikos.nikoleris@arm.com } else if (pkt->cmd == MemCmd::WriteClean) { 43712345Snikos.nikoleris@arm.com // WriteClean handling is a special case. We can allocate a 43812345Snikos.nikoleris@arm.com // block directly if it doesn't exist and we can update the 43912345Snikos.nikoleris@arm.com // block immediately. The WriteClean transfers the ownership 44012345Snikos.nikoleris@arm.com // of the block as well. 44112345Snikos.nikoleris@arm.com assert(blkSize == pkt->getSize()); 44212345Snikos.nikoleris@arm.com 44312345Snikos.nikoleris@arm.com if (!blk) { 44412346Snikos.nikoleris@arm.com if (pkt->writeThrough()) { 44512346Snikos.nikoleris@arm.com // if this is a write through packet, we don't try to 44612346Snikos.nikoleris@arm.com // allocate if the block is not present 44712345Snikos.nikoleris@arm.com return false; 44812346Snikos.nikoleris@arm.com } else { 44912346Snikos.nikoleris@arm.com // a writeback that misses needs to allocate a new block 45012346Snikos.nikoleris@arm.com blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), 45112346Snikos.nikoleris@arm.com writebacks); 45212346Snikos.nikoleris@arm.com if (!blk) { 45312346Snikos.nikoleris@arm.com // no replaceable block available: give up, fwd to 45412346Snikos.nikoleris@arm.com // next level. 45512346Snikos.nikoleris@arm.com incMissCount(pkt); 45612346Snikos.nikoleris@arm.com return false; 45712346Snikos.nikoleris@arm.com } 45812346Snikos.nikoleris@arm.com tags->insertBlock(pkt, blk); 45912346Snikos.nikoleris@arm.com 46012346Snikos.nikoleris@arm.com blk->status = (BlkValid | BlkReadable); 46112346Snikos.nikoleris@arm.com if (pkt->isSecure()) { 46212346Snikos.nikoleris@arm.com blk->status |= BlkSecure; 46312346Snikos.nikoleris@arm.com } 46412345Snikos.nikoleris@arm.com } 46512345Snikos.nikoleris@arm.com } 46612345Snikos.nikoleris@arm.com 46712345Snikos.nikoleris@arm.com // at this point either this is a writeback or a write-through 46812345Snikos.nikoleris@arm.com // write clean operation and the block is already in this 46912345Snikos.nikoleris@arm.com // cache, we need to update the data and the block flags 47012345Snikos.nikoleris@arm.com assert(blk); 47112500Snikos.nikoleris@arm.com assert(!blk->isDirty()); 47212346Snikos.nikoleris@arm.com if (!pkt->writeThrough()) { 47312346Snikos.nikoleris@arm.com blk->status |= BlkDirty; 47412346Snikos.nikoleris@arm.com } 47512345Snikos.nikoleris@arm.com // nothing else to do; writeback doesn't expect response 47612345Snikos.nikoleris@arm.com assert(!pkt->needsResponse()); 47712345Snikos.nikoleris@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 47812345Snikos.nikoleris@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 47912345Snikos.nikoleris@arm.com 48012345Snikos.nikoleris@arm.com incHitCount(pkt); 48112345Snikos.nikoleris@arm.com // populate the time when the block will be ready to access. 48212345Snikos.nikoleris@arm.com blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay + 48312345Snikos.nikoleris@arm.com pkt->payloadDelay; 48412346Snikos.nikoleris@arm.com // if this a write-through packet it will be sent to cache 48512346Snikos.nikoleris@arm.com // below 48612346Snikos.nikoleris@arm.com return !pkt->writeThrough(); 48711601Sandreas.hansson@arm.com } else if (blk && (pkt->needsWritable() ? blk->isWritable() : 48811601Sandreas.hansson@arm.com blk->isReadable())) { 48911051Sandreas.hansson@arm.com // OK to satisfy access 49011051Sandreas.hansson@arm.com incHitCount(pkt); 49111601Sandreas.hansson@arm.com satisfyRequest(pkt, blk); 49211601Sandreas.hansson@arm.com maintainClusivity(pkt->fromCache(), blk); 49311601Sandreas.hansson@arm.com 49411051Sandreas.hansson@arm.com return true; 49511051Sandreas.hansson@arm.com } 49611051Sandreas.hansson@arm.com 49711484Snikos.nikoleris@arm.com // Can't satisfy access normally... either no block (blk == nullptr) 49811284Sandreas.hansson@arm.com // or have block but need writable 49911051Sandreas.hansson@arm.com 50011051Sandreas.hansson@arm.com incMissCount(pkt); 50111051Sandreas.hansson@arm.com 50211484Snikos.nikoleris@arm.com if (blk == nullptr && pkt->isLLSC() && pkt->isWrite()) { 50311051Sandreas.hansson@arm.com // complete miss on store conditional... just give up now 50411051Sandreas.hansson@arm.com pkt->req->setExtraData(0); 50511051Sandreas.hansson@arm.com return true; 50611051Sandreas.hansson@arm.com } 50711051Sandreas.hansson@arm.com 50811051Sandreas.hansson@arm.com return false; 50911051Sandreas.hansson@arm.com} 51011051Sandreas.hansson@arm.com 51111051Sandreas.hansson@arm.comvoid 51211601Sandreas.hansson@arm.comCache::maintainClusivity(bool from_cache, CacheBlk *blk) 51311601Sandreas.hansson@arm.com{ 51411601Sandreas.hansson@arm.com if (from_cache && blk && blk->isValid() && !blk->isDirty() && 51511601Sandreas.hansson@arm.com clusivity == Enums::mostly_excl) { 51611601Sandreas.hansson@arm.com // if we have responded to a cache, and our block is still 51711601Sandreas.hansson@arm.com // valid, but not dirty, and this cache is mostly exclusive 51811601Sandreas.hansson@arm.com // with respect to the cache above, drop the block 51911601Sandreas.hansson@arm.com invalidateBlock(blk); 52011601Sandreas.hansson@arm.com } 52111601Sandreas.hansson@arm.com} 52211601Sandreas.hansson@arm.com 52311601Sandreas.hansson@arm.comvoid 52411051Sandreas.hansson@arm.comCache::doWritebacks(PacketList& writebacks, Tick forward_time) 52511051Sandreas.hansson@arm.com{ 52611051Sandreas.hansson@arm.com while (!writebacks.empty()) { 52711051Sandreas.hansson@arm.com PacketPtr wbPkt = writebacks.front(); 52811051Sandreas.hansson@arm.com // We use forwardLatency here because we are copying writebacks to 52912345Snikos.nikoleris@arm.com // write buffer. 53012345Snikos.nikoleris@arm.com 53112345Snikos.nikoleris@arm.com // Call isCachedAbove for Writebacks, CleanEvicts and 53212345Snikos.nikoleris@arm.com // WriteCleans to discover if the block is cached above. 53311051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) { 53411051Sandreas.hansson@arm.com if (wbPkt->cmd == MemCmd::CleanEvict) { 53511051Sandreas.hansson@arm.com // Delete CleanEvict because cached copies exist above. The 53611051Sandreas.hansson@arm.com // packet destructor will delete the request object because 53711051Sandreas.hansson@arm.com // this is a non-snoop request packet which does not require a 53811051Sandreas.hansson@arm.com // response. 53911051Sandreas.hansson@arm.com delete wbPkt; 54011199Sandreas.hansson@arm.com } else if (wbPkt->cmd == MemCmd::WritebackClean) { 54111199Sandreas.hansson@arm.com // clean writeback, do not send since the block is 54211199Sandreas.hansson@arm.com // still cached above 54311199Sandreas.hansson@arm.com assert(writebackClean); 54411199Sandreas.hansson@arm.com delete wbPkt; 54511051Sandreas.hansson@arm.com } else { 54612345Snikos.nikoleris@arm.com assert(wbPkt->cmd == MemCmd::WritebackDirty || 54712345Snikos.nikoleris@arm.com wbPkt->cmd == MemCmd::WriteClean); 54811051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag in Writeback and send below, so that 54911051Sandreas.hansson@arm.com // the Writeback does not reset the bit corresponding to this 55011051Sandreas.hansson@arm.com // address in the snoop filter below. 55111051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 55211051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 55311051Sandreas.hansson@arm.com } 55411051Sandreas.hansson@arm.com } else { 55511051Sandreas.hansson@arm.com // If the block is not cached above, send packet below. Both 55611051Sandreas.hansson@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 55711051Sandreas.hansson@arm.com // reset the bit corresponding to this address in the snoop filter 55811051Sandreas.hansson@arm.com // below. 55911051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 56011051Sandreas.hansson@arm.com } 56111051Sandreas.hansson@arm.com writebacks.pop_front(); 56211051Sandreas.hansson@arm.com } 56311051Sandreas.hansson@arm.com} 56411051Sandreas.hansson@arm.com 56511130Sali.jafri@arm.comvoid 56611130Sali.jafri@arm.comCache::doWritebacksAtomic(PacketList& writebacks) 56711130Sali.jafri@arm.com{ 56811130Sali.jafri@arm.com while (!writebacks.empty()) { 56911130Sali.jafri@arm.com PacketPtr wbPkt = writebacks.front(); 57011130Sali.jafri@arm.com // Call isCachedAbove for both Writebacks and CleanEvicts. If 57111130Sali.jafri@arm.com // isCachedAbove returns true we set BLOCK_CACHED flag in Writebacks 57211130Sali.jafri@arm.com // and discard CleanEvicts. 57311130Sali.jafri@arm.com if (isCachedAbove(wbPkt, false)) { 57412345Snikos.nikoleris@arm.com if (wbPkt->cmd == MemCmd::WritebackDirty || 57512345Snikos.nikoleris@arm.com wbPkt->cmd == MemCmd::WriteClean) { 57611130Sali.jafri@arm.com // Set BLOCK_CACHED flag in Writeback and send below, 57711130Sali.jafri@arm.com // so that the Writeback does not reset the bit 57811130Sali.jafri@arm.com // corresponding to this address in the snoop filter 57911130Sali.jafri@arm.com // below. We can discard CleanEvicts because cached 58011130Sali.jafri@arm.com // copies exist above. Atomic mode isCachedAbove 58111130Sali.jafri@arm.com // modifies packet to set BLOCK_CACHED flag 58211130Sali.jafri@arm.com memSidePort->sendAtomic(wbPkt); 58311130Sali.jafri@arm.com } 58411130Sali.jafri@arm.com } else { 58511130Sali.jafri@arm.com // If the block is not cached above, send packet below. Both 58611130Sali.jafri@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 58711130Sali.jafri@arm.com // reset the bit corresponding to this address in the snoop filter 58811130Sali.jafri@arm.com // below. 58911130Sali.jafri@arm.com memSidePort->sendAtomic(wbPkt); 59011130Sali.jafri@arm.com } 59111130Sali.jafri@arm.com writebacks.pop_front(); 59211130Sali.jafri@arm.com // In case of CleanEvicts, the packet destructor will delete the 59311130Sali.jafri@arm.com // request object because this is a non-snoop request packet which 59411130Sali.jafri@arm.com // does not require a response. 59511130Sali.jafri@arm.com delete wbPkt; 59611130Sali.jafri@arm.com } 59711130Sali.jafri@arm.com} 59811130Sali.jafri@arm.com 59911051Sandreas.hansson@arm.com 60011051Sandreas.hansson@arm.comvoid 60111051Sandreas.hansson@arm.comCache::recvTimingSnoopResp(PacketPtr pkt) 60211051Sandreas.hansson@arm.com{ 60311744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s for %s\n", __func__, pkt->print()); 60411051Sandreas.hansson@arm.com 60511051Sandreas.hansson@arm.com assert(pkt->isResponse()); 60611051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 60711051Sandreas.hansson@arm.com 60811276Sandreas.hansson@arm.com // determine if the response is from a snoop request we created 60911276Sandreas.hansson@arm.com // (in which case it should be in the outstandingSnoop), or if we 61011276Sandreas.hansson@arm.com // merely forwarded someone else's snoop request 61111276Sandreas.hansson@arm.com const bool forwardAsSnoop = outstandingSnoop.find(pkt->req) == 61211276Sandreas.hansson@arm.com outstandingSnoop.end(); 61311276Sandreas.hansson@arm.com 61411276Sandreas.hansson@arm.com if (!forwardAsSnoop) { 61511276Sandreas.hansson@arm.com // the packet came from this cache, so sink it here and do not 61611276Sandreas.hansson@arm.com // forward it 61711051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::HardPFResp); 61811276Sandreas.hansson@arm.com 61911276Sandreas.hansson@arm.com outstandingSnoop.erase(pkt->req); 62011276Sandreas.hansson@arm.com 62111276Sandreas.hansson@arm.com DPRINTF(Cache, "Got prefetch response from above for addr " 62211276Sandreas.hansson@arm.com "%#llx (%s)\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 62311051Sandreas.hansson@arm.com recvTimingResp(pkt); 62411051Sandreas.hansson@arm.com return; 62511051Sandreas.hansson@arm.com } 62611051Sandreas.hansson@arm.com 62711051Sandreas.hansson@arm.com // forwardLatency is set here because there is a response from an 62811051Sandreas.hansson@arm.com // upper level cache. 62911051Sandreas.hansson@arm.com // To pay the delay that occurs if the packet comes from the bus, 63011051Sandreas.hansson@arm.com // we charge also headerDelay. 63111051Sandreas.hansson@arm.com Tick snoop_resp_time = clockEdge(forwardLatency) + pkt->headerDelay; 63211051Sandreas.hansson@arm.com // Reset the timing of the packet. 63311051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 63411051Sandreas.hansson@arm.com memSidePort->schedTimingSnoopResp(pkt, snoop_resp_time); 63511051Sandreas.hansson@arm.com} 63611051Sandreas.hansson@arm.com 63711051Sandreas.hansson@arm.comvoid 63811051Sandreas.hansson@arm.comCache::promoteWholeLineWrites(PacketPtr pkt) 63911051Sandreas.hansson@arm.com{ 64011051Sandreas.hansson@arm.com // Cache line clearing instructions 64111051Sandreas.hansson@arm.com if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) && 64211051Sandreas.hansson@arm.com (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0)) { 64311051Sandreas.hansson@arm.com pkt->cmd = MemCmd::WriteLineReq; 64411051Sandreas.hansson@arm.com DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n"); 64511051Sandreas.hansson@arm.com } 64611051Sandreas.hansson@arm.com} 64711051Sandreas.hansson@arm.com 64811051Sandreas.hansson@arm.combool 64911051Sandreas.hansson@arm.comCache::recvTimingReq(PacketPtr pkt) 65011051Sandreas.hansson@arm.com{ 65111830Sbaz21@cam.ac.uk DPRINTF(CacheTags, "%s tags:\n%s\n", __func__, tags->print()); 65211051Sandreas.hansson@arm.com 65311051Sandreas.hansson@arm.com assert(pkt->isRequest()); 65411051Sandreas.hansson@arm.com 65511051Sandreas.hansson@arm.com // Just forward the packet if caches are disabled. 65611051Sandreas.hansson@arm.com if (system->bypassCaches()) { 65711051Sandreas.hansson@arm.com // @todo This should really enqueue the packet rather 65811051Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt); 65911051Sandreas.hansson@arm.com assert(success); 66011051Sandreas.hansson@arm.com return true; 66111051Sandreas.hansson@arm.com } 66211051Sandreas.hansson@arm.com 66311051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 66411051Sandreas.hansson@arm.com 66512349Snikos.nikoleris@arm.com // Cache maintenance operations have to visit all the caches down 66612349Snikos.nikoleris@arm.com // to the specified xbar (PoC, PoU, etc.). Even if a cache above 66712349Snikos.nikoleris@arm.com // is responding we forward the packet to the memory below rather 66812349Snikos.nikoleris@arm.com // than creating an express snoop. 66911284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 67011051Sandreas.hansson@arm.com // a cache above us (but not where the packet came from) is 67111284Sandreas.hansson@arm.com // responding to the request, in other words it has the line 67211284Sandreas.hansson@arm.com // in Modified or Owned state 67311744Snikos.nikoleris@arm.com DPRINTF(Cache, "Cache above responding to %s: not responding\n", 67411744Snikos.nikoleris@arm.com pkt->print()); 67511051Sandreas.hansson@arm.com 67611284Sandreas.hansson@arm.com // if the packet needs the block to be writable, and the cache 67711284Sandreas.hansson@arm.com // that has promised to respond (setting the cache responding 67811284Sandreas.hansson@arm.com // flag) is not providing writable (it is in Owned rather than 67911284Sandreas.hansson@arm.com // the Modified state), we know that there may be other Shared 68011284Sandreas.hansson@arm.com // copies in the system; go out and invalidate them all 68111334Sandreas.hansson@arm.com assert(pkt->needsWritable() && !pkt->responderHadWritable()); 68211284Sandreas.hansson@arm.com 68311334Sandreas.hansson@arm.com // an upstream cache that had the line in Owned state 68411334Sandreas.hansson@arm.com // (dirty, but not writable), is responding and thus 68511334Sandreas.hansson@arm.com // transferring the dirty line from one branch of the 68611334Sandreas.hansson@arm.com // cache hierarchy to another 68711284Sandreas.hansson@arm.com 68811334Sandreas.hansson@arm.com // send out an express snoop and invalidate all other 68911334Sandreas.hansson@arm.com // copies (snooping a packet that needs writable is the 69011334Sandreas.hansson@arm.com // same as an invalidation), thus turning the Owned line 69111334Sandreas.hansson@arm.com // into a Modified line, note that we don't invalidate the 69211334Sandreas.hansson@arm.com // block in the current cache or any other cache on the 69311334Sandreas.hansson@arm.com // path to memory 69411051Sandreas.hansson@arm.com 69511334Sandreas.hansson@arm.com // create a downstream express snoop with cleared packet 69611334Sandreas.hansson@arm.com // flags, there is no need to allocate any data as the 69711334Sandreas.hansson@arm.com // packet is merely used to co-ordinate state transitions 69811334Sandreas.hansson@arm.com Packet *snoop_pkt = new Packet(pkt, true, false); 69911051Sandreas.hansson@arm.com 70011334Sandreas.hansson@arm.com // also reset the bus time that the original packet has 70111334Sandreas.hansson@arm.com // not yet paid for 70211334Sandreas.hansson@arm.com snoop_pkt->headerDelay = snoop_pkt->payloadDelay = 0; 70311051Sandreas.hansson@arm.com 70411334Sandreas.hansson@arm.com // make this an instantaneous express snoop, and let the 70511334Sandreas.hansson@arm.com // other caches in the system know that the another cache 70611334Sandreas.hansson@arm.com // is responding, because we have found the authorative 70711334Sandreas.hansson@arm.com // copy (Modified or Owned) that will supply the right 70811334Sandreas.hansson@arm.com // data 70911334Sandreas.hansson@arm.com snoop_pkt->setExpressSnoop(); 71011334Sandreas.hansson@arm.com snoop_pkt->setCacheResponding(); 71111051Sandreas.hansson@arm.com 71211334Sandreas.hansson@arm.com // this express snoop travels towards the memory, and at 71311334Sandreas.hansson@arm.com // every crossbar it is snooped upwards thus reaching 71411334Sandreas.hansson@arm.com // every cache in the system 71511334Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(snoop_pkt); 71611334Sandreas.hansson@arm.com // express snoops always succeed 71711334Sandreas.hansson@arm.com assert(success); 71811334Sandreas.hansson@arm.com 71911334Sandreas.hansson@arm.com // main memory will delete the snoop packet 72011051Sandreas.hansson@arm.com 72111284Sandreas.hansson@arm.com // queue for deletion, as opposed to immediate deletion, as 72211284Sandreas.hansson@arm.com // the sending cache is still relying on the packet 72311190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 72411051Sandreas.hansson@arm.com 72511334Sandreas.hansson@arm.com // no need to take any further action in this particular cache 72611334Sandreas.hansson@arm.com // as an upstram cache has already committed to responding, 72711334Sandreas.hansson@arm.com // and we have already sent out any express snoops in the 72811334Sandreas.hansson@arm.com // section above to ensure all other copies in the system are 72911334Sandreas.hansson@arm.com // invalidated 73011051Sandreas.hansson@arm.com return true; 73111051Sandreas.hansson@arm.com } 73211051Sandreas.hansson@arm.com 73311051Sandreas.hansson@arm.com // anything that is merely forwarded pays for the forward latency and 73411051Sandreas.hansson@arm.com // the delay provided by the crossbar 73511051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 73611051Sandreas.hansson@arm.com 73711051Sandreas.hansson@arm.com // We use lookupLatency here because it is used to specify the latency 73811051Sandreas.hansson@arm.com // to access. 73911051Sandreas.hansson@arm.com Cycles lat = lookupLatency; 74011484Snikos.nikoleris@arm.com CacheBlk *blk = nullptr; 74111051Sandreas.hansson@arm.com bool satisfied = false; 74211051Sandreas.hansson@arm.com { 74311051Sandreas.hansson@arm.com PacketList writebacks; 74411051Sandreas.hansson@arm.com // Note that lat is passed by reference here. The function 74511051Sandreas.hansson@arm.com // access() calls accessBlock() which can modify lat value. 74611051Sandreas.hansson@arm.com satisfied = access(pkt, blk, lat, writebacks); 74711051Sandreas.hansson@arm.com 74811051Sandreas.hansson@arm.com // copy writebacks to write buffer here to ensure they logically 74911051Sandreas.hansson@arm.com // proceed anything happening below 75011051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 75111051Sandreas.hansson@arm.com } 75211051Sandreas.hansson@arm.com 75311051Sandreas.hansson@arm.com // Here we charge the headerDelay that takes into account the latencies 75411051Sandreas.hansson@arm.com // of the bus, if the packet comes from it. 75511051Sandreas.hansson@arm.com // The latency charged it is just lat that is the value of lookupLatency 75611051Sandreas.hansson@arm.com // modified by access() function, or if not just lookupLatency. 75711051Sandreas.hansson@arm.com // In case of a hit we are neglecting response latency. 75811051Sandreas.hansson@arm.com // In case of a miss we are neglecting forward latency. 75911051Sandreas.hansson@arm.com Tick request_time = clockEdge(lat) + pkt->headerDelay; 76011051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 76111051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 76211051Sandreas.hansson@arm.com 76311051Sandreas.hansson@arm.com // track time of availability of next prefetch, if any 76411051Sandreas.hansson@arm.com Tick next_pf_time = MaxTick; 76511051Sandreas.hansson@arm.com 76611051Sandreas.hansson@arm.com bool needsResponse = pkt->needsResponse(); 76711051Sandreas.hansson@arm.com 76811051Sandreas.hansson@arm.com if (satisfied) { 76911051Sandreas.hansson@arm.com // should never be satisfying an uncacheable access as we 77011051Sandreas.hansson@arm.com // flush and invalidate any existing block as part of the 77111051Sandreas.hansson@arm.com // lookup 77211051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 77311051Sandreas.hansson@arm.com 77411051Sandreas.hansson@arm.com // hit (for all other request types) 77511051Sandreas.hansson@arm.com 77611483Snikos.nikoleris@arm.com if (prefetcher && (prefetchOnAccess || 77711483Snikos.nikoleris@arm.com (blk && blk->wasPrefetched()))) { 77811051Sandreas.hansson@arm.com if (blk) 77911051Sandreas.hansson@arm.com blk->status &= ~BlkHWPrefetched; 78011051Sandreas.hansson@arm.com 78111051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 78212349Snikos.nikoleris@arm.com if (!pkt->cmd.isSWPrefetch()) { 78312349Snikos.nikoleris@arm.com assert(!pkt->req->isCacheMaintenance()); 78411051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 78512349Snikos.nikoleris@arm.com } 78611051Sandreas.hansson@arm.com } 78711051Sandreas.hansson@arm.com 78811051Sandreas.hansson@arm.com if (needsResponse) { 78911051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 79011051Sandreas.hansson@arm.com // @todo: Make someone pay for this 79111051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 79211051Sandreas.hansson@arm.com 79311051Sandreas.hansson@arm.com // In this case we are considering request_time that takes 79411051Sandreas.hansson@arm.com // into account the delay of the xbar, if any, and just 79511051Sandreas.hansson@arm.com // lat, neglecting responseLatency, modelling hit latency 79611051Sandreas.hansson@arm.com // just as lookupLatency or or the value of lat overriden 79711051Sandreas.hansson@arm.com // by access(), that calls accessBlock() function. 79811194Sali.jafri@arm.com cpuSidePort->schedTimingResp(pkt, request_time, true); 79911051Sandreas.hansson@arm.com } else { 80011744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__, 80111744Snikos.nikoleris@arm.com pkt->print()); 80211199Sandreas.hansson@arm.com 80311190Sandreas.hansson@arm.com // queue the packet for deletion, as the sending cache is 80411190Sandreas.hansson@arm.com // still relying on it; if the block is found in access(), 80511190Sandreas.hansson@arm.com // CleanEvict and Writeback messages will be deleted 80611190Sandreas.hansson@arm.com // here as well 80711190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 80811051Sandreas.hansson@arm.com } 80911051Sandreas.hansson@arm.com } else { 81011051Sandreas.hansson@arm.com // miss 81111051Sandreas.hansson@arm.com 81211892Snikos.nikoleris@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 81311051Sandreas.hansson@arm.com 81411051Sandreas.hansson@arm.com // ignore any existing MSHR if we are dealing with an 81511051Sandreas.hansson@arm.com // uncacheable request 81611051Sandreas.hansson@arm.com MSHR *mshr = pkt->req->isUncacheable() ? nullptr : 81711051Sandreas.hansson@arm.com mshrQueue.findMatch(blk_addr, pkt->isSecure()); 81811051Sandreas.hansson@arm.com 81911051Sandreas.hansson@arm.com // Software prefetch handling: 82011051Sandreas.hansson@arm.com // To keep the core from waiting on data it won't look at 82111051Sandreas.hansson@arm.com // anyway, send back a response with dummy data. Miss handling 82211051Sandreas.hansson@arm.com // will continue asynchronously. Unfortunately, the core will 82311051Sandreas.hansson@arm.com // insist upon freeing original Packet/Request, so we have to 82411051Sandreas.hansson@arm.com // create a new pair with a different lifecycle. Note that this 82511051Sandreas.hansson@arm.com // processing happens before any MSHR munging on the behalf of 82611051Sandreas.hansson@arm.com // this request because this new Request will be the one stored 82711051Sandreas.hansson@arm.com // into the MSHRs, not the original. 82811051Sandreas.hansson@arm.com if (pkt->cmd.isSWPrefetch()) { 82911051Sandreas.hansson@arm.com assert(needsResponse); 83011051Sandreas.hansson@arm.com assert(pkt->req->hasPaddr()); 83111051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 83211051Sandreas.hansson@arm.com 83311051Sandreas.hansson@arm.com // There's no reason to add a prefetch as an additional target 83411051Sandreas.hansson@arm.com // to an existing MSHR. If an outstanding request is already 83511051Sandreas.hansson@arm.com // in progress, there is nothing for the prefetch to do. 83611051Sandreas.hansson@arm.com // If this is the case, we don't even create a request at all. 83711051Sandreas.hansson@arm.com PacketPtr pf = nullptr; 83811051Sandreas.hansson@arm.com 83911051Sandreas.hansson@arm.com if (!mshr) { 84011051Sandreas.hansson@arm.com // copy the request and create a new SoftPFReq packet 84111051Sandreas.hansson@arm.com RequestPtr req = new Request(pkt->req->getPaddr(), 84211051Sandreas.hansson@arm.com pkt->req->getSize(), 84311051Sandreas.hansson@arm.com pkt->req->getFlags(), 84411051Sandreas.hansson@arm.com pkt->req->masterId()); 84511051Sandreas.hansson@arm.com pf = new Packet(req, pkt->cmd); 84611051Sandreas.hansson@arm.com pf->allocate(); 84711051Sandreas.hansson@arm.com assert(pf->getAddr() == pkt->getAddr()); 84811051Sandreas.hansson@arm.com assert(pf->getSize() == pkt->getSize()); 84911051Sandreas.hansson@arm.com } 85011051Sandreas.hansson@arm.com 85111051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 85211286Sandreas.hansson@arm.com 85311051Sandreas.hansson@arm.com // request_time is used here, taking into account lat and the delay 85411051Sandreas.hansson@arm.com // charged if the packet comes from the xbar. 85511194Sali.jafri@arm.com cpuSidePort->schedTimingResp(pkt, request_time, true); 85611051Sandreas.hansson@arm.com 85711051Sandreas.hansson@arm.com // If an outstanding request is in progress (we found an 85811051Sandreas.hansson@arm.com // MSHR) this is set to null 85911051Sandreas.hansson@arm.com pkt = pf; 86011051Sandreas.hansson@arm.com } 86111051Sandreas.hansson@arm.com 86211051Sandreas.hansson@arm.com if (mshr) { 86311051Sandreas.hansson@arm.com /// MSHR hit 86411051Sandreas.hansson@arm.com /// @note writebacks will be checked in getNextMSHR() 86511051Sandreas.hansson@arm.com /// for any conflicting requests to the same block 86611051Sandreas.hansson@arm.com 86711051Sandreas.hansson@arm.com //@todo remove hw_pf here 86811051Sandreas.hansson@arm.com 86911051Sandreas.hansson@arm.com // Coalesce unless it was a software prefetch (see above). 87011051Sandreas.hansson@arm.com if (pkt) { 87111199Sandreas.hansson@arm.com assert(!pkt->isWriteback()); 87211199Sandreas.hansson@arm.com // CleanEvicts corresponding to blocks which have 87311199Sandreas.hansson@arm.com // outstanding requests in MSHRs are simply sunk here 87411051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::CleanEvict) { 87511190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 87612349Snikos.nikoleris@arm.com } else if (pkt->cmd == MemCmd::WriteClean) { 87712349Snikos.nikoleris@arm.com // A WriteClean should never coalesce with any 87812349Snikos.nikoleris@arm.com // outstanding cache maintenance requests. 87912349Snikos.nikoleris@arm.com 88012349Snikos.nikoleris@arm.com // We use forward_time here because there is an 88112349Snikos.nikoleris@arm.com // uncached memory write, forwarded to WriteBuffer. 88212349Snikos.nikoleris@arm.com allocateWriteBuffer(pkt, forward_time); 88311051Sandreas.hansson@arm.com } else { 88411744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s coalescing MSHR for %s\n", __func__, 88511744Snikos.nikoleris@arm.com pkt->print()); 88611051Sandreas.hansson@arm.com 88711051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 88811051Sandreas.hansson@arm.com mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 88911051Sandreas.hansson@arm.com // We use forward_time here because it is the same 89011051Sandreas.hansson@arm.com // considering new targets. We have multiple 89111051Sandreas.hansson@arm.com // requests for the same address here. It 89211051Sandreas.hansson@arm.com // specifies the latency to allocate an internal 89311051Sandreas.hansson@arm.com // buffer and to schedule an event to the queued 89411051Sandreas.hansson@arm.com // port and also takes into account the additional 89511051Sandreas.hansson@arm.com // delay of the xbar. 89611197Sandreas.hansson@arm.com mshr->allocateTarget(pkt, forward_time, order++, 89711197Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 89811051Sandreas.hansson@arm.com if (mshr->getNumTargets() == numTarget) { 89911051Sandreas.hansson@arm.com noTargetMSHR = mshr; 90011051Sandreas.hansson@arm.com setBlocked(Blocked_NoTargets); 90111051Sandreas.hansson@arm.com // need to be careful with this... if this mshr isn't 90211051Sandreas.hansson@arm.com // ready yet (i.e. time > curTick()), we don't want to 90311051Sandreas.hansson@arm.com // move it ahead of mshrs that are ready 90411051Sandreas.hansson@arm.com // mshrQueue.moveToFront(mshr); 90511051Sandreas.hansson@arm.com } 90611051Sandreas.hansson@arm.com } 90711051Sandreas.hansson@arm.com // We should call the prefetcher reguardless if the request is 90811483Snikos.nikoleris@arm.com // satisfied or not, reguardless if the request is in the MSHR 90911483Snikos.nikoleris@arm.com // or not. The request could be a ReadReq hit, but still not 91011051Sandreas.hansson@arm.com // satisfied (potentially because of a prior write to the same 91111051Sandreas.hansson@arm.com // cache line. So, even when not satisfied, tehre is an MSHR 91211483Snikos.nikoleris@arm.com // already allocated for this, we need to let the prefetcher 91311483Snikos.nikoleris@arm.com // know about the request 91411051Sandreas.hansson@arm.com if (prefetcher) { 91511051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 91612349Snikos.nikoleris@arm.com if (!pkt->cmd.isSWPrefetch() && 91712349Snikos.nikoleris@arm.com !pkt->req->isCacheMaintenance()) 91811051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 91911051Sandreas.hansson@arm.com } 92011051Sandreas.hansson@arm.com } 92111051Sandreas.hansson@arm.com } else { 92211051Sandreas.hansson@arm.com // no MSHR 92311051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 92411051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 92511051Sandreas.hansson@arm.com mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++; 92611051Sandreas.hansson@arm.com } else { 92711051Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 92811051Sandreas.hansson@arm.com } 92911051Sandreas.hansson@arm.com 93012345Snikos.nikoleris@arm.com if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean || 93111051Sandreas.hansson@arm.com (pkt->req->isUncacheable() && pkt->isWrite())) { 93211051Sandreas.hansson@arm.com // We use forward_time here because there is an 93311051Sandreas.hansson@arm.com // uncached memory write, forwarded to WriteBuffer. 93411051Sandreas.hansson@arm.com allocateWriteBuffer(pkt, forward_time); 93511051Sandreas.hansson@arm.com } else { 93611051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 93711051Sandreas.hansson@arm.com // should have flushed and have no valid block 93811051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 93911051Sandreas.hansson@arm.com 94011051Sandreas.hansson@arm.com // If we have a write miss to a valid block, we 94111051Sandreas.hansson@arm.com // need to mark the block non-readable. Otherwise 94211051Sandreas.hansson@arm.com // if we allow reads while there's an outstanding 94311051Sandreas.hansson@arm.com // write miss, the read could return stale data 94411051Sandreas.hansson@arm.com // out of the cache block... a more aggressive 94511051Sandreas.hansson@arm.com // system could detect the overlap (if any) and 94611051Sandreas.hansson@arm.com // forward data out of the MSHRs, but we don't do 94711051Sandreas.hansson@arm.com // that yet. Note that we do need to leave the 94811051Sandreas.hansson@arm.com // block valid so that it stays in the cache, in 94911051Sandreas.hansson@arm.com // case we get an upgrade response (and hence no 95011051Sandreas.hansson@arm.com // new data) when the write miss completes. 95111051Sandreas.hansson@arm.com // As long as CPUs do proper store/load forwarding 95211051Sandreas.hansson@arm.com // internally, and have a sufficiently weak memory 95311051Sandreas.hansson@arm.com // model, this is probably unnecessary, but at some 95411051Sandreas.hansson@arm.com // point it must have seemed like we needed it... 95512349Snikos.nikoleris@arm.com assert((pkt->needsWritable() && !blk->isWritable()) || 95612349Snikos.nikoleris@arm.com pkt->req->isCacheMaintenance()); 95711051Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 95811051Sandreas.hansson@arm.com } 95911051Sandreas.hansson@arm.com // Here we are using forward_time, modelling the latency of 96011051Sandreas.hansson@arm.com // a miss (outbound) just as forwardLatency, neglecting the 96111051Sandreas.hansson@arm.com // lookupLatency component. 96211051Sandreas.hansson@arm.com allocateMissBuffer(pkt, forward_time); 96311051Sandreas.hansson@arm.com } 96411051Sandreas.hansson@arm.com 96511051Sandreas.hansson@arm.com if (prefetcher) { 96611051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 96712349Snikos.nikoleris@arm.com if (!pkt->cmd.isSWPrefetch() && 96812349Snikos.nikoleris@arm.com !pkt->req->isCacheMaintenance()) 96911051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 97011051Sandreas.hansson@arm.com } 97111051Sandreas.hansson@arm.com } 97211051Sandreas.hansson@arm.com } 97311051Sandreas.hansson@arm.com 97411051Sandreas.hansson@arm.com if (next_pf_time != MaxTick) 97511051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 97611051Sandreas.hansson@arm.com 97711051Sandreas.hansson@arm.com return true; 97811051Sandreas.hansson@arm.com} 97911051Sandreas.hansson@arm.com 98011051Sandreas.hansson@arm.comPacketPtr 98111452Sandreas.hansson@arm.comCache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, 98211452Sandreas.hansson@arm.com bool needsWritable) const 98311051Sandreas.hansson@arm.com{ 98411452Sandreas.hansson@arm.com // should never see evictions here 98511452Sandreas.hansson@arm.com assert(!cpu_pkt->isEviction()); 98611452Sandreas.hansson@arm.com 98711051Sandreas.hansson@arm.com bool blkValid = blk && blk->isValid(); 98811051Sandreas.hansson@arm.com 98911452Sandreas.hansson@arm.com if (cpu_pkt->req->isUncacheable() || 99011745Sandreas.hansson@arm.com (!blkValid && cpu_pkt->isUpgrade()) || 99112349Snikos.nikoleris@arm.com cpu_pkt->cmd == MemCmd::InvalidateReq || cpu_pkt->isClean()) { 99211452Sandreas.hansson@arm.com // uncacheable requests and upgrades from upper-level caches 99311452Sandreas.hansson@arm.com // that missed completely just go through as is 99411452Sandreas.hansson@arm.com return nullptr; 99511051Sandreas.hansson@arm.com } 99611051Sandreas.hansson@arm.com 99711051Sandreas.hansson@arm.com assert(cpu_pkt->needsResponse()); 99811051Sandreas.hansson@arm.com 99911051Sandreas.hansson@arm.com MemCmd cmd; 100011051Sandreas.hansson@arm.com // @TODO make useUpgrades a parameter. 100111051Sandreas.hansson@arm.com // Note that ownership protocols require upgrade, otherwise a 100211051Sandreas.hansson@arm.com // write miss on a shared owned block will generate a ReadExcl, 100311051Sandreas.hansson@arm.com // which will clobber the owned copy. 100411051Sandreas.hansson@arm.com const bool useUpgrades = true; 100511747Snikos.nikoleris@arm.com if (cpu_pkt->cmd == MemCmd::WriteLineReq) { 100611747Snikos.nikoleris@arm.com assert(!blkValid || !blk->isWritable()); 100711747Snikos.nikoleris@arm.com // forward as invalidate to all other caches, this gives us 100811747Snikos.nikoleris@arm.com // the line in Exclusive state, and invalidates all other 100911747Snikos.nikoleris@arm.com // copies 101011747Snikos.nikoleris@arm.com cmd = MemCmd::InvalidateReq; 101111747Snikos.nikoleris@arm.com } else if (blkValid && useUpgrades) { 101211284Sandreas.hansson@arm.com // only reason to be here is that blk is read only and we need 101311284Sandreas.hansson@arm.com // it to be writable 101411284Sandreas.hansson@arm.com assert(needsWritable); 101511051Sandreas.hansson@arm.com assert(!blk->isWritable()); 101611051Sandreas.hansson@arm.com cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq; 101711051Sandreas.hansson@arm.com } else if (cpu_pkt->cmd == MemCmd::SCUpgradeFailReq || 101811051Sandreas.hansson@arm.com cpu_pkt->cmd == MemCmd::StoreCondFailReq) { 101911051Sandreas.hansson@arm.com // Even though this SC will fail, we still need to send out the 102011051Sandreas.hansson@arm.com // request and get the data to supply it to other snoopers in the case 102111051Sandreas.hansson@arm.com // where the determination the StoreCond fails is delayed due to 102211051Sandreas.hansson@arm.com // all caches not being on the same local bus. 102311051Sandreas.hansson@arm.com cmd = MemCmd::SCUpgradeFailReq; 102411051Sandreas.hansson@arm.com } else { 102511051Sandreas.hansson@arm.com // block is invalid 102612425Snikos.nikoleris@arm.com 102712425Snikos.nikoleris@arm.com // If the request does not need a writable there are two cases 102812425Snikos.nikoleris@arm.com // where we need to ensure the response will not fetch the 102912425Snikos.nikoleris@arm.com // block in dirty state: 103012425Snikos.nikoleris@arm.com // * this cache is read only and it does not perform 103112425Snikos.nikoleris@arm.com // writebacks, 103212425Snikos.nikoleris@arm.com // * this cache is mostly exclusive and will not fill (since 103312425Snikos.nikoleris@arm.com // it does not fill it will have to writeback the dirty data 103412425Snikos.nikoleris@arm.com // immediately which generates uneccesary writebacks). 103512425Snikos.nikoleris@arm.com bool force_clean_rsp = isReadOnly || clusivity == Enums::mostly_excl; 103611284Sandreas.hansson@arm.com cmd = needsWritable ? MemCmd::ReadExReq : 103712425Snikos.nikoleris@arm.com (force_clean_rsp ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq); 103811051Sandreas.hansson@arm.com } 103911051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize); 104011051Sandreas.hansson@arm.com 104111284Sandreas.hansson@arm.com // if there are upstream caches that have already marked the 104211284Sandreas.hansson@arm.com // packet as having sharers (not passing writable), pass that info 104311284Sandreas.hansson@arm.com // downstream 104411602Sandreas.hansson@arm.com if (cpu_pkt->hasSharers() && !needsWritable) { 104511051Sandreas.hansson@arm.com // note that cpu_pkt may have spent a considerable time in the 104611051Sandreas.hansson@arm.com // MSHR queue and that the information could possibly be out 104711051Sandreas.hansson@arm.com // of date, however, there is no harm in conservatively 104811284Sandreas.hansson@arm.com // assuming the block has sharers 104911284Sandreas.hansson@arm.com pkt->setHasSharers(); 105011744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: passing hasSharers from %s to %s\n", 105111744Snikos.nikoleris@arm.com __func__, cpu_pkt->print(), pkt->print()); 105211051Sandreas.hansson@arm.com } 105311051Sandreas.hansson@arm.com 105411051Sandreas.hansson@arm.com // the packet should be block aligned 105511892Snikos.nikoleris@arm.com assert(pkt->getAddr() == pkt->getBlockAddr(blkSize)); 105611051Sandreas.hansson@arm.com 105711051Sandreas.hansson@arm.com pkt->allocate(); 105811744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: created %s from %s\n", __func__, pkt->print(), 105911744Snikos.nikoleris@arm.com cpu_pkt->print()); 106011051Sandreas.hansson@arm.com return pkt; 106111051Sandreas.hansson@arm.com} 106211051Sandreas.hansson@arm.com 106311051Sandreas.hansson@arm.com 106411051Sandreas.hansson@arm.comTick 106511051Sandreas.hansson@arm.comCache::recvAtomic(PacketPtr pkt) 106611051Sandreas.hansson@arm.com{ 106711051Sandreas.hansson@arm.com // We are in atomic mode so we pay just for lookupLatency here. 106811051Sandreas.hansson@arm.com Cycles lat = lookupLatency; 106911051Sandreas.hansson@arm.com 107011051Sandreas.hansson@arm.com // Forward the request if the system is in cache bypass mode. 107111051Sandreas.hansson@arm.com if (system->bypassCaches()) 107211051Sandreas.hansson@arm.com return ticksToCycles(memSidePort->sendAtomic(pkt)); 107311051Sandreas.hansson@arm.com 107411051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 107511051Sandreas.hansson@arm.com 107611333Sandreas.hansson@arm.com // follow the same flow as in recvTimingReq, and check if a cache 107711333Sandreas.hansson@arm.com // above us is responding 107812349Snikos.nikoleris@arm.com if (pkt->cacheResponding() && !pkt->isClean()) { 107912349Snikos.nikoleris@arm.com assert(!pkt->req->isCacheInvalidate()); 108011744Snikos.nikoleris@arm.com DPRINTF(Cache, "Cache above responding to %s: not responding\n", 108111744Snikos.nikoleris@arm.com pkt->print()); 108211333Sandreas.hansson@arm.com 108311333Sandreas.hansson@arm.com // if a cache is responding, and it had the line in Owned 108411333Sandreas.hansson@arm.com // rather than Modified state, we need to invalidate any 108511333Sandreas.hansson@arm.com // copies that are not on the same path to memory 108611334Sandreas.hansson@arm.com assert(pkt->needsWritable() && !pkt->responderHadWritable()); 108711334Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(pkt)); 108811051Sandreas.hansson@arm.com 108911051Sandreas.hansson@arm.com return lat * clockPeriod(); 109011051Sandreas.hansson@arm.com } 109111051Sandreas.hansson@arm.com 109211051Sandreas.hansson@arm.com // should assert here that there are no outstanding MSHRs or 109311051Sandreas.hansson@arm.com // writebacks... that would mean that someone used an atomic 109411051Sandreas.hansson@arm.com // access in timing mode 109511051Sandreas.hansson@arm.com 109611484Snikos.nikoleris@arm.com CacheBlk *blk = nullptr; 109711051Sandreas.hansson@arm.com PacketList writebacks; 109811051Sandreas.hansson@arm.com bool satisfied = access(pkt, blk, lat, writebacks); 109911051Sandreas.hansson@arm.com 110012349Snikos.nikoleris@arm.com if (pkt->isClean() && blk && blk->isDirty()) { 110112349Snikos.nikoleris@arm.com // A cache clean opearation is looking for a dirty 110212349Snikos.nikoleris@arm.com // block. If a dirty block is encountered a WriteClean 110312349Snikos.nikoleris@arm.com // will update any copies to the path to the memory 110412349Snikos.nikoleris@arm.com // until the point of reference. 110512349Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n", 110612349Snikos.nikoleris@arm.com __func__, pkt->print(), blk->print()); 110712351Snikos.nikoleris@arm.com PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id); 110812349Snikos.nikoleris@arm.com writebacks.push_back(wb_pkt); 110912349Snikos.nikoleris@arm.com pkt->setSatisfied(); 111012349Snikos.nikoleris@arm.com } 111112349Snikos.nikoleris@arm.com 111211051Sandreas.hansson@arm.com // handle writebacks resulting from the access here to ensure they 111311051Sandreas.hansson@arm.com // logically proceed anything happening below 111411130Sali.jafri@arm.com doWritebacksAtomic(writebacks); 111511051Sandreas.hansson@arm.com 111611051Sandreas.hansson@arm.com if (!satisfied) { 111711051Sandreas.hansson@arm.com // MISS 111811051Sandreas.hansson@arm.com 111911452Sandreas.hansson@arm.com // deal with the packets that go through the write path of 112012345Snikos.nikoleris@arm.com // the cache, i.e. any evictions and writes 112112345Snikos.nikoleris@arm.com if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean || 112211452Sandreas.hansson@arm.com (pkt->req->isUncacheable() && pkt->isWrite())) { 112311452Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(pkt)); 112411452Sandreas.hansson@arm.com return lat * clockPeriod(); 112511452Sandreas.hansson@arm.com } 112611452Sandreas.hansson@arm.com // only misses left 112711452Sandreas.hansson@arm.com 112811452Sandreas.hansson@arm.com PacketPtr bus_pkt = createMissPacket(pkt, blk, pkt->needsWritable()); 112911051Sandreas.hansson@arm.com 113011484Snikos.nikoleris@arm.com bool is_forward = (bus_pkt == nullptr); 113111051Sandreas.hansson@arm.com 113211051Sandreas.hansson@arm.com if (is_forward) { 113311051Sandreas.hansson@arm.com // just forwarding the same request to the next level 113411051Sandreas.hansson@arm.com // no local cache operation involved 113511051Sandreas.hansson@arm.com bus_pkt = pkt; 113611051Sandreas.hansson@arm.com } 113711051Sandreas.hansson@arm.com 113811744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Sending an atomic %s\n", __func__, 113911744Snikos.nikoleris@arm.com bus_pkt->print()); 114011051Sandreas.hansson@arm.com 114111051Sandreas.hansson@arm.com#if TRACING_ON 114211051Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 114311051Sandreas.hansson@arm.com#endif 114411051Sandreas.hansson@arm.com 114511051Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(bus_pkt)); 114611051Sandreas.hansson@arm.com 114711452Sandreas.hansson@arm.com bool is_invalidate = bus_pkt->isInvalidate(); 114811452Sandreas.hansson@arm.com 114911051Sandreas.hansson@arm.com // We are now dealing with the response handling 115011744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Receive response: %s in state %i\n", __func__, 115111744Snikos.nikoleris@arm.com bus_pkt->print(), old_state); 115211051Sandreas.hansson@arm.com 115311051Sandreas.hansson@arm.com // If packet was a forward, the response (if any) is already 115411051Sandreas.hansson@arm.com // in place in the bus_pkt == pkt structure, so we don't need 115511051Sandreas.hansson@arm.com // to do anything. Otherwise, use the separate bus_pkt to 115611051Sandreas.hansson@arm.com // generate response to pkt and then delete it. 115711051Sandreas.hansson@arm.com if (!is_forward) { 115811051Sandreas.hansson@arm.com if (pkt->needsResponse()) { 115911051Sandreas.hansson@arm.com assert(bus_pkt->isResponse()); 116011051Sandreas.hansson@arm.com if (bus_pkt->isError()) { 116111051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 116211051Sandreas.hansson@arm.com pkt->copyError(bus_pkt); 116311051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::WriteLineReq) { 116411051Sandreas.hansson@arm.com // note the use of pkt, not bus_pkt here. 116511051Sandreas.hansson@arm.com 116611051Sandreas.hansson@arm.com // write-line request to the cache that promoted 116711051Sandreas.hansson@arm.com // the write to a whole line 116811197Sandreas.hansson@arm.com blk = handleFill(pkt, blk, writebacks, 116911197Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 117011452Sandreas.hansson@arm.com assert(blk != NULL); 117111452Sandreas.hansson@arm.com is_invalidate = false; 117211601Sandreas.hansson@arm.com satisfyRequest(pkt, blk); 117311051Sandreas.hansson@arm.com } else if (bus_pkt->isRead() || 117411051Sandreas.hansson@arm.com bus_pkt->cmd == MemCmd::UpgradeResp) { 117511051Sandreas.hansson@arm.com // we're updating cache state to allow us to 117611051Sandreas.hansson@arm.com // satisfy the upstream request from the cache 117711197Sandreas.hansson@arm.com blk = handleFill(bus_pkt, blk, writebacks, 117811197Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 117911601Sandreas.hansson@arm.com satisfyRequest(pkt, blk); 118011601Sandreas.hansson@arm.com maintainClusivity(pkt->fromCache(), blk); 118111051Sandreas.hansson@arm.com } else { 118211051Sandreas.hansson@arm.com // we're satisfying the upstream request without 118311051Sandreas.hansson@arm.com // modifying cache state, e.g., a write-through 118411051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 118511051Sandreas.hansson@arm.com } 118611051Sandreas.hansson@arm.com } 118711051Sandreas.hansson@arm.com delete bus_pkt; 118811051Sandreas.hansson@arm.com } 118911452Sandreas.hansson@arm.com 119011452Sandreas.hansson@arm.com if (is_invalidate && blk && blk->isValid()) { 119111452Sandreas.hansson@arm.com invalidateBlock(blk); 119211452Sandreas.hansson@arm.com } 119311051Sandreas.hansson@arm.com } 119411051Sandreas.hansson@arm.com 119511051Sandreas.hansson@arm.com // Note that we don't invoke the prefetcher at all in atomic mode. 119611051Sandreas.hansson@arm.com // It's not clear how to do it properly, particularly for 119711051Sandreas.hansson@arm.com // prefetchers that aggressively generate prefetch candidates and 119811051Sandreas.hansson@arm.com // rely on bandwidth contention to throttle them; these will tend 119911051Sandreas.hansson@arm.com // to pollute the cache in atomic mode since there is no bandwidth 120011051Sandreas.hansson@arm.com // contention. If we ever do want to enable prefetching in atomic 120111051Sandreas.hansson@arm.com // mode, though, this is the place to do it... see timingAccess() 120211051Sandreas.hansson@arm.com // for an example (though we'd want to issue the prefetch(es) 120311051Sandreas.hansson@arm.com // immediately rather than calling requestMemSideBus() as we do 120411051Sandreas.hansson@arm.com // there). 120511051Sandreas.hansson@arm.com 120611197Sandreas.hansson@arm.com // do any writebacks resulting from the response handling 120711130Sali.jafri@arm.com doWritebacksAtomic(writebacks); 120811051Sandreas.hansson@arm.com 120911197Sandreas.hansson@arm.com // if we used temp block, check to see if its valid and if so 121011197Sandreas.hansson@arm.com // clear it out, but only do so after the call to recvAtomic is 121111197Sandreas.hansson@arm.com // finished so that any downstream observers (such as a snoop 121211197Sandreas.hansson@arm.com // filter), first see the fill, and only then see the eviction 121311197Sandreas.hansson@arm.com if (blk == tempBlock && tempBlock->isValid()) { 121411197Sandreas.hansson@arm.com // the atomic CPU calls recvAtomic for fetch and load/store 121511197Sandreas.hansson@arm.com // sequentuially, and we may already have a tempBlock 121611197Sandreas.hansson@arm.com // writeback from the fetch that we have not yet sent 121711197Sandreas.hansson@arm.com if (tempBlockWriteback) { 121811197Sandreas.hansson@arm.com // if that is the case, write the prevoius one back, and 121911197Sandreas.hansson@arm.com // do not schedule any new event 122011197Sandreas.hansson@arm.com writebackTempBlockAtomic(); 122111197Sandreas.hansson@arm.com } else { 122211197Sandreas.hansson@arm.com // the writeback/clean eviction happens after the call to 122311197Sandreas.hansson@arm.com // recvAtomic has finished (but before any successive 122411197Sandreas.hansson@arm.com // calls), so that the response handling from the fill is 122511197Sandreas.hansson@arm.com // allowed to happen first 122611197Sandreas.hansson@arm.com schedule(writebackTempBlockAtomicEvent, curTick()); 122711197Sandreas.hansson@arm.com } 122811197Sandreas.hansson@arm.com 122911199Sandreas.hansson@arm.com tempBlockWriteback = (blk->isDirty() || writebackClean) ? 123011199Sandreas.hansson@arm.com writebackBlk(blk) : cleanEvictBlk(blk); 123111867Snikos.nikoleris@arm.com invalidateBlock(blk); 123211197Sandreas.hansson@arm.com } 123311197Sandreas.hansson@arm.com 123411051Sandreas.hansson@arm.com if (pkt->needsResponse()) { 123511051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 123611051Sandreas.hansson@arm.com } 123711051Sandreas.hansson@arm.com 123811051Sandreas.hansson@arm.com return lat * clockPeriod(); 123911051Sandreas.hansson@arm.com} 124011051Sandreas.hansson@arm.com 124111051Sandreas.hansson@arm.com 124211051Sandreas.hansson@arm.comvoid 124311051Sandreas.hansson@arm.comCache::functionalAccess(PacketPtr pkt, bool fromCpuSide) 124411051Sandreas.hansson@arm.com{ 124511051Sandreas.hansson@arm.com if (system->bypassCaches()) { 124611051Sandreas.hansson@arm.com // Packets from the memory side are snoop request and 124711051Sandreas.hansson@arm.com // shouldn't happen in bypass mode. 124811051Sandreas.hansson@arm.com assert(fromCpuSide); 124911051Sandreas.hansson@arm.com 125011051Sandreas.hansson@arm.com // The cache should be flushed if we are in cache bypass mode, 125111051Sandreas.hansson@arm.com // so we don't need to check if we need to update anything. 125211051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 125311051Sandreas.hansson@arm.com return; 125411051Sandreas.hansson@arm.com } 125511051Sandreas.hansson@arm.com 125611892Snikos.nikoleris@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 125711051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 125811051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 125911051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 126011051Sandreas.hansson@arm.com 126111051Sandreas.hansson@arm.com pkt->pushLabel(name()); 126211051Sandreas.hansson@arm.com 126311051Sandreas.hansson@arm.com CacheBlkPrintWrapper cbpw(blk); 126411051Sandreas.hansson@arm.com 126511051Sandreas.hansson@arm.com // Note that just because an L2/L3 has valid data doesn't mean an 126611051Sandreas.hansson@arm.com // L1 doesn't have a more up-to-date modified copy that still 126711051Sandreas.hansson@arm.com // needs to be found. As a result we always update the request if 126811051Sandreas.hansson@arm.com // we have it, but only declare it satisfied if we are the owner. 126911051Sandreas.hansson@arm.com 127011051Sandreas.hansson@arm.com // see if we have data at all (owned or otherwise) 127111051Sandreas.hansson@arm.com bool have_data = blk && blk->isValid() 127211051Sandreas.hansson@arm.com && pkt->checkFunctional(&cbpw, blk_addr, is_secure, blkSize, 127311051Sandreas.hansson@arm.com blk->data); 127411051Sandreas.hansson@arm.com 127511284Sandreas.hansson@arm.com // data we have is dirty if marked as such or if we have an 127611284Sandreas.hansson@arm.com // in-service MSHR that is pending a modified line 127711051Sandreas.hansson@arm.com bool have_dirty = 127811051Sandreas.hansson@arm.com have_data && (blk->isDirty() || 127911284Sandreas.hansson@arm.com (mshr && mshr->inService && mshr->isPendingModified())); 128011051Sandreas.hansson@arm.com 128111051Sandreas.hansson@arm.com bool done = have_dirty 128211051Sandreas.hansson@arm.com || cpuSidePort->checkFunctional(pkt) 128311051Sandreas.hansson@arm.com || mshrQueue.checkFunctional(pkt, blk_addr) 128411051Sandreas.hansson@arm.com || writeBuffer.checkFunctional(pkt, blk_addr) 128511051Sandreas.hansson@arm.com || memSidePort->checkFunctional(pkt); 128611051Sandreas.hansson@arm.com 128711744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: %s %s%s%s\n", __func__, pkt->print(), 128811051Sandreas.hansson@arm.com (blk && blk->isValid()) ? "valid " : "", 128911051Sandreas.hansson@arm.com have_data ? "data " : "", done ? "done " : ""); 129011051Sandreas.hansson@arm.com 129111051Sandreas.hansson@arm.com // We're leaving the cache, so pop cache->name() label 129211051Sandreas.hansson@arm.com pkt->popLabel(); 129311051Sandreas.hansson@arm.com 129411051Sandreas.hansson@arm.com if (done) { 129511051Sandreas.hansson@arm.com pkt->makeResponse(); 129611051Sandreas.hansson@arm.com } else { 129711051Sandreas.hansson@arm.com // if it came as a request from the CPU side then make sure it 129811051Sandreas.hansson@arm.com // continues towards the memory side 129911051Sandreas.hansson@arm.com if (fromCpuSide) { 130011051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 130111485Snikos.nikoleris@arm.com } else if (cpuSidePort->isSnooping()) { 130211051Sandreas.hansson@arm.com // if it came from the memory side, it must be a snoop request 130311051Sandreas.hansson@arm.com // and we should only forward it if we are forwarding snoops 130411051Sandreas.hansson@arm.com cpuSidePort->sendFunctionalSnoop(pkt); 130511051Sandreas.hansson@arm.com } 130611051Sandreas.hansson@arm.com } 130711051Sandreas.hansson@arm.com} 130811051Sandreas.hansson@arm.com 130911051Sandreas.hansson@arm.com 131011051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 131111051Sandreas.hansson@arm.com// 131211051Sandreas.hansson@arm.com// Response handling: responses from the memory side 131311051Sandreas.hansson@arm.com// 131411051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 131511051Sandreas.hansson@arm.com 131611051Sandreas.hansson@arm.com 131711051Sandreas.hansson@arm.comvoid 131811375Sandreas.hansson@arm.comCache::handleUncacheableWriteResp(PacketPtr pkt) 131911375Sandreas.hansson@arm.com{ 132011375Sandreas.hansson@arm.com Tick completion_time = clockEdge(responseLatency) + 132111375Sandreas.hansson@arm.com pkt->headerDelay + pkt->payloadDelay; 132211375Sandreas.hansson@arm.com 132311453Sandreas.hansson@arm.com // Reset the bus additional time as it is now accounted for 132411453Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 132511375Sandreas.hansson@arm.com 132611453Sandreas.hansson@arm.com cpuSidePort->schedTimingResp(pkt, completion_time, true); 132711375Sandreas.hansson@arm.com} 132811375Sandreas.hansson@arm.com 132911375Sandreas.hansson@arm.comvoid 133011051Sandreas.hansson@arm.comCache::recvTimingResp(PacketPtr pkt) 133111051Sandreas.hansson@arm.com{ 133211051Sandreas.hansson@arm.com assert(pkt->isResponse()); 133311051Sandreas.hansson@arm.com 133411051Sandreas.hansson@arm.com // all header delay should be paid for by the crossbar, unless 133511051Sandreas.hansson@arm.com // this is a prefetch response from above 133611051Sandreas.hansson@arm.com panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp, 133711051Sandreas.hansson@arm.com "%s saw a non-zero packet delay\n", name()); 133811051Sandreas.hansson@arm.com 133911051Sandreas.hansson@arm.com bool is_error = pkt->isError(); 134011051Sandreas.hansson@arm.com 134111051Sandreas.hansson@arm.com if (is_error) { 134211744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Cache received %s with error\n", __func__, 134311744Snikos.nikoleris@arm.com pkt->print()); 134411051Sandreas.hansson@arm.com } 134511051Sandreas.hansson@arm.com 134611744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Handling response %s\n", __func__, 134711744Snikos.nikoleris@arm.com pkt->print()); 134811051Sandreas.hansson@arm.com 134911375Sandreas.hansson@arm.com // if this is a write, we should be looking at an uncacheable 135011375Sandreas.hansson@arm.com // write 135111375Sandreas.hansson@arm.com if (pkt->isWrite()) { 135211375Sandreas.hansson@arm.com assert(pkt->req->isUncacheable()); 135311375Sandreas.hansson@arm.com handleUncacheableWriteResp(pkt); 135411375Sandreas.hansson@arm.com return; 135511375Sandreas.hansson@arm.com } 135611375Sandreas.hansson@arm.com 135711375Sandreas.hansson@arm.com // we have dealt with any (uncacheable) writes above, from here on 135811375Sandreas.hansson@arm.com // we know we are dealing with an MSHR due to a miss or a prefetch 135911453Sandreas.hansson@arm.com MSHR *mshr = dynamic_cast<MSHR*>(pkt->popSenderState()); 136011375Sandreas.hansson@arm.com assert(mshr); 136111051Sandreas.hansson@arm.com 136211051Sandreas.hansson@arm.com if (mshr == noTargetMSHR) { 136311051Sandreas.hansson@arm.com // we always clear at least one target 136411051Sandreas.hansson@arm.com clearBlocked(Blocked_NoTargets); 136511484Snikos.nikoleris@arm.com noTargetMSHR = nullptr; 136611051Sandreas.hansson@arm.com } 136711051Sandreas.hansson@arm.com 136811051Sandreas.hansson@arm.com // Initial target is used just for stats 136911051Sandreas.hansson@arm.com MSHR::Target *initial_tgt = mshr->getTarget(); 137011051Sandreas.hansson@arm.com int stats_cmd_idx = initial_tgt->pkt->cmdToIndex(); 137111051Sandreas.hansson@arm.com Tick miss_latency = curTick() - initial_tgt->recvTime; 137211051Sandreas.hansson@arm.com 137311051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 137411051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 137511051Sandreas.hansson@arm.com mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] += 137611051Sandreas.hansson@arm.com miss_latency; 137711051Sandreas.hansson@arm.com } else { 137811051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 137911051Sandreas.hansson@arm.com mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] += 138011051Sandreas.hansson@arm.com miss_latency; 138111051Sandreas.hansson@arm.com } 138211051Sandreas.hansson@arm.com 138311375Sandreas.hansson@arm.com bool wasFull = mshrQueue.isFull(); 138411375Sandreas.hansson@arm.com 138511375Sandreas.hansson@arm.com PacketList writebacks; 138611375Sandreas.hansson@arm.com 138711375Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 138811375Sandreas.hansson@arm.com 138912348Snikos.nikoleris@arm.com bool is_fill = !mshr->isForward && 139012348Snikos.nikoleris@arm.com (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp); 139112348Snikos.nikoleris@arm.com 139212348Snikos.nikoleris@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 139312348Snikos.nikoleris@arm.com const bool valid_blk = blk && blk->isValid(); 139412348Snikos.nikoleris@arm.com // If the response indicates that there are no sharers and we 139512348Snikos.nikoleris@arm.com // either had the block already or the response is filling we can 139612348Snikos.nikoleris@arm.com // promote our copy to writable 139712349Snikos.nikoleris@arm.com if (!pkt->hasSharers() && 139812349Snikos.nikoleris@arm.com (is_fill || (valid_blk && !pkt->req->isCacheInvalidate()))) { 139911284Sandreas.hansson@arm.com mshr->promoteWritable(); 140011177Sandreas.hansson@arm.com } 140111177Sandreas.hansson@arm.com 140211051Sandreas.hansson@arm.com if (is_fill && !is_error) { 140311051Sandreas.hansson@arm.com DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n", 140411051Sandreas.hansson@arm.com pkt->getAddr()); 140511051Sandreas.hansson@arm.com 140611741Snikos.nikoleris@arm.com blk = handleFill(pkt, blk, writebacks, mshr->allocOnFill()); 140711484Snikos.nikoleris@arm.com assert(blk != nullptr); 140811051Sandreas.hansson@arm.com } 140911051Sandreas.hansson@arm.com 141011051Sandreas.hansson@arm.com // allow invalidation responses originating from write-line 141111051Sandreas.hansson@arm.com // requests to be discarded 141211136Sandreas.hansson@arm.com bool is_invalidate = pkt->isInvalidate(); 141311051Sandreas.hansson@arm.com 141412349Snikos.nikoleris@arm.com // The block was marked as not readable while there was a pending 141512349Snikos.nikoleris@arm.com // cache maintenance operation, restore its flag. 141612349Snikos.nikoleris@arm.com if (pkt->isClean() && !is_invalidate && valid_blk) { 141712349Snikos.nikoleris@arm.com blk->status |= BlkReadable; 141812349Snikos.nikoleris@arm.com } 141912349Snikos.nikoleris@arm.com 142011051Sandreas.hansson@arm.com // First offset for critical word first calculations 142111051Sandreas.hansson@arm.com int initial_offset = initial_tgt->pkt->getOffset(blkSize); 142211051Sandreas.hansson@arm.com 142311601Sandreas.hansson@arm.com bool from_cache = false; 142411742Snikos.nikoleris@arm.com MSHR::TargetList targets = mshr->extractServiceableTargets(pkt); 142511742Snikos.nikoleris@arm.com for (auto &target: targets) { 142611742Snikos.nikoleris@arm.com Packet *tgt_pkt = target.pkt; 142711742Snikos.nikoleris@arm.com switch (target.source) { 142811051Sandreas.hansson@arm.com case MSHR::Target::FromCPU: 142911051Sandreas.hansson@arm.com Tick completion_time; 143011051Sandreas.hansson@arm.com // Here we charge on completion_time the delay of the xbar if the 143111051Sandreas.hansson@arm.com // packet comes from it, charged on headerDelay. 143211051Sandreas.hansson@arm.com completion_time = pkt->headerDelay; 143311051Sandreas.hansson@arm.com 143411051Sandreas.hansson@arm.com // Software prefetch handling for cache closest to core 143511051Sandreas.hansson@arm.com if (tgt_pkt->cmd.isSWPrefetch()) { 143611483Snikos.nikoleris@arm.com // a software prefetch would have already been ack'd 143711483Snikos.nikoleris@arm.com // immediately with dummy data so the core would be able to 143811483Snikos.nikoleris@arm.com // retire it. This request completes right here, so we 143911483Snikos.nikoleris@arm.com // deallocate it. 144011051Sandreas.hansson@arm.com delete tgt_pkt->req; 144111051Sandreas.hansson@arm.com delete tgt_pkt; 144211051Sandreas.hansson@arm.com break; // skip response 144311051Sandreas.hansson@arm.com } 144411051Sandreas.hansson@arm.com 144511601Sandreas.hansson@arm.com // keep track of whether we have responded to another 144611601Sandreas.hansson@arm.com // cache 144711601Sandreas.hansson@arm.com from_cache = from_cache || tgt_pkt->fromCache(); 144811601Sandreas.hansson@arm.com 144911051Sandreas.hansson@arm.com // unlike the other packet flows, where data is found in other 145011051Sandreas.hansson@arm.com // caches or memory and brought back, write-line requests always 145111051Sandreas.hansson@arm.com // have the data right away, so the above check for "is fill?" 145211051Sandreas.hansson@arm.com // cannot actually be determined until examining the stored MSHR 145311051Sandreas.hansson@arm.com // state. We "catch up" with that logic here, which is duplicated 145411051Sandreas.hansson@arm.com // from above. 145511051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::WriteLineReq) { 145611051Sandreas.hansson@arm.com assert(!is_error); 145711284Sandreas.hansson@arm.com // we got the block in a writable state, so promote 145811284Sandreas.hansson@arm.com // any deferred targets if possible 145911284Sandreas.hansson@arm.com mshr->promoteWritable(); 146011051Sandreas.hansson@arm.com // NB: we use the original packet here and not the response! 146111741Snikos.nikoleris@arm.com blk = handleFill(tgt_pkt, blk, writebacks, 146211742Snikos.nikoleris@arm.com targets.allocOnFill); 146311484Snikos.nikoleris@arm.com assert(blk != nullptr); 146411051Sandreas.hansson@arm.com 146511051Sandreas.hansson@arm.com // treat as a fill, and discard the invalidation 146611051Sandreas.hansson@arm.com // response 146711051Sandreas.hansson@arm.com is_fill = true; 146811136Sandreas.hansson@arm.com is_invalidate = false; 146911051Sandreas.hansson@arm.com } 147011051Sandreas.hansson@arm.com 147111051Sandreas.hansson@arm.com if (is_fill) { 147211601Sandreas.hansson@arm.com satisfyRequest(tgt_pkt, blk, true, mshr->hasPostDowngrade()); 147311051Sandreas.hansson@arm.com 147411051Sandreas.hansson@arm.com // How many bytes past the first request is this one 147511051Sandreas.hansson@arm.com int transfer_offset = 147611051Sandreas.hansson@arm.com tgt_pkt->getOffset(blkSize) - initial_offset; 147711051Sandreas.hansson@arm.com if (transfer_offset < 0) { 147811051Sandreas.hansson@arm.com transfer_offset += blkSize; 147911051Sandreas.hansson@arm.com } 148011051Sandreas.hansson@arm.com 148111051Sandreas.hansson@arm.com // If not critical word (offset) return payloadDelay. 148211051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 148311051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 148411051Sandreas.hansson@arm.com // the core. 148511051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 148611051Sandreas.hansson@arm.com (transfer_offset ? pkt->payloadDelay : 0); 148711051Sandreas.hansson@arm.com 148811051Sandreas.hansson@arm.com assert(!tgt_pkt->req->isUncacheable()); 148911051Sandreas.hansson@arm.com 149011051Sandreas.hansson@arm.com assert(tgt_pkt->req->masterId() < system->maxMasters()); 149111051Sandreas.hansson@arm.com missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] += 149211742Snikos.nikoleris@arm.com completion_time - target.recvTime; 149311051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::UpgradeFailResp) { 149411051Sandreas.hansson@arm.com // failed StoreCond upgrade 149511051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::StoreCondReq || 149611051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::StoreCondFailReq || 149711051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::SCUpgradeFailReq); 149811051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 149911051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 150011051Sandreas.hansson@arm.com // the core. 150111051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 150211051Sandreas.hansson@arm.com pkt->payloadDelay; 150311051Sandreas.hansson@arm.com tgt_pkt->req->setExtraData(0); 150411051Sandreas.hansson@arm.com } else { 150511750Snikos.nikoleris@arm.com // We are about to send a response to a cache above 150611750Snikos.nikoleris@arm.com // that asked for an invalidation; we need to 150711750Snikos.nikoleris@arm.com // invalidate our copy immediately as the most 150811750Snikos.nikoleris@arm.com // up-to-date copy of the block will now be in the 150911750Snikos.nikoleris@arm.com // cache above. It will also prevent this cache from 151011750Snikos.nikoleris@arm.com // responding (if the block was previously dirty) to 151111750Snikos.nikoleris@arm.com // snoops as they should snoop the caches above where 151211750Snikos.nikoleris@arm.com // they will get the response from. 151311750Snikos.nikoleris@arm.com if (is_invalidate && blk && blk->isValid()) { 151411750Snikos.nikoleris@arm.com invalidateBlock(blk); 151511750Snikos.nikoleris@arm.com } 151611051Sandreas.hansson@arm.com // not a cache fill, just forwarding response 151711051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 151811051Sandreas.hansson@arm.com // from lower level cahces/memory to the core. 151911051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 152011051Sandreas.hansson@arm.com pkt->payloadDelay; 152111051Sandreas.hansson@arm.com if (pkt->isRead() && !is_error) { 152211051Sandreas.hansson@arm.com // sanity check 152311051Sandreas.hansson@arm.com assert(pkt->getAddr() == tgt_pkt->getAddr()); 152411051Sandreas.hansson@arm.com assert(pkt->getSize() >= tgt_pkt->getSize()); 152511051Sandreas.hansson@arm.com 152611051Sandreas.hansson@arm.com tgt_pkt->setData(pkt->getConstPtr<uint8_t>()); 152711051Sandreas.hansson@arm.com } 152811051Sandreas.hansson@arm.com } 152911051Sandreas.hansson@arm.com tgt_pkt->makeTimingResponse(); 153011051Sandreas.hansson@arm.com // if this packet is an error copy that to the new packet 153111051Sandreas.hansson@arm.com if (is_error) 153211051Sandreas.hansson@arm.com tgt_pkt->copyError(pkt); 153311051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::ReadResp && 153411136Sandreas.hansson@arm.com (is_invalidate || mshr->hasPostInvalidate())) { 153511051Sandreas.hansson@arm.com // If intermediate cache got ReadRespWithInvalidate, 153611051Sandreas.hansson@arm.com // propagate that. Response should not have 153711051Sandreas.hansson@arm.com // isInvalidate() set otherwise. 153811051Sandreas.hansson@arm.com tgt_pkt->cmd = MemCmd::ReadRespWithInvalidate; 153911744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: updated cmd to %s\n", __func__, 154011744Snikos.nikoleris@arm.com tgt_pkt->print()); 154111051Sandreas.hansson@arm.com } 154211051Sandreas.hansson@arm.com // Reset the bus additional time as it is now accounted for 154311051Sandreas.hansson@arm.com tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0; 154411194Sali.jafri@arm.com cpuSidePort->schedTimingResp(tgt_pkt, completion_time, true); 154511051Sandreas.hansson@arm.com break; 154611051Sandreas.hansson@arm.com 154711051Sandreas.hansson@arm.com case MSHR::Target::FromPrefetcher: 154811051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::HardPFReq); 154911051Sandreas.hansson@arm.com if (blk) 155011051Sandreas.hansson@arm.com blk->status |= BlkHWPrefetched; 155111051Sandreas.hansson@arm.com delete tgt_pkt->req; 155211051Sandreas.hansson@arm.com delete tgt_pkt; 155311051Sandreas.hansson@arm.com break; 155411051Sandreas.hansson@arm.com 155511051Sandreas.hansson@arm.com case MSHR::Target::FromSnoop: 155611051Sandreas.hansson@arm.com // I don't believe that a snoop can be in an error state 155711051Sandreas.hansson@arm.com assert(!is_error); 155811051Sandreas.hansson@arm.com // response to snoop request 155911051Sandreas.hansson@arm.com DPRINTF(Cache, "processing deferred snoop...\n"); 156011749Snikos.nikoleris@arm.com // If the response is invalidating, a snooping target can 156111749Snikos.nikoleris@arm.com // be satisfied if it is also invalidating. If the reponse is, not 156212349Snikos.nikoleris@arm.com // only invalidating, but more specifically an InvalidateResp and 156312349Snikos.nikoleris@arm.com // the MSHR was created due to an InvalidateReq then a cache above 156412349Snikos.nikoleris@arm.com // is waiting to satisfy a WriteLineReq. In this case even an 156511749Snikos.nikoleris@arm.com // non-invalidating snoop is added as a target here since this is 156611749Snikos.nikoleris@arm.com // the ordering point. When the InvalidateResp reaches this cache, 156711749Snikos.nikoleris@arm.com // the snooping target will snoop further the cache above with the 156811749Snikos.nikoleris@arm.com // WriteLineReq. 156912349Snikos.nikoleris@arm.com assert(!is_invalidate || pkt->cmd == MemCmd::InvalidateResp || 157012349Snikos.nikoleris@arm.com pkt->req->isCacheMaintenance() || 157112349Snikos.nikoleris@arm.com mshr->hasPostInvalidate()); 157211051Sandreas.hansson@arm.com handleSnoop(tgt_pkt, blk, true, true, mshr->hasPostInvalidate()); 157311051Sandreas.hansson@arm.com break; 157411051Sandreas.hansson@arm.com 157511051Sandreas.hansson@arm.com default: 157611742Snikos.nikoleris@arm.com panic("Illegal target->source enum %d\n", target.source); 157711051Sandreas.hansson@arm.com } 157811051Sandreas.hansson@arm.com } 157911051Sandreas.hansson@arm.com 158011601Sandreas.hansson@arm.com maintainClusivity(from_cache, blk); 158111601Sandreas.hansson@arm.com 158211051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 158311051Sandreas.hansson@arm.com // an invalidate response stemming from a write line request 158411051Sandreas.hansson@arm.com // should not invalidate the block, so check if the 158511051Sandreas.hansson@arm.com // invalidation should be discarded 158611136Sandreas.hansson@arm.com if (is_invalidate || mshr->hasPostInvalidate()) { 158711197Sandreas.hansson@arm.com invalidateBlock(blk); 158811051Sandreas.hansson@arm.com } else if (mshr->hasPostDowngrade()) { 158911051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 159011051Sandreas.hansson@arm.com } 159111051Sandreas.hansson@arm.com } 159211051Sandreas.hansson@arm.com 159311051Sandreas.hansson@arm.com if (mshr->promoteDeferredTargets()) { 159411051Sandreas.hansson@arm.com // avoid later read getting stale data while write miss is 159511051Sandreas.hansson@arm.com // outstanding.. see comment in timingAccess() 159611051Sandreas.hansson@arm.com if (blk) { 159711051Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 159811051Sandreas.hansson@arm.com } 159911375Sandreas.hansson@arm.com mshrQueue.markPending(mshr); 160011051Sandreas.hansson@arm.com schedMemSideSendEvent(clockEdge() + pkt->payloadDelay); 160111051Sandreas.hansson@arm.com } else { 160211375Sandreas.hansson@arm.com mshrQueue.deallocate(mshr); 160311375Sandreas.hansson@arm.com if (wasFull && !mshrQueue.isFull()) { 160411375Sandreas.hansson@arm.com clearBlocked(Blocked_NoMSHRs); 160511051Sandreas.hansson@arm.com } 160611051Sandreas.hansson@arm.com 160711051Sandreas.hansson@arm.com // Request the bus for a prefetch if this deallocation freed enough 160811051Sandreas.hansson@arm.com // MSHRs for a prefetch to take place 160911375Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 161011051Sandreas.hansson@arm.com Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(), 161111051Sandreas.hansson@arm.com clockEdge()); 161211051Sandreas.hansson@arm.com if (next_pf_time != MaxTick) 161311051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 161411051Sandreas.hansson@arm.com } 161511051Sandreas.hansson@arm.com } 161611051Sandreas.hansson@arm.com // reset the xbar additional timinig as it is now accounted for 161711051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 161811051Sandreas.hansson@arm.com 161911051Sandreas.hansson@arm.com // copy writebacks to write buffer 162011051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 162111051Sandreas.hansson@arm.com 162211051Sandreas.hansson@arm.com // if we used temp block, check to see if its valid and then clear it out 162311051Sandreas.hansson@arm.com if (blk == tempBlock && tempBlock->isValid()) { 162411051Sandreas.hansson@arm.com // We use forwardLatency here because we are copying 162511051Sandreas.hansson@arm.com // Writebacks/CleanEvicts to write buffer. It specifies the latency to 162611051Sandreas.hansson@arm.com // allocate an internal buffer and to schedule an event to the 162711051Sandreas.hansson@arm.com // queued port. 162811199Sandreas.hansson@arm.com if (blk->isDirty() || writebackClean) { 162911051Sandreas.hansson@arm.com PacketPtr wbPkt = writebackBlk(blk); 163011051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 163111051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag if cached above. 163211051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) 163311051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 163411051Sandreas.hansson@arm.com } else { 163511051Sandreas.hansson@arm.com PacketPtr wcPkt = cleanEvictBlk(blk); 163611051Sandreas.hansson@arm.com // Check to see if block is cached above. If not allocate 163711051Sandreas.hansson@arm.com // write buffer 163811051Sandreas.hansson@arm.com if (isCachedAbove(wcPkt)) 163911051Sandreas.hansson@arm.com delete wcPkt; 164011051Sandreas.hansson@arm.com else 164111051Sandreas.hansson@arm.com allocateWriteBuffer(wcPkt, forward_time); 164211051Sandreas.hansson@arm.com } 164311867Snikos.nikoleris@arm.com invalidateBlock(blk); 164411051Sandreas.hansson@arm.com } 164511051Sandreas.hansson@arm.com 164611744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: Leaving with %s\n", __func__, pkt->print()); 164711051Sandreas.hansson@arm.com delete pkt; 164811051Sandreas.hansson@arm.com} 164911051Sandreas.hansson@arm.com 165011051Sandreas.hansson@arm.comPacketPtr 165111051Sandreas.hansson@arm.comCache::writebackBlk(CacheBlk *blk) 165211051Sandreas.hansson@arm.com{ 165311199Sandreas.hansson@arm.com chatty_assert(!isReadOnly || writebackClean, 165411199Sandreas.hansson@arm.com "Writeback from read-only cache"); 165511199Sandreas.hansson@arm.com assert(blk && blk->isValid() && (blk->isDirty() || writebackClean)); 165611051Sandreas.hansson@arm.com 165711051Sandreas.hansson@arm.com writebacks[Request::wbMasterId]++; 165811051Sandreas.hansson@arm.com 165911199Sandreas.hansson@arm.com Request *req = new Request(tags->regenerateBlkAddr(blk->tag, blk->set), 166011199Sandreas.hansson@arm.com blkSize, 0, Request::wbMasterId); 166111051Sandreas.hansson@arm.com if (blk->isSecure()) 166211199Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 166311051Sandreas.hansson@arm.com 166411199Sandreas.hansson@arm.com req->taskId(blk->task_id); 166511051Sandreas.hansson@arm.com blk->task_id= ContextSwitchTaskId::Unknown; 166611051Sandreas.hansson@arm.com blk->tickInserted = curTick(); 166711051Sandreas.hansson@arm.com 166811199Sandreas.hansson@arm.com PacketPtr pkt = 166911199Sandreas.hansson@arm.com new Packet(req, blk->isDirty() ? 167011199Sandreas.hansson@arm.com MemCmd::WritebackDirty : MemCmd::WritebackClean); 167111199Sandreas.hansson@arm.com 167211744Snikos.nikoleris@arm.com DPRINTF(Cache, "Create Writeback %s writable: %d, dirty: %d\n", 167311744Snikos.nikoleris@arm.com pkt->print(), blk->isWritable(), blk->isDirty()); 167411199Sandreas.hansson@arm.com 167511051Sandreas.hansson@arm.com if (blk->isWritable()) { 167611051Sandreas.hansson@arm.com // not asserting shared means we pass the block in modified 167711051Sandreas.hansson@arm.com // state, mark our own block non-writeable 167811051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 167911051Sandreas.hansson@arm.com } else { 168011284Sandreas.hansson@arm.com // we are in the Owned state, tell the receiver 168111284Sandreas.hansson@arm.com pkt->setHasSharers(); 168211051Sandreas.hansson@arm.com } 168311051Sandreas.hansson@arm.com 168411199Sandreas.hansson@arm.com // make sure the block is not marked dirty 168511199Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 168611051Sandreas.hansson@arm.com 168711199Sandreas.hansson@arm.com pkt->allocate(); 168811199Sandreas.hansson@arm.com std::memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize); 168911199Sandreas.hansson@arm.com 169011199Sandreas.hansson@arm.com return pkt; 169111051Sandreas.hansson@arm.com} 169211051Sandreas.hansson@arm.com 169311051Sandreas.hansson@arm.comPacketPtr 169412351Snikos.nikoleris@arm.comCache::writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id) 169512345Snikos.nikoleris@arm.com{ 169612345Snikos.nikoleris@arm.com Request *req = new Request(tags->regenerateBlkAddr(blk->tag, blk->set), 169712345Snikos.nikoleris@arm.com blkSize, 0, Request::wbMasterId); 169812345Snikos.nikoleris@arm.com if (blk->isSecure()) { 169912345Snikos.nikoleris@arm.com req->setFlags(Request::SECURE); 170012345Snikos.nikoleris@arm.com } 170112345Snikos.nikoleris@arm.com req->taskId(blk->task_id); 170212500Snikos.nikoleris@arm.com 170312351Snikos.nikoleris@arm.com PacketPtr pkt = new Packet(req, MemCmd::WriteClean, blkSize, id); 170412500Snikos.nikoleris@arm.com 170512346Snikos.nikoleris@arm.com if (dest) { 170612346Snikos.nikoleris@arm.com req->setFlags(dest); 170712346Snikos.nikoleris@arm.com pkt->setWriteThrough(); 170812346Snikos.nikoleris@arm.com } 170912500Snikos.nikoleris@arm.com 171012500Snikos.nikoleris@arm.com DPRINTF(Cache, "Create %s writable: %d, dirty: %d\n", pkt->print(), 171112500Snikos.nikoleris@arm.com blk->isWritable(), blk->isDirty()); 171212500Snikos.nikoleris@arm.com 171312500Snikos.nikoleris@arm.com if (blk->isWritable()) { 171412500Snikos.nikoleris@arm.com // not asserting shared means we pass the block in modified 171512500Snikos.nikoleris@arm.com // state, mark our own block non-writeable 171612500Snikos.nikoleris@arm.com blk->status &= ~BlkWritable; 171712500Snikos.nikoleris@arm.com } else { 171812500Snikos.nikoleris@arm.com // we are in the Owned state, tell the receiver 171912500Snikos.nikoleris@arm.com pkt->setHasSharers(); 172012500Snikos.nikoleris@arm.com } 172112500Snikos.nikoleris@arm.com 172212500Snikos.nikoleris@arm.com // make sure the block is not marked dirty 172312500Snikos.nikoleris@arm.com blk->status &= ~BlkDirty; 172412500Snikos.nikoleris@arm.com 172512500Snikos.nikoleris@arm.com pkt->allocate(); 172612345Snikos.nikoleris@arm.com std::memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize); 172712500Snikos.nikoleris@arm.com 172812345Snikos.nikoleris@arm.com return pkt; 172912345Snikos.nikoleris@arm.com} 173012345Snikos.nikoleris@arm.com 173112345Snikos.nikoleris@arm.com 173212345Snikos.nikoleris@arm.comPacketPtr 173311051Sandreas.hansson@arm.comCache::cleanEvictBlk(CacheBlk *blk) 173411051Sandreas.hansson@arm.com{ 173511199Sandreas.hansson@arm.com assert(!writebackClean); 173611051Sandreas.hansson@arm.com assert(blk && blk->isValid() && !blk->isDirty()); 173711051Sandreas.hansson@arm.com // Creating a zero sized write, a message to the snoop filter 173811051Sandreas.hansson@arm.com Request *req = 173911051Sandreas.hansson@arm.com new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0, 174011051Sandreas.hansson@arm.com Request::wbMasterId); 174111051Sandreas.hansson@arm.com if (blk->isSecure()) 174211051Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 174311051Sandreas.hansson@arm.com 174411051Sandreas.hansson@arm.com req->taskId(blk->task_id); 174511051Sandreas.hansson@arm.com blk->task_id = ContextSwitchTaskId::Unknown; 174611051Sandreas.hansson@arm.com blk->tickInserted = curTick(); 174711051Sandreas.hansson@arm.com 174811051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::CleanEvict); 174911051Sandreas.hansson@arm.com pkt->allocate(); 175011744Snikos.nikoleris@arm.com DPRINTF(Cache, "Create CleanEvict %s\n", pkt->print()); 175111051Sandreas.hansson@arm.com 175211051Sandreas.hansson@arm.com return pkt; 175311051Sandreas.hansson@arm.com} 175411051Sandreas.hansson@arm.com 175511051Sandreas.hansson@arm.comvoid 175611051Sandreas.hansson@arm.comCache::memWriteback() 175711051Sandreas.hansson@arm.com{ 175811051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::writebackVisitor); 175911051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 176011051Sandreas.hansson@arm.com} 176111051Sandreas.hansson@arm.com 176211051Sandreas.hansson@arm.comvoid 176311051Sandreas.hansson@arm.comCache::memInvalidate() 176411051Sandreas.hansson@arm.com{ 176511051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::invalidateVisitor); 176611051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 176711051Sandreas.hansson@arm.com} 176811051Sandreas.hansson@arm.com 176911051Sandreas.hansson@arm.combool 177011051Sandreas.hansson@arm.comCache::isDirty() const 177111051Sandreas.hansson@arm.com{ 177211051Sandreas.hansson@arm.com CacheBlkIsDirtyVisitor visitor; 177311051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 177411051Sandreas.hansson@arm.com 177511051Sandreas.hansson@arm.com return visitor.isDirty(); 177611051Sandreas.hansson@arm.com} 177711051Sandreas.hansson@arm.com 177811051Sandreas.hansson@arm.combool 177911051Sandreas.hansson@arm.comCache::writebackVisitor(CacheBlk &blk) 178011051Sandreas.hansson@arm.com{ 178111051Sandreas.hansson@arm.com if (blk.isDirty()) { 178211051Sandreas.hansson@arm.com assert(blk.isValid()); 178311051Sandreas.hansson@arm.com 178411051Sandreas.hansson@arm.com Request request(tags->regenerateBlkAddr(blk.tag, blk.set), 178511051Sandreas.hansson@arm.com blkSize, 0, Request::funcMasterId); 178611051Sandreas.hansson@arm.com request.taskId(blk.task_id); 178711865Snikos.nikoleris@arm.com if (blk.isSecure()) { 178811865Snikos.nikoleris@arm.com request.setFlags(Request::SECURE); 178911865Snikos.nikoleris@arm.com } 179011051Sandreas.hansson@arm.com 179111051Sandreas.hansson@arm.com Packet packet(&request, MemCmd::WriteReq); 179211051Sandreas.hansson@arm.com packet.dataStatic(blk.data); 179311051Sandreas.hansson@arm.com 179411051Sandreas.hansson@arm.com memSidePort->sendFunctional(&packet); 179511051Sandreas.hansson@arm.com 179611051Sandreas.hansson@arm.com blk.status &= ~BlkDirty; 179711051Sandreas.hansson@arm.com } 179811051Sandreas.hansson@arm.com 179911051Sandreas.hansson@arm.com return true; 180011051Sandreas.hansson@arm.com} 180111051Sandreas.hansson@arm.com 180211051Sandreas.hansson@arm.combool 180311051Sandreas.hansson@arm.comCache::invalidateVisitor(CacheBlk &blk) 180411051Sandreas.hansson@arm.com{ 180511051Sandreas.hansson@arm.com 180611051Sandreas.hansson@arm.com if (blk.isDirty()) 180711051Sandreas.hansson@arm.com warn_once("Invalidating dirty cache lines. Expect things to break.\n"); 180811051Sandreas.hansson@arm.com 180911051Sandreas.hansson@arm.com if (blk.isValid()) { 181011051Sandreas.hansson@arm.com assert(!blk.isDirty()); 181111867Snikos.nikoleris@arm.com invalidateBlock(&blk); 181211051Sandreas.hansson@arm.com } 181311051Sandreas.hansson@arm.com 181411051Sandreas.hansson@arm.com return true; 181511051Sandreas.hansson@arm.com} 181611051Sandreas.hansson@arm.com 181711051Sandreas.hansson@arm.comCacheBlk* 181811051Sandreas.hansson@arm.comCache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks) 181911051Sandreas.hansson@arm.com{ 182011051Sandreas.hansson@arm.com CacheBlk *blk = tags->findVictim(addr); 182111051Sandreas.hansson@arm.com 182211484Snikos.nikoleris@arm.com // It is valid to return nullptr if there is no victim 182311051Sandreas.hansson@arm.com if (!blk) 182411051Sandreas.hansson@arm.com return nullptr; 182511051Sandreas.hansson@arm.com 182611051Sandreas.hansson@arm.com if (blk->isValid()) { 182711051Sandreas.hansson@arm.com Addr repl_addr = tags->regenerateBlkAddr(blk->tag, blk->set); 182811051Sandreas.hansson@arm.com MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure()); 182911051Sandreas.hansson@arm.com if (repl_mshr) { 183011051Sandreas.hansson@arm.com // must be an outstanding upgrade request 183111051Sandreas.hansson@arm.com // on a block we're about to replace... 183211051Sandreas.hansson@arm.com assert(!blk->isWritable() || blk->isDirty()); 183311284Sandreas.hansson@arm.com assert(repl_mshr->needsWritable()); 183411051Sandreas.hansson@arm.com // too hard to replace block with transient state 183511051Sandreas.hansson@arm.com // allocation failed, block not inserted 183611484Snikos.nikoleris@arm.com return nullptr; 183711051Sandreas.hansson@arm.com } else { 183811483Snikos.nikoleris@arm.com DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx " 183911483Snikos.nikoleris@arm.com "(%s): %s\n", repl_addr, blk->isSecure() ? "s" : "ns", 184011051Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", 184111051Sandreas.hansson@arm.com blk->isDirty() ? "writeback" : "clean"); 184211051Sandreas.hansson@arm.com 184311436SRekai.GonzalezAlberquilla@arm.com if (blk->wasPrefetched()) { 184411436SRekai.GonzalezAlberquilla@arm.com unusedPrefetches++; 184511436SRekai.GonzalezAlberquilla@arm.com } 184611051Sandreas.hansson@arm.com // Will send up Writeback/CleanEvict snoops via isCachedAbove 184711051Sandreas.hansson@arm.com // when pushing this writeback list into the write buffer. 184811199Sandreas.hansson@arm.com if (blk->isDirty() || writebackClean) { 184911051Sandreas.hansson@arm.com // Save writeback packet for handling by caller 185011051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(blk)); 185111051Sandreas.hansson@arm.com } else { 185211051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(blk)); 185311051Sandreas.hansson@arm.com } 185411051Sandreas.hansson@arm.com } 185511051Sandreas.hansson@arm.com } 185611051Sandreas.hansson@arm.com 185711051Sandreas.hansson@arm.com return blk; 185811051Sandreas.hansson@arm.com} 185911051Sandreas.hansson@arm.com 186011197Sandreas.hansson@arm.comvoid 186111197Sandreas.hansson@arm.comCache::invalidateBlock(CacheBlk *blk) 186211197Sandreas.hansson@arm.com{ 186311197Sandreas.hansson@arm.com if (blk != tempBlock) 186411197Sandreas.hansson@arm.com tags->invalidate(blk); 186511197Sandreas.hansson@arm.com blk->invalidate(); 186611197Sandreas.hansson@arm.com} 186711051Sandreas.hansson@arm.com 186811051Sandreas.hansson@arm.com// Note that the reason we return a list of writebacks rather than 186911051Sandreas.hansson@arm.com// inserting them directly in the write buffer is that this function 187011051Sandreas.hansson@arm.com// is called by both atomic and timing-mode accesses, and in atomic 187111051Sandreas.hansson@arm.com// mode we don't mess with the write buffer (we just perform the 187211051Sandreas.hansson@arm.com// writebacks atomically once the original request is complete). 187311051Sandreas.hansson@arm.comCacheBlk* 187411197Sandreas.hansson@arm.comCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks, 187511197Sandreas.hansson@arm.com bool allocate) 187611051Sandreas.hansson@arm.com{ 187711051Sandreas.hansson@arm.com assert(pkt->isResponse() || pkt->cmd == MemCmd::WriteLineReq); 187811051Sandreas.hansson@arm.com Addr addr = pkt->getAddr(); 187911051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 188011051Sandreas.hansson@arm.com#if TRACING_ON 188111051Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 188211051Sandreas.hansson@arm.com#endif 188311051Sandreas.hansson@arm.com 188411375Sandreas.hansson@arm.com // When handling a fill, we should have no writes to this line. 188511892Snikos.nikoleris@arm.com assert(addr == pkt->getBlockAddr(blkSize)); 188611375Sandreas.hansson@arm.com assert(!writeBuffer.findMatch(addr, is_secure)); 188711051Sandreas.hansson@arm.com 188811484Snikos.nikoleris@arm.com if (blk == nullptr) { 188911051Sandreas.hansson@arm.com // better have read new data... 189011051Sandreas.hansson@arm.com assert(pkt->hasData()); 189111051Sandreas.hansson@arm.com 189211051Sandreas.hansson@arm.com // only read responses and write-line requests have data; 189311051Sandreas.hansson@arm.com // note that we don't write the data here for write-line - that 189411601Sandreas.hansson@arm.com // happens in the subsequent call to satisfyRequest 189511051Sandreas.hansson@arm.com assert(pkt->isRead() || pkt->cmd == MemCmd::WriteLineReq); 189611051Sandreas.hansson@arm.com 189711197Sandreas.hansson@arm.com // need to do a replacement if allocating, otherwise we stick 189811197Sandreas.hansson@arm.com // with the temporary storage 189911484Snikos.nikoleris@arm.com blk = allocate ? allocateBlock(addr, is_secure, writebacks) : nullptr; 190011197Sandreas.hansson@arm.com 190111484Snikos.nikoleris@arm.com if (blk == nullptr) { 190211197Sandreas.hansson@arm.com // No replaceable block or a mostly exclusive 190311197Sandreas.hansson@arm.com // cache... just use temporary storage to complete the 190411197Sandreas.hansson@arm.com // current request and then get rid of it 190511051Sandreas.hansson@arm.com assert(!tempBlock->isValid()); 190611051Sandreas.hansson@arm.com blk = tempBlock; 190711051Sandreas.hansson@arm.com tempBlock->set = tags->extractSet(addr); 190811051Sandreas.hansson@arm.com tempBlock->tag = tags->extractTag(addr); 190911051Sandreas.hansson@arm.com // @todo: set security state as well... 191011051Sandreas.hansson@arm.com DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr, 191111051Sandreas.hansson@arm.com is_secure ? "s" : "ns"); 191211051Sandreas.hansson@arm.com } else { 191311051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 191411051Sandreas.hansson@arm.com } 191511051Sandreas.hansson@arm.com 191611051Sandreas.hansson@arm.com // we should never be overwriting a valid block 191711051Sandreas.hansson@arm.com assert(!blk->isValid()); 191811051Sandreas.hansson@arm.com } else { 191911051Sandreas.hansson@arm.com // existing block... probably an upgrade 192011051Sandreas.hansson@arm.com assert(blk->tag == tags->extractTag(addr)); 192111051Sandreas.hansson@arm.com // either we're getting new data or the block should already be valid 192211051Sandreas.hansson@arm.com assert(pkt->hasData() || blk->isValid()); 192311051Sandreas.hansson@arm.com // don't clear block status... if block is already dirty we 192411051Sandreas.hansson@arm.com // don't want to lose that 192511051Sandreas.hansson@arm.com } 192611051Sandreas.hansson@arm.com 192711051Sandreas.hansson@arm.com if (is_secure) 192811051Sandreas.hansson@arm.com blk->status |= BlkSecure; 192911051Sandreas.hansson@arm.com blk->status |= BlkValid | BlkReadable; 193011051Sandreas.hansson@arm.com 193111137Sandreas.hansson@arm.com // sanity check for whole-line writes, which should always be 193211137Sandreas.hansson@arm.com // marked as writable as part of the fill, and then later marked 193311601Sandreas.hansson@arm.com // dirty as part of satisfyRequest 193411137Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WriteLineReq) { 193511284Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 193611137Sandreas.hansson@arm.com } 193711137Sandreas.hansson@arm.com 193811284Sandreas.hansson@arm.com // here we deal with setting the appropriate state of the line, 193911284Sandreas.hansson@arm.com // and we start by looking at the hasSharers flag, and ignore the 194011284Sandreas.hansson@arm.com // cacheResponding flag (normally signalling dirty data) if the 194111284Sandreas.hansson@arm.com // packet has sharers, thus the line is never allocated as Owned 194211284Sandreas.hansson@arm.com // (dirty but not writable), and always ends up being either 194311284Sandreas.hansson@arm.com // Shared, Exclusive or Modified, see Packet::setCacheResponding 194411284Sandreas.hansson@arm.com // for more details 194511284Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 194611284Sandreas.hansson@arm.com // we could get a writable line from memory (rather than a 194711284Sandreas.hansson@arm.com // cache) even in a read-only cache, note that we set this bit 194811284Sandreas.hansson@arm.com // even for a read-only cache, possibly revisit this decision 194911051Sandreas.hansson@arm.com blk->status |= BlkWritable; 195011051Sandreas.hansson@arm.com 195111284Sandreas.hansson@arm.com // check if we got this via cache-to-cache transfer (i.e., from a 195211284Sandreas.hansson@arm.com // cache that had the block in Modified or Owned state) 195311284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 195411284Sandreas.hansson@arm.com // we got the block in Modified state, and invalidated the 195511284Sandreas.hansson@arm.com // owners copy 195611051Sandreas.hansson@arm.com blk->status |= BlkDirty; 195711051Sandreas.hansson@arm.com 195811051Sandreas.hansson@arm.com chatty_assert(!isReadOnly, "Should never see dirty snoop response " 195911051Sandreas.hansson@arm.com "in read-only cache %s\n", name()); 196011051Sandreas.hansson@arm.com } 196111051Sandreas.hansson@arm.com } 196211051Sandreas.hansson@arm.com 196311051Sandreas.hansson@arm.com DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n", 196411051Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", old_state, blk->print()); 196511051Sandreas.hansson@arm.com 196611051Sandreas.hansson@arm.com // if we got new data, copy it in (checking for a read response 196711051Sandreas.hansson@arm.com // and a response that has data is the same in the end) 196811051Sandreas.hansson@arm.com if (pkt->isRead()) { 196911051Sandreas.hansson@arm.com // sanity checks 197011051Sandreas.hansson@arm.com assert(pkt->hasData()); 197111051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 197211051Sandreas.hansson@arm.com 197311051Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 197411051Sandreas.hansson@arm.com } 197511051Sandreas.hansson@arm.com // We pay for fillLatency here. 197611051Sandreas.hansson@arm.com blk->whenReady = clockEdge() + fillLatency * clockPeriod() + 197711051Sandreas.hansson@arm.com pkt->payloadDelay; 197811051Sandreas.hansson@arm.com 197911051Sandreas.hansson@arm.com return blk; 198011051Sandreas.hansson@arm.com} 198111051Sandreas.hansson@arm.com 198211051Sandreas.hansson@arm.com 198311051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 198411051Sandreas.hansson@arm.com// 198511051Sandreas.hansson@arm.com// Snoop path: requests coming in from the memory side 198611051Sandreas.hansson@arm.com// 198711051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 198811051Sandreas.hansson@arm.com 198911051Sandreas.hansson@arm.comvoid 199011051Sandreas.hansson@arm.comCache::doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 199111051Sandreas.hansson@arm.com bool already_copied, bool pending_inval) 199211051Sandreas.hansson@arm.com{ 199311051Sandreas.hansson@arm.com // sanity check 199411051Sandreas.hansson@arm.com assert(req_pkt->isRequest()); 199511051Sandreas.hansson@arm.com assert(req_pkt->needsResponse()); 199611051Sandreas.hansson@arm.com 199711744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: for %s\n", __func__, req_pkt->print()); 199811051Sandreas.hansson@arm.com // timing-mode snoop responses require a new packet, unless we 199911051Sandreas.hansson@arm.com // already made a copy... 200011051Sandreas.hansson@arm.com PacketPtr pkt = req_pkt; 200111051Sandreas.hansson@arm.com if (!already_copied) 200211051Sandreas.hansson@arm.com // do not clear flags, and allocate space for data if the 200311051Sandreas.hansson@arm.com // packet needs it (the only packets that carry data are read 200411051Sandreas.hansson@arm.com // responses) 200511051Sandreas.hansson@arm.com pkt = new Packet(req_pkt, false, req_pkt->isRead()); 200611051Sandreas.hansson@arm.com 200711051Sandreas.hansson@arm.com assert(req_pkt->req->isUncacheable() || req_pkt->isInvalidate() || 200811284Sandreas.hansson@arm.com pkt->hasSharers()); 200911051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 201011051Sandreas.hansson@arm.com if (pkt->isRead()) { 201111051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk_data, blkSize); 201211051Sandreas.hansson@arm.com } 201311051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::ReadResp && pending_inval) { 201411051Sandreas.hansson@arm.com // Assume we defer a response to a read from a far-away cache 201511051Sandreas.hansson@arm.com // A, then later defer a ReadExcl from a cache B on the same 201611284Sandreas.hansson@arm.com // bus as us. We'll assert cacheResponding in both cases, but 201711284Sandreas.hansson@arm.com // in the latter case cacheResponding will keep the 201811284Sandreas.hansson@arm.com // invalidation from reaching cache A. This special response 201911284Sandreas.hansson@arm.com // tells cache A that it gets the block to satisfy its read, 202011284Sandreas.hansson@arm.com // but must immediately invalidate it. 202111051Sandreas.hansson@arm.com pkt->cmd = MemCmd::ReadRespWithInvalidate; 202211051Sandreas.hansson@arm.com } 202311051Sandreas.hansson@arm.com // Here we consider forward_time, paying for just forward latency and 202411051Sandreas.hansson@arm.com // also charging the delay provided by the xbar. 202511051Sandreas.hansson@arm.com // forward_time is used as send_time in next allocateWriteBuffer(). 202611051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 202711051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 202811051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 202911744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: created response: %s tick: %lu\n", __func__, 203011744Snikos.nikoleris@arm.com pkt->print(), forward_time); 203111051Sandreas.hansson@arm.com memSidePort->schedTimingSnoopResp(pkt, forward_time, true); 203211051Sandreas.hansson@arm.com} 203311051Sandreas.hansson@arm.com 203411127Sandreas.hansson@arm.comuint32_t 203511051Sandreas.hansson@arm.comCache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing, 203611051Sandreas.hansson@arm.com bool is_deferred, bool pending_inval) 203711051Sandreas.hansson@arm.com{ 203811744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print()); 203911051Sandreas.hansson@arm.com // deferred snoops can only happen in timing mode 204011051Sandreas.hansson@arm.com assert(!(is_deferred && !is_timing)); 204111051Sandreas.hansson@arm.com // pending_inval only makes sense on deferred snoops 204211051Sandreas.hansson@arm.com assert(!(pending_inval && !is_deferred)); 204311051Sandreas.hansson@arm.com assert(pkt->isRequest()); 204411051Sandreas.hansson@arm.com 204511051Sandreas.hansson@arm.com // the packet may get modified if we or a forwarded snooper 204611051Sandreas.hansson@arm.com // responds in atomic mode, so remember a few things about the 204711051Sandreas.hansson@arm.com // original packet up front 204811051Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 204911284Sandreas.hansson@arm.com bool M5_VAR_USED needs_writable = pkt->needsWritable(); 205011051Sandreas.hansson@arm.com 205111285Sandreas.hansson@arm.com // at the moment we could get an uncacheable write which does not 205211285Sandreas.hansson@arm.com // have the invalidate flag, and we need a suitable way of dealing 205311285Sandreas.hansson@arm.com // with this case 205411285Sandreas.hansson@arm.com panic_if(invalidate && pkt->req->isUncacheable(), 205511744Snikos.nikoleris@arm.com "%s got an invalidating uncacheable snoop request %s", 205611744Snikos.nikoleris@arm.com name(), pkt->print()); 205711285Sandreas.hansson@arm.com 205811127Sandreas.hansson@arm.com uint32_t snoop_delay = 0; 205911127Sandreas.hansson@arm.com 206011051Sandreas.hansson@arm.com if (forwardSnoops) { 206111051Sandreas.hansson@arm.com // first propagate snoop upward to see if anyone above us wants to 206211051Sandreas.hansson@arm.com // handle it. save & restore packet src since it will get 206311051Sandreas.hansson@arm.com // rewritten to be relative to cpu-side bus (if any) 206411284Sandreas.hansson@arm.com bool alreadyResponded = pkt->cacheResponding(); 206511051Sandreas.hansson@arm.com if (is_timing) { 206611051Sandreas.hansson@arm.com // copy the packet so that we can clear any flags before 206711051Sandreas.hansson@arm.com // forwarding it upwards, we also allocate data (passing 206811051Sandreas.hansson@arm.com // the pointer along in case of static data), in case 206911051Sandreas.hansson@arm.com // there is a snoop hit in upper levels 207011051Sandreas.hansson@arm.com Packet snoopPkt(pkt, true, true); 207111051Sandreas.hansson@arm.com snoopPkt.setExpressSnoop(); 207211051Sandreas.hansson@arm.com // the snoop packet does not need to wait any additional 207311051Sandreas.hansson@arm.com // time 207411051Sandreas.hansson@arm.com snoopPkt.headerDelay = snoopPkt.payloadDelay = 0; 207511051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoopPkt); 207611127Sandreas.hansson@arm.com 207711127Sandreas.hansson@arm.com // add the header delay (including crossbar and snoop 207811127Sandreas.hansson@arm.com // delays) of the upward snoop to the snoop delay for this 207911127Sandreas.hansson@arm.com // cache 208011127Sandreas.hansson@arm.com snoop_delay += snoopPkt.headerDelay; 208111127Sandreas.hansson@arm.com 208211284Sandreas.hansson@arm.com if (snoopPkt.cacheResponding()) { 208311051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache 208411051Sandreas.hansson@arm.com assert(!alreadyResponded); 208511284Sandreas.hansson@arm.com pkt->setCacheResponding(); 208611051Sandreas.hansson@arm.com } 208711284Sandreas.hansson@arm.com // upstream cache has the block, or has an outstanding 208811284Sandreas.hansson@arm.com // MSHR, pass the flag on 208911284Sandreas.hansson@arm.com if (snoopPkt.hasSharers()) { 209011284Sandreas.hansson@arm.com pkt->setHasSharers(); 209111051Sandreas.hansson@arm.com } 209211051Sandreas.hansson@arm.com // If this request is a prefetch or clean evict and an upper level 209311051Sandreas.hansson@arm.com // signals block present, make sure to propagate the block 209411051Sandreas.hansson@arm.com // presence to the requester. 209511051Sandreas.hansson@arm.com if (snoopPkt.isBlockCached()) { 209611051Sandreas.hansson@arm.com pkt->setBlockCached(); 209711051Sandreas.hansson@arm.com } 209812349Snikos.nikoleris@arm.com // If the request was satisfied by snooping the cache 209912349Snikos.nikoleris@arm.com // above, mark the original packet as satisfied too. 210012349Snikos.nikoleris@arm.com if (snoopPkt.satisfied()) { 210112349Snikos.nikoleris@arm.com pkt->setSatisfied(); 210212349Snikos.nikoleris@arm.com } 210311051Sandreas.hansson@arm.com } else { 210411051Sandreas.hansson@arm.com cpuSidePort->sendAtomicSnoop(pkt); 210511284Sandreas.hansson@arm.com if (!alreadyResponded && pkt->cacheResponding()) { 210611051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache: 210711051Sandreas.hansson@arm.com // forward response to original requester 210811051Sandreas.hansson@arm.com assert(pkt->isResponse()); 210911051Sandreas.hansson@arm.com } 211011051Sandreas.hansson@arm.com } 211111051Sandreas.hansson@arm.com } 211211051Sandreas.hansson@arm.com 211312349Snikos.nikoleris@arm.com bool respond = false; 211412349Snikos.nikoleris@arm.com bool blk_valid = blk && blk->isValid(); 211512349Snikos.nikoleris@arm.com if (pkt->isClean()) { 211612349Snikos.nikoleris@arm.com if (blk_valid && blk->isDirty()) { 211712349Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: packet (snoop) %s found block: %s\n", 211812349Snikos.nikoleris@arm.com __func__, pkt->print(), blk->print()); 211912351Snikos.nikoleris@arm.com PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id); 212012349Snikos.nikoleris@arm.com PacketList writebacks; 212112349Snikos.nikoleris@arm.com writebacks.push_back(wb_pkt); 212212349Snikos.nikoleris@arm.com 212312349Snikos.nikoleris@arm.com if (is_timing) { 212412349Snikos.nikoleris@arm.com // anything that is merely forwarded pays for the forward 212512349Snikos.nikoleris@arm.com // latency and the delay provided by the crossbar 212612349Snikos.nikoleris@arm.com Tick forward_time = clockEdge(forwardLatency) + 212712349Snikos.nikoleris@arm.com pkt->headerDelay; 212812349Snikos.nikoleris@arm.com doWritebacks(writebacks, forward_time); 212912349Snikos.nikoleris@arm.com } else { 213012349Snikos.nikoleris@arm.com doWritebacksAtomic(writebacks); 213112349Snikos.nikoleris@arm.com } 213212349Snikos.nikoleris@arm.com pkt->setSatisfied(); 213312349Snikos.nikoleris@arm.com } 213412349Snikos.nikoleris@arm.com } else if (!blk_valid) { 213511744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: snoop miss for %s\n", __func__, 213611744Snikos.nikoleris@arm.com pkt->print()); 213711493Sandreas.hansson@arm.com if (is_deferred) { 213811493Sandreas.hansson@arm.com // we no longer have the block, and will not respond, but a 213911493Sandreas.hansson@arm.com // packet was allocated in MSHR::handleSnoop and we have 214011493Sandreas.hansson@arm.com // to delete it 214111493Sandreas.hansson@arm.com assert(pkt->needsResponse()); 214211493Sandreas.hansson@arm.com 214311493Sandreas.hansson@arm.com // we have passed the block to a cache upstream, that 214411493Sandreas.hansson@arm.com // cache should be responding 214511493Sandreas.hansson@arm.com assert(pkt->cacheResponding()); 214611493Sandreas.hansson@arm.com 214711493Sandreas.hansson@arm.com delete pkt; 214811493Sandreas.hansson@arm.com } 214911127Sandreas.hansson@arm.com return snoop_delay; 215011051Sandreas.hansson@arm.com } else { 215111744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: snoop hit for %s, old state is %s\n", __func__, 215211744Snikos.nikoleris@arm.com pkt->print(), blk->print()); 215312349Snikos.nikoleris@arm.com 215412349Snikos.nikoleris@arm.com // We may end up modifying both the block state and the packet (if 215512349Snikos.nikoleris@arm.com // we respond in atomic mode), so just figure out what to do now 215612349Snikos.nikoleris@arm.com // and then do it later. We respond to all snoops that need 215712349Snikos.nikoleris@arm.com // responses provided we have the block in dirty state. The 215812349Snikos.nikoleris@arm.com // invalidation itself is taken care of below. We don't respond to 215912349Snikos.nikoleris@arm.com // cache maintenance operations as this is done by the destination 216012349Snikos.nikoleris@arm.com // xbar. 216112349Snikos.nikoleris@arm.com respond = blk->isDirty() && pkt->needsResponse(); 216212349Snikos.nikoleris@arm.com 216312349Snikos.nikoleris@arm.com chatty_assert(!(isReadOnly && blk->isDirty()), "Should never have " 216412349Snikos.nikoleris@arm.com "a dirty block in a read-only cache %s\n", name()); 216511051Sandreas.hansson@arm.com } 216611051Sandreas.hansson@arm.com 216711051Sandreas.hansson@arm.com // Invalidate any prefetch's from below that would strip write permissions 216811051Sandreas.hansson@arm.com // MemCmd::HardPFReq is only observed by upstream caches. After missing 216911051Sandreas.hansson@arm.com // above and in it's own cache, a new MemCmd::ReadReq is created that 217011051Sandreas.hansson@arm.com // downstream caches observe. 217111051Sandreas.hansson@arm.com if (pkt->mustCheckAbove()) { 217211483Snikos.nikoleris@arm.com DPRINTF(Cache, "Found addr %#llx in upper level cache for snoop %s " 217311744Snikos.nikoleris@arm.com "from lower cache\n", pkt->getAddr(), pkt->print()); 217411051Sandreas.hansson@arm.com pkt->setBlockCached(); 217511127Sandreas.hansson@arm.com return snoop_delay; 217611051Sandreas.hansson@arm.com } 217711051Sandreas.hansson@arm.com 217811285Sandreas.hansson@arm.com if (pkt->isRead() && !invalidate) { 217911285Sandreas.hansson@arm.com // reading without requiring the line in a writable state 218011284Sandreas.hansson@arm.com assert(!needs_writable); 218111284Sandreas.hansson@arm.com pkt->setHasSharers(); 218211285Sandreas.hansson@arm.com 218311285Sandreas.hansson@arm.com // if the requesting packet is uncacheable, retain the line in 218411285Sandreas.hansson@arm.com // the current state, otherwhise unset the writable flag, 218511285Sandreas.hansson@arm.com // which means we go from Modified to Owned (and will respond 218611285Sandreas.hansson@arm.com // below), remain in Owned (and will respond below), from 218711285Sandreas.hansson@arm.com // Exclusive to Shared, or remain in Shared 218811285Sandreas.hansson@arm.com if (!pkt->req->isUncacheable()) 218911285Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 219012349Snikos.nikoleris@arm.com DPRINTF(Cache, "new state is %s\n", blk->print()); 219111051Sandreas.hansson@arm.com } 219211051Sandreas.hansson@arm.com 219311051Sandreas.hansson@arm.com if (respond) { 219411051Sandreas.hansson@arm.com // prevent anyone else from responding, cache as well as 219511051Sandreas.hansson@arm.com // memory, and also prevent any memory from even seeing the 219611284Sandreas.hansson@arm.com // request 219711284Sandreas.hansson@arm.com pkt->setCacheResponding(); 219812349Snikos.nikoleris@arm.com if (!pkt->isClean() && blk->isWritable()) { 219911284Sandreas.hansson@arm.com // inform the cache hierarchy that this cache had the line 220011284Sandreas.hansson@arm.com // in the Modified state so that we avoid unnecessary 220111284Sandreas.hansson@arm.com // invalidations (see Packet::setResponderHadWritable) 220211284Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 220311284Sandreas.hansson@arm.com 220411081Sandreas.hansson@arm.com // in the case of an uncacheable request there is no point 220511284Sandreas.hansson@arm.com // in setting the responderHadWritable flag, but since the 220611284Sandreas.hansson@arm.com // recipient does not care there is no harm in doing so 220711284Sandreas.hansson@arm.com } else { 220811284Sandreas.hansson@arm.com // if the packet has needsWritable set we invalidate our 220911284Sandreas.hansson@arm.com // copy below and all other copies will be invalidates 221011284Sandreas.hansson@arm.com // through express snoops, and if needsWritable is not set 221111284Sandreas.hansson@arm.com // we already called setHasSharers above 221211051Sandreas.hansson@arm.com } 221311284Sandreas.hansson@arm.com 221411285Sandreas.hansson@arm.com // if we are returning a writable and dirty (Modified) line, 221511285Sandreas.hansson@arm.com // we should be invalidating the line 221611285Sandreas.hansson@arm.com panic_if(!invalidate && !pkt->hasSharers(), 221711744Snikos.nikoleris@arm.com "%s is passing a Modified line through %s, " 221811744Snikos.nikoleris@arm.com "but keeping the block", name(), pkt->print()); 221911285Sandreas.hansson@arm.com 222011051Sandreas.hansson@arm.com if (is_timing) { 222111051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, blk->data, is_deferred, pending_inval); 222211051Sandreas.hansson@arm.com } else { 222311051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 222411286Sandreas.hansson@arm.com // packets such as upgrades do not actually have any data 222511286Sandreas.hansson@arm.com // payload 222611286Sandreas.hansson@arm.com if (pkt->hasData()) 222711286Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 222811051Sandreas.hansson@arm.com } 222911051Sandreas.hansson@arm.com } 223011051Sandreas.hansson@arm.com 223111602Sandreas.hansson@arm.com if (!respond && is_deferred) { 223211051Sandreas.hansson@arm.com assert(pkt->needsResponse()); 223311602Sandreas.hansson@arm.com 223411602Sandreas.hansson@arm.com // if we copied the deferred packet with the intention to 223511602Sandreas.hansson@arm.com // respond, but are not responding, then a cache above us must 223611602Sandreas.hansson@arm.com // be, and we can use this as the indication of whether this 223711602Sandreas.hansson@arm.com // is a packet where we created a copy of the request or not 223811602Sandreas.hansson@arm.com if (!pkt->cacheResponding()) { 223911602Sandreas.hansson@arm.com delete pkt->req; 224011602Sandreas.hansson@arm.com } 224111602Sandreas.hansson@arm.com 224211051Sandreas.hansson@arm.com delete pkt; 224311051Sandreas.hansson@arm.com } 224411051Sandreas.hansson@arm.com 224511051Sandreas.hansson@arm.com // Do this last in case it deallocates block data or something 224611051Sandreas.hansson@arm.com // like that 224712349Snikos.nikoleris@arm.com if (blk_valid && invalidate) { 224811197Sandreas.hansson@arm.com invalidateBlock(blk); 224912349Snikos.nikoleris@arm.com DPRINTF(Cache, "new state is %s\n", blk->print()); 225011051Sandreas.hansson@arm.com } 225111051Sandreas.hansson@arm.com 225211127Sandreas.hansson@arm.com return snoop_delay; 225311051Sandreas.hansson@arm.com} 225411051Sandreas.hansson@arm.com 225511051Sandreas.hansson@arm.com 225611051Sandreas.hansson@arm.comvoid 225711051Sandreas.hansson@arm.comCache::recvTimingSnoopReq(PacketPtr pkt) 225811051Sandreas.hansson@arm.com{ 225911744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print()); 226011051Sandreas.hansson@arm.com 226111051Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 226211051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 226311051Sandreas.hansson@arm.com 226411130Sali.jafri@arm.com // no need to snoop requests that are not in range 226511051Sandreas.hansson@arm.com if (!inRange(pkt->getAddr())) { 226611051Sandreas.hansson@arm.com return; 226711051Sandreas.hansson@arm.com } 226811051Sandreas.hansson@arm.com 226911051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 227011051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 227111051Sandreas.hansson@arm.com 227211892Snikos.nikoleris@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 227311051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 227411051Sandreas.hansson@arm.com 227511127Sandreas.hansson@arm.com // Update the latency cost of the snoop so that the crossbar can 227611127Sandreas.hansson@arm.com // account for it. Do not overwrite what other neighbouring caches 227711127Sandreas.hansson@arm.com // have already done, rather take the maximum. The update is 227811127Sandreas.hansson@arm.com // tentative, for cases where we return before an upward snoop 227911127Sandreas.hansson@arm.com // happens below. 228011127Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, 228111127Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 228211127Sandreas.hansson@arm.com 228311051Sandreas.hansson@arm.com // Inform request(Prefetch, CleanEvict or Writeback) from below of 228411051Sandreas.hansson@arm.com // MSHR hit, set setBlockCached. 228511051Sandreas.hansson@arm.com if (mshr && pkt->mustCheckAbove()) { 228611744Snikos.nikoleris@arm.com DPRINTF(Cache, "Setting block cached for %s from lower cache on " 228711744Snikos.nikoleris@arm.com "mshr hit\n", pkt->print()); 228811051Sandreas.hansson@arm.com pkt->setBlockCached(); 228911051Sandreas.hansson@arm.com return; 229011051Sandreas.hansson@arm.com } 229111051Sandreas.hansson@arm.com 229212349Snikos.nikoleris@arm.com // Bypass any existing cache maintenance requests if the request 229312349Snikos.nikoleris@arm.com // has been satisfied already (i.e., the dirty block has been 229412349Snikos.nikoleris@arm.com // found). 229512349Snikos.nikoleris@arm.com if (mshr && pkt->req->isCacheMaintenance() && pkt->satisfied()) { 229612349Snikos.nikoleris@arm.com return; 229712349Snikos.nikoleris@arm.com } 229812349Snikos.nikoleris@arm.com 229911051Sandreas.hansson@arm.com // Let the MSHR itself track the snoop and decide whether we want 230011051Sandreas.hansson@arm.com // to go ahead and do the regular cache snoop 230111051Sandreas.hansson@arm.com if (mshr && mshr->handleSnoop(pkt, order++)) { 230211051Sandreas.hansson@arm.com DPRINTF(Cache, "Deferring snoop on in-service MSHR to blk %#llx (%s)." 230311051Sandreas.hansson@arm.com "mshrs: %s\n", blk_addr, is_secure ? "s" : "ns", 230411051Sandreas.hansson@arm.com mshr->print()); 230511051Sandreas.hansson@arm.com 230611051Sandreas.hansson@arm.com if (mshr->getNumTargets() > numTarget) 230711051Sandreas.hansson@arm.com warn("allocating bonus target for snoop"); //handle later 230811051Sandreas.hansson@arm.com return; 230911051Sandreas.hansson@arm.com } 231011051Sandreas.hansson@arm.com 231111051Sandreas.hansson@arm.com //We also need to check the writeback buffers and handle those 231211375Sandreas.hansson@arm.com WriteQueueEntry *wb_entry = writeBuffer.findMatch(blk_addr, is_secure); 231311375Sandreas.hansson@arm.com if (wb_entry) { 231411051Sandreas.hansson@arm.com DPRINTF(Cache, "Snoop hit in writeback to addr %#llx (%s)\n", 231511051Sandreas.hansson@arm.com pkt->getAddr(), is_secure ? "s" : "ns"); 231611051Sandreas.hansson@arm.com // Expect to see only Writebacks and/or CleanEvicts here, both of 231711051Sandreas.hansson@arm.com // which should not be generated for uncacheable data. 231811051Sandreas.hansson@arm.com assert(!wb_entry->isUncacheable()); 231911051Sandreas.hansson@arm.com // There should only be a single request responsible for generating 232011051Sandreas.hansson@arm.com // Writebacks/CleanEvicts. 232111051Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 232211051Sandreas.hansson@arm.com PacketPtr wb_pkt = wb_entry->getTarget()->pkt; 232312345Snikos.nikoleris@arm.com assert(wb_pkt->isEviction() || wb_pkt->cmd == MemCmd::WriteClean); 232411051Sandreas.hansson@arm.com 232511199Sandreas.hansson@arm.com if (pkt->isEviction()) { 232611051Sandreas.hansson@arm.com // if the block is found in the write queue, set the BLOCK_CACHED 232711051Sandreas.hansson@arm.com // flag for Writeback/CleanEvict snoop. On return the snoop will 232811051Sandreas.hansson@arm.com // propagate the BLOCK_CACHED flag in Writeback packets and prevent 232911051Sandreas.hansson@arm.com // any CleanEvicts from travelling down the memory hierarchy. 233011051Sandreas.hansson@arm.com pkt->setBlockCached(); 233111744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Squashing %s from lower cache on writequeue " 233211744Snikos.nikoleris@arm.com "hit\n", __func__, pkt->print()); 233311051Sandreas.hansson@arm.com return; 233411051Sandreas.hansson@arm.com } 233511051Sandreas.hansson@arm.com 233611332Sandreas.hansson@arm.com // conceptually writebacks are no different to other blocks in 233711332Sandreas.hansson@arm.com // this cache, so the behaviour is modelled after handleSnoop, 233811332Sandreas.hansson@arm.com // the difference being that instead of querying the block 233911332Sandreas.hansson@arm.com // state to determine if it is dirty and writable, we use the 234011332Sandreas.hansson@arm.com // command and fields of the writeback packet 234111332Sandreas.hansson@arm.com bool respond = wb_pkt->cmd == MemCmd::WritebackDirty && 234211751Snikos.nikoleris@arm.com pkt->needsResponse(); 234311332Sandreas.hansson@arm.com bool have_writable = !wb_pkt->hasSharers(); 234411332Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 234511332Sandreas.hansson@arm.com 234611332Sandreas.hansson@arm.com if (!pkt->req->isUncacheable() && pkt->isRead() && !invalidate) { 234711332Sandreas.hansson@arm.com assert(!pkt->needsWritable()); 234811332Sandreas.hansson@arm.com pkt->setHasSharers(); 234911332Sandreas.hansson@arm.com wb_pkt->setHasSharers(); 235011332Sandreas.hansson@arm.com } 235111332Sandreas.hansson@arm.com 235211332Sandreas.hansson@arm.com if (respond) { 235311284Sandreas.hansson@arm.com pkt->setCacheResponding(); 235411332Sandreas.hansson@arm.com 235511332Sandreas.hansson@arm.com if (have_writable) { 235611332Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 235711051Sandreas.hansson@arm.com } 235811332Sandreas.hansson@arm.com 235911051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, wb_pkt->getConstPtr<uint8_t>(), 236011051Sandreas.hansson@arm.com false, false); 236111051Sandreas.hansson@arm.com } 236211051Sandreas.hansson@arm.com 236312349Snikos.nikoleris@arm.com if (invalidate && wb_pkt->cmd != MemCmd::WriteClean) { 236411051Sandreas.hansson@arm.com // Invalidation trumps our writeback... discard here 236511051Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 236611375Sandreas.hansson@arm.com markInService(wb_entry); 236711051Sandreas.hansson@arm.com delete wb_pkt; 236811051Sandreas.hansson@arm.com } 236911051Sandreas.hansson@arm.com } 237011051Sandreas.hansson@arm.com 237111051Sandreas.hansson@arm.com // If this was a shared writeback, there may still be 237211051Sandreas.hansson@arm.com // other shared copies above that require invalidation. 237311051Sandreas.hansson@arm.com // We could be more selective and return here if the 237411051Sandreas.hansson@arm.com // request is non-exclusive or if the writeback is 237511051Sandreas.hansson@arm.com // exclusive. 237611127Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, true, false, false); 237711127Sandreas.hansson@arm.com 237811127Sandreas.hansson@arm.com // Override what we did when we first saw the snoop, as we now 237911127Sandreas.hansson@arm.com // also have the cost of the upwards snoops to account for 238011127Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, snoop_delay + 238111127Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 238211051Sandreas.hansson@arm.com} 238311051Sandreas.hansson@arm.com 238411051Sandreas.hansson@arm.combool 238511051Sandreas.hansson@arm.comCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt) 238611051Sandreas.hansson@arm.com{ 238711051Sandreas.hansson@arm.com // Express snoop responses from master to slave, e.g., from L1 to L2 238811051Sandreas.hansson@arm.com cache->recvTimingSnoopResp(pkt); 238911051Sandreas.hansson@arm.com return true; 239011051Sandreas.hansson@arm.com} 239111051Sandreas.hansson@arm.com 239211051Sandreas.hansson@arm.comTick 239311051Sandreas.hansson@arm.comCache::recvAtomicSnoop(PacketPtr pkt) 239411051Sandreas.hansson@arm.com{ 239511051Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 239611051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 239711051Sandreas.hansson@arm.com 239811130Sali.jafri@arm.com // no need to snoop requests that are not in range. 239911130Sali.jafri@arm.com if (!inRange(pkt->getAddr())) { 240011051Sandreas.hansson@arm.com return 0; 240111051Sandreas.hansson@arm.com } 240211051Sandreas.hansson@arm.com 240311051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 240411127Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, false, false, false); 240511127Sandreas.hansson@arm.com return snoop_delay + lookupLatency * clockPeriod(); 240611051Sandreas.hansson@arm.com} 240711051Sandreas.hansson@arm.com 240811051Sandreas.hansson@arm.com 240911375Sandreas.hansson@arm.comQueueEntry* 241011375Sandreas.hansson@arm.comCache::getNextQueueEntry() 241111051Sandreas.hansson@arm.com{ 241211051Sandreas.hansson@arm.com // Check both MSHR queue and write buffer for potential requests, 241311051Sandreas.hansson@arm.com // note that null does not mean there is no request, it could 241411051Sandreas.hansson@arm.com // simply be that it is not ready 241511375Sandreas.hansson@arm.com MSHR *miss_mshr = mshrQueue.getNext(); 241611375Sandreas.hansson@arm.com WriteQueueEntry *wq_entry = writeBuffer.getNext(); 241711051Sandreas.hansson@arm.com 241811051Sandreas.hansson@arm.com // If we got a write buffer request ready, first priority is a 241911453Sandreas.hansson@arm.com // full write buffer, otherwise we favour the miss requests 242011453Sandreas.hansson@arm.com if (wq_entry && (writeBuffer.isFull() || !miss_mshr)) { 242111051Sandreas.hansson@arm.com // need to search MSHR queue for conflicting earlier miss. 242211051Sandreas.hansson@arm.com MSHR *conflict_mshr = 242311375Sandreas.hansson@arm.com mshrQueue.findPending(wq_entry->blkAddr, 242411375Sandreas.hansson@arm.com wq_entry->isSecure); 242511375Sandreas.hansson@arm.com 242611375Sandreas.hansson@arm.com if (conflict_mshr && conflict_mshr->order < wq_entry->order) { 242711051Sandreas.hansson@arm.com // Service misses in order until conflict is cleared. 242811051Sandreas.hansson@arm.com return conflict_mshr; 242911051Sandreas.hansson@arm.com 243011051Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 243111051Sandreas.hansson@arm.com } 243211051Sandreas.hansson@arm.com 243311051Sandreas.hansson@arm.com // No conflicts; issue write 243411375Sandreas.hansson@arm.com return wq_entry; 243511051Sandreas.hansson@arm.com } else if (miss_mshr) { 243611051Sandreas.hansson@arm.com // need to check for conflicting earlier writeback 243711375Sandreas.hansson@arm.com WriteQueueEntry *conflict_mshr = 243811051Sandreas.hansson@arm.com writeBuffer.findPending(miss_mshr->blkAddr, 243911051Sandreas.hansson@arm.com miss_mshr->isSecure); 244011051Sandreas.hansson@arm.com if (conflict_mshr) { 244111051Sandreas.hansson@arm.com // not sure why we don't check order here... it was in the 244211051Sandreas.hansson@arm.com // original code but commented out. 244311051Sandreas.hansson@arm.com 244411051Sandreas.hansson@arm.com // The only way this happens is if we are 244511051Sandreas.hansson@arm.com // doing a write and we didn't have permissions 244611051Sandreas.hansson@arm.com // then subsequently saw a writeback (owned got evicted) 244711051Sandreas.hansson@arm.com // We need to make sure to perform the writeback first 244811051Sandreas.hansson@arm.com // To preserve the dirty data, then we can issue the write 244911051Sandreas.hansson@arm.com 245011375Sandreas.hansson@arm.com // should we return wq_entry here instead? I.e. do we 245111051Sandreas.hansson@arm.com // have to flush writes in order? I don't think so... not 245211051Sandreas.hansson@arm.com // for Alpha anyway. Maybe for x86? 245311051Sandreas.hansson@arm.com return conflict_mshr; 245411051Sandreas.hansson@arm.com 245511051Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 245611051Sandreas.hansson@arm.com } 245711051Sandreas.hansson@arm.com 245811051Sandreas.hansson@arm.com // No conflicts; issue read 245911051Sandreas.hansson@arm.com return miss_mshr; 246011051Sandreas.hansson@arm.com } 246111051Sandreas.hansson@arm.com 246211051Sandreas.hansson@arm.com // fall through... no pending requests. Try a prefetch. 246311375Sandreas.hansson@arm.com assert(!miss_mshr && !wq_entry); 246411051Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 246511051Sandreas.hansson@arm.com // If we have a miss queue slot, we can try a prefetch 246611051Sandreas.hansson@arm.com PacketPtr pkt = prefetcher->getPacket(); 246711051Sandreas.hansson@arm.com if (pkt) { 246811892Snikos.nikoleris@arm.com Addr pf_addr = pkt->getBlockAddr(blkSize); 246911051Sandreas.hansson@arm.com if (!tags->findBlock(pf_addr, pkt->isSecure()) && 247011051Sandreas.hansson@arm.com !mshrQueue.findMatch(pf_addr, pkt->isSecure()) && 247111051Sandreas.hansson@arm.com !writeBuffer.findMatch(pf_addr, pkt->isSecure())) { 247211051Sandreas.hansson@arm.com // Update statistic on number of prefetches issued 247311051Sandreas.hansson@arm.com // (hwpf_mshr_misses) 247411051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 247511051Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 247611051Sandreas.hansson@arm.com 247711051Sandreas.hansson@arm.com // allocate an MSHR and return it, note 247811051Sandreas.hansson@arm.com // that we send the packet straight away, so do not 247911051Sandreas.hansson@arm.com // schedule the send 248011051Sandreas.hansson@arm.com return allocateMissBuffer(pkt, curTick(), false); 248111051Sandreas.hansson@arm.com } else { 248211051Sandreas.hansson@arm.com // free the request and packet 248311051Sandreas.hansson@arm.com delete pkt->req; 248411051Sandreas.hansson@arm.com delete pkt; 248511051Sandreas.hansson@arm.com } 248611051Sandreas.hansson@arm.com } 248711051Sandreas.hansson@arm.com } 248811051Sandreas.hansson@arm.com 248911375Sandreas.hansson@arm.com return nullptr; 249011051Sandreas.hansson@arm.com} 249111051Sandreas.hansson@arm.com 249211051Sandreas.hansson@arm.combool 249311130Sali.jafri@arm.comCache::isCachedAbove(PacketPtr pkt, bool is_timing) const 249411051Sandreas.hansson@arm.com{ 249511051Sandreas.hansson@arm.com if (!forwardSnoops) 249611051Sandreas.hansson@arm.com return false; 249711051Sandreas.hansson@arm.com // Mirroring the flow of HardPFReqs, the cache sends CleanEvict and 249811051Sandreas.hansson@arm.com // Writeback snoops into upper level caches to check for copies of the 249911051Sandreas.hansson@arm.com // same block. Using the BLOCK_CACHED flag with the Writeback/CleanEvict 250011051Sandreas.hansson@arm.com // packet, the cache can inform the crossbar below of presence or absence 250111051Sandreas.hansson@arm.com // of the block. 250211130Sali.jafri@arm.com if (is_timing) { 250311130Sali.jafri@arm.com Packet snoop_pkt(pkt, true, false); 250411130Sali.jafri@arm.com snoop_pkt.setExpressSnoop(); 250511130Sali.jafri@arm.com // Assert that packet is either Writeback or CleanEvict and not a 250611130Sali.jafri@arm.com // prefetch request because prefetch requests need an MSHR and may 250711130Sali.jafri@arm.com // generate a snoop response. 250812345Snikos.nikoleris@arm.com assert(pkt->isEviction() || pkt->cmd == MemCmd::WriteClean); 250911484Snikos.nikoleris@arm.com snoop_pkt.senderState = nullptr; 251011130Sali.jafri@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 251111130Sali.jafri@arm.com // Writeback/CleanEvict snoops do not generate a snoop response. 251211284Sandreas.hansson@arm.com assert(!(snoop_pkt.cacheResponding())); 251311130Sali.jafri@arm.com return snoop_pkt.isBlockCached(); 251411130Sali.jafri@arm.com } else { 251511130Sali.jafri@arm.com cpuSidePort->sendAtomicSnoop(pkt); 251611130Sali.jafri@arm.com return pkt->isBlockCached(); 251711130Sali.jafri@arm.com } 251811051Sandreas.hansson@arm.com} 251911051Sandreas.hansson@arm.com 252011375Sandreas.hansson@arm.comTick 252111375Sandreas.hansson@arm.comCache::nextQueueReadyTime() const 252211051Sandreas.hansson@arm.com{ 252311375Sandreas.hansson@arm.com Tick nextReady = std::min(mshrQueue.nextReadyTime(), 252411375Sandreas.hansson@arm.com writeBuffer.nextReadyTime()); 252511375Sandreas.hansson@arm.com 252611375Sandreas.hansson@arm.com // Don't signal prefetch ready time if no MSHRs available 252711375Sandreas.hansson@arm.com // Will signal once enoguh MSHRs are deallocated 252811375Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 252911375Sandreas.hansson@arm.com nextReady = std::min(nextReady, 253011375Sandreas.hansson@arm.com prefetcher->nextPrefetchReadyTime()); 253111051Sandreas.hansson@arm.com } 253211051Sandreas.hansson@arm.com 253311375Sandreas.hansson@arm.com return nextReady; 253411375Sandreas.hansson@arm.com} 253511375Sandreas.hansson@arm.com 253611375Sandreas.hansson@arm.combool 253711375Sandreas.hansson@arm.comCache::sendMSHRQueuePacket(MSHR* mshr) 253811375Sandreas.hansson@arm.com{ 253911375Sandreas.hansson@arm.com assert(mshr); 254011375Sandreas.hansson@arm.com 254111051Sandreas.hansson@arm.com // use request from 1st target 254211051Sandreas.hansson@arm.com PacketPtr tgt_pkt = mshr->getTarget()->pkt; 254311375Sandreas.hansson@arm.com 254411744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: MSHR %s\n", __func__, tgt_pkt->print()); 254511051Sandreas.hansson@arm.com 254611051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure); 254711051Sandreas.hansson@arm.com 254811051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::HardPFReq && forwardSnoops) { 254911375Sandreas.hansson@arm.com // we should never have hardware prefetches to allocated 255011375Sandreas.hansson@arm.com // blocks 255111484Snikos.nikoleris@arm.com assert(blk == nullptr); 255211375Sandreas.hansson@arm.com 255311051Sandreas.hansson@arm.com // We need to check the caches above us to verify that 255411051Sandreas.hansson@arm.com // they don't have a copy of this block in the dirty state 255511051Sandreas.hansson@arm.com // at the moment. Without this check we could get a stale 255611051Sandreas.hansson@arm.com // copy from memory that might get used in place of the 255711051Sandreas.hansson@arm.com // dirty one. 255811051Sandreas.hansson@arm.com Packet snoop_pkt(tgt_pkt, true, false); 255911051Sandreas.hansson@arm.com snoop_pkt.setExpressSnoop(); 256011275Sandreas.hansson@arm.com // We are sending this packet upwards, but if it hits we will 256111275Sandreas.hansson@arm.com // get a snoop response that we end up treating just like a 256211275Sandreas.hansson@arm.com // normal response, hence it needs the MSHR as its sender 256311275Sandreas.hansson@arm.com // state 256411051Sandreas.hansson@arm.com snoop_pkt.senderState = mshr; 256511051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 256611051Sandreas.hansson@arm.com 256711051Sandreas.hansson@arm.com // Check to see if the prefetch was squashed by an upper cache (to 256811051Sandreas.hansson@arm.com // prevent us from grabbing the line) or if a Check to see if a 256911051Sandreas.hansson@arm.com // writeback arrived between the time the prefetch was placed in 257011051Sandreas.hansson@arm.com // the MSHRs and when it was selected to be sent or if the 257111051Sandreas.hansson@arm.com // prefetch was squashed by an upper cache. 257211051Sandreas.hansson@arm.com 257311284Sandreas.hansson@arm.com // It is important to check cacheResponding before 257411284Sandreas.hansson@arm.com // prefetchSquashed. If another cache has committed to 257511284Sandreas.hansson@arm.com // responding, it will be sending a dirty response which will 257611284Sandreas.hansson@arm.com // arrive at the MSHR allocated for this request. Checking the 257711284Sandreas.hansson@arm.com // prefetchSquash first may result in the MSHR being 257811284Sandreas.hansson@arm.com // prematurely deallocated. 257911284Sandreas.hansson@arm.com if (snoop_pkt.cacheResponding()) { 258011276Sandreas.hansson@arm.com auto M5_VAR_USED r = outstandingSnoop.insert(snoop_pkt.req); 258111276Sandreas.hansson@arm.com assert(r.second); 258211284Sandreas.hansson@arm.com 258311284Sandreas.hansson@arm.com // if we are getting a snoop response with no sharers it 258411284Sandreas.hansson@arm.com // will be allocated as Modified 258511284Sandreas.hansson@arm.com bool pending_modified_resp = !snoop_pkt.hasSharers(); 258611284Sandreas.hansson@arm.com markInService(mshr, pending_modified_resp); 258711284Sandreas.hansson@arm.com 258811051Sandreas.hansson@arm.com DPRINTF(Cache, "Upward snoop of prefetch for addr" 258911051Sandreas.hansson@arm.com " %#x (%s) hit\n", 259011051Sandreas.hansson@arm.com tgt_pkt->getAddr(), tgt_pkt->isSecure()? "s": "ns"); 259111375Sandreas.hansson@arm.com return false; 259211051Sandreas.hansson@arm.com } 259311051Sandreas.hansson@arm.com 259411375Sandreas.hansson@arm.com if (snoop_pkt.isBlockCached()) { 259511051Sandreas.hansson@arm.com DPRINTF(Cache, "Block present, prefetch squashed by cache. " 259611051Sandreas.hansson@arm.com "Deallocating mshr target %#x.\n", 259711051Sandreas.hansson@arm.com mshr->blkAddr); 259811375Sandreas.hansson@arm.com 259911051Sandreas.hansson@arm.com // Deallocate the mshr target 260011375Sandreas.hansson@arm.com if (mshrQueue.forceDeallocateTarget(mshr)) { 260111277Sandreas.hansson@arm.com // Clear block if this deallocation resulted freed an 260211277Sandreas.hansson@arm.com // mshr when all had previously been utilized 260311375Sandreas.hansson@arm.com clearBlocked(Blocked_NoMSHRs); 260411051Sandreas.hansson@arm.com } 260512167Spau.cabre@metempsy.com 260612167Spau.cabre@metempsy.com // given that no response is expected, delete Request and Packet 260712167Spau.cabre@metempsy.com delete tgt_pkt->req; 260812167Spau.cabre@metempsy.com delete tgt_pkt; 260912167Spau.cabre@metempsy.com 261011375Sandreas.hansson@arm.com return false; 261111051Sandreas.hansson@arm.com } 261211051Sandreas.hansson@arm.com } 261311051Sandreas.hansson@arm.com 261411375Sandreas.hansson@arm.com // either a prefetch that is not present upstream, or a normal 261511375Sandreas.hansson@arm.com // MSHR request, proceed to get the packet to send downstream 261611452Sandreas.hansson@arm.com PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable()); 261711375Sandreas.hansson@arm.com 261811484Snikos.nikoleris@arm.com mshr->isForward = (pkt == nullptr); 261911375Sandreas.hansson@arm.com 262011375Sandreas.hansson@arm.com if (mshr->isForward) { 262111375Sandreas.hansson@arm.com // not a cache block request, but a response is expected 262211375Sandreas.hansson@arm.com // make copy of current packet to forward, keep current 262311375Sandreas.hansson@arm.com // copy for response handling 262411375Sandreas.hansson@arm.com pkt = new Packet(tgt_pkt, false, true); 262511375Sandreas.hansson@arm.com assert(!pkt->isWrite()); 262611375Sandreas.hansson@arm.com } 262711375Sandreas.hansson@arm.com 262811375Sandreas.hansson@arm.com // play it safe and append (rather than set) the sender state, 262911375Sandreas.hansson@arm.com // as forwarded packets may already have existing state 263011375Sandreas.hansson@arm.com pkt->pushSenderState(mshr); 263111375Sandreas.hansson@arm.com 263212349Snikos.nikoleris@arm.com if (pkt->isClean() && blk && blk->isDirty()) { 263312349Snikos.nikoleris@arm.com // A cache clean opearation is looking for a dirty block. Mark 263412349Snikos.nikoleris@arm.com // the packet so that the destination xbar can determine that 263512349Snikos.nikoleris@arm.com // there will be a follow-up write packet as well. 263612349Snikos.nikoleris@arm.com pkt->setSatisfied(); 263712349Snikos.nikoleris@arm.com } 263812349Snikos.nikoleris@arm.com 263911375Sandreas.hansson@arm.com if (!memSidePort->sendTimingReq(pkt)) { 264011375Sandreas.hansson@arm.com // we are awaiting a retry, but we 264111375Sandreas.hansson@arm.com // delete the packet and will be creating a new packet 264211375Sandreas.hansson@arm.com // when we get the opportunity 264311375Sandreas.hansson@arm.com delete pkt; 264411375Sandreas.hansson@arm.com 264511375Sandreas.hansson@arm.com // note that we have now masked any requestBus and 264611375Sandreas.hansson@arm.com // schedSendEvent (we will wait for a retry before 264711375Sandreas.hansson@arm.com // doing anything), and this is so even if we do not 264811375Sandreas.hansson@arm.com // care about this packet and might override it before 264911375Sandreas.hansson@arm.com // it gets retried 265011375Sandreas.hansson@arm.com return true; 265111375Sandreas.hansson@arm.com } else { 265211375Sandreas.hansson@arm.com // As part of the call to sendTimingReq the packet is 265311375Sandreas.hansson@arm.com // forwarded to all neighbouring caches (and any caches 265411375Sandreas.hansson@arm.com // above them) as a snoop. Thus at this point we know if 265511375Sandreas.hansson@arm.com // any of the neighbouring caches are responding, and if 265611375Sandreas.hansson@arm.com // so, we know it is dirty, and we can determine if it is 265711375Sandreas.hansson@arm.com // being passed as Modified, making our MSHR the ordering 265811375Sandreas.hansson@arm.com // point 265911375Sandreas.hansson@arm.com bool pending_modified_resp = !pkt->hasSharers() && 266011375Sandreas.hansson@arm.com pkt->cacheResponding(); 266111375Sandreas.hansson@arm.com markInService(mshr, pending_modified_resp); 266212349Snikos.nikoleris@arm.com if (pkt->isClean() && blk && blk->isDirty()) { 266312349Snikos.nikoleris@arm.com // A cache clean opearation is looking for a dirty 266412349Snikos.nikoleris@arm.com // block. If a dirty block is encountered a WriteClean 266512349Snikos.nikoleris@arm.com // will update any copies to the path to the memory 266612349Snikos.nikoleris@arm.com // until the point of reference. 266712349Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n", 266812349Snikos.nikoleris@arm.com __func__, pkt->print(), blk->print()); 266912351Snikos.nikoleris@arm.com PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), 267012351Snikos.nikoleris@arm.com pkt->id); 267112349Snikos.nikoleris@arm.com PacketList writebacks; 267212349Snikos.nikoleris@arm.com writebacks.push_back(wb_pkt); 267312349Snikos.nikoleris@arm.com doWritebacks(writebacks, 0); 267412349Snikos.nikoleris@arm.com } 267512349Snikos.nikoleris@arm.com 267611375Sandreas.hansson@arm.com return false; 267711375Sandreas.hansson@arm.com } 267811375Sandreas.hansson@arm.com} 267911375Sandreas.hansson@arm.com 268011375Sandreas.hansson@arm.combool 268111375Sandreas.hansson@arm.comCache::sendWriteQueuePacket(WriteQueueEntry* wq_entry) 268211375Sandreas.hansson@arm.com{ 268311375Sandreas.hansson@arm.com assert(wq_entry); 268411375Sandreas.hansson@arm.com 268511375Sandreas.hansson@arm.com // always a single target for write queue entries 268611375Sandreas.hansson@arm.com PacketPtr tgt_pkt = wq_entry->getTarget()->pkt; 268711375Sandreas.hansson@arm.com 268811744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: write %s\n", __func__, tgt_pkt->print()); 268911375Sandreas.hansson@arm.com 269011453Sandreas.hansson@arm.com // forward as is, both for evictions and uncacheable writes 269111453Sandreas.hansson@arm.com if (!memSidePort->sendTimingReq(tgt_pkt)) { 269211375Sandreas.hansson@arm.com // note that we have now masked any requestBus and 269311375Sandreas.hansson@arm.com // schedSendEvent (we will wait for a retry before 269411375Sandreas.hansson@arm.com // doing anything), and this is so even if we do not 269511375Sandreas.hansson@arm.com // care about this packet and might override it before 269611375Sandreas.hansson@arm.com // it gets retried 269711375Sandreas.hansson@arm.com return true; 269811375Sandreas.hansson@arm.com } else { 269911375Sandreas.hansson@arm.com markInService(wq_entry); 270011375Sandreas.hansson@arm.com return false; 270111051Sandreas.hansson@arm.com } 270211051Sandreas.hansson@arm.com} 270311051Sandreas.hansson@arm.com 270411051Sandreas.hansson@arm.comvoid 270511051Sandreas.hansson@arm.comCache::serialize(CheckpointOut &cp) const 270611051Sandreas.hansson@arm.com{ 270711051Sandreas.hansson@arm.com bool dirty(isDirty()); 270811051Sandreas.hansson@arm.com 270911051Sandreas.hansson@arm.com if (dirty) { 271011051Sandreas.hansson@arm.com warn("*** The cache still contains dirty data. ***\n"); 271111051Sandreas.hansson@arm.com warn(" Make sure to drain the system using the correct flags.\n"); 271211483Snikos.nikoleris@arm.com warn(" This checkpoint will not restore correctly and dirty data " 271311483Snikos.nikoleris@arm.com " in the cache will be lost!\n"); 271411051Sandreas.hansson@arm.com } 271511051Sandreas.hansson@arm.com 271611051Sandreas.hansson@arm.com // Since we don't checkpoint the data in the cache, any dirty data 271711051Sandreas.hansson@arm.com // will be lost when restoring from a checkpoint of a system that 271811051Sandreas.hansson@arm.com // wasn't drained properly. Flag the checkpoint as invalid if the 271911051Sandreas.hansson@arm.com // cache contains dirty data. 272011051Sandreas.hansson@arm.com bool bad_checkpoint(dirty); 272111051Sandreas.hansson@arm.com SERIALIZE_SCALAR(bad_checkpoint); 272211051Sandreas.hansson@arm.com} 272311051Sandreas.hansson@arm.com 272411051Sandreas.hansson@arm.comvoid 272511051Sandreas.hansson@arm.comCache::unserialize(CheckpointIn &cp) 272611051Sandreas.hansson@arm.com{ 272711051Sandreas.hansson@arm.com bool bad_checkpoint; 272811051Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(bad_checkpoint); 272911051Sandreas.hansson@arm.com if (bad_checkpoint) { 273011051Sandreas.hansson@arm.com fatal("Restoring from checkpoints with dirty caches is not supported " 273111051Sandreas.hansson@arm.com "in the classic memory system. Please remove any caches or " 273211051Sandreas.hansson@arm.com " drain them properly before taking checkpoints.\n"); 273311051Sandreas.hansson@arm.com } 273411051Sandreas.hansson@arm.com} 273511051Sandreas.hansson@arm.com 273611051Sandreas.hansson@arm.com/////////////// 273711051Sandreas.hansson@arm.com// 273811051Sandreas.hansson@arm.com// CpuSidePort 273911051Sandreas.hansson@arm.com// 274011051Sandreas.hansson@arm.com/////////////// 274111051Sandreas.hansson@arm.com 274211051Sandreas.hansson@arm.comAddrRangeList 274311051Sandreas.hansson@arm.comCache::CpuSidePort::getAddrRanges() const 274411051Sandreas.hansson@arm.com{ 274511051Sandreas.hansson@arm.com return cache->getAddrRanges(); 274611051Sandreas.hansson@arm.com} 274711051Sandreas.hansson@arm.com 274811051Sandreas.hansson@arm.combool 274912343Snikos.nikoleris@arm.comCache::CpuSidePort::tryTiming(PacketPtr pkt) 275012343Snikos.nikoleris@arm.com{ 275112343Snikos.nikoleris@arm.com assert(!cache->system->bypassCaches()); 275212343Snikos.nikoleris@arm.com 275312343Snikos.nikoleris@arm.com // always let express snoop packets through if even if blocked 275412343Snikos.nikoleris@arm.com if (pkt->isExpressSnoop()) { 275512343Snikos.nikoleris@arm.com return true; 275612343Snikos.nikoleris@arm.com } else if (isBlocked() || mustSendRetry) { 275712343Snikos.nikoleris@arm.com // either already committed to send a retry, or blocked 275812343Snikos.nikoleris@arm.com mustSendRetry = true; 275912343Snikos.nikoleris@arm.com return false; 276012343Snikos.nikoleris@arm.com } 276112343Snikos.nikoleris@arm.com mustSendRetry = false; 276212343Snikos.nikoleris@arm.com return true; 276312343Snikos.nikoleris@arm.com} 276412343Snikos.nikoleris@arm.com 276512343Snikos.nikoleris@arm.combool 276611051Sandreas.hansson@arm.comCache::CpuSidePort::recvTimingReq(PacketPtr pkt) 276711051Sandreas.hansson@arm.com{ 276811051Sandreas.hansson@arm.com assert(!cache->system->bypassCaches()); 276911051Sandreas.hansson@arm.com 277011334Sandreas.hansson@arm.com // always let express snoop packets through if even if blocked 277111334Sandreas.hansson@arm.com if (pkt->isExpressSnoop()) { 277211051Sandreas.hansson@arm.com bool M5_VAR_USED bypass_success = cache->recvTimingReq(pkt); 277311051Sandreas.hansson@arm.com assert(bypass_success); 277411051Sandreas.hansson@arm.com return true; 277511051Sandreas.hansson@arm.com } 277611051Sandreas.hansson@arm.com 277712343Snikos.nikoleris@arm.com return tryTiming(pkt) && cache->recvTimingReq(pkt); 277811051Sandreas.hansson@arm.com} 277911051Sandreas.hansson@arm.com 278011051Sandreas.hansson@arm.comTick 278111051Sandreas.hansson@arm.comCache::CpuSidePort::recvAtomic(PacketPtr pkt) 278211051Sandreas.hansson@arm.com{ 278311051Sandreas.hansson@arm.com return cache->recvAtomic(pkt); 278411051Sandreas.hansson@arm.com} 278511051Sandreas.hansson@arm.com 278611051Sandreas.hansson@arm.comvoid 278711051Sandreas.hansson@arm.comCache::CpuSidePort::recvFunctional(PacketPtr pkt) 278811051Sandreas.hansson@arm.com{ 278911051Sandreas.hansson@arm.com // functional request 279011051Sandreas.hansson@arm.com cache->functionalAccess(pkt, true); 279111051Sandreas.hansson@arm.com} 279211051Sandreas.hansson@arm.com 279311051Sandreas.hansson@arm.comCache:: 279411051Sandreas.hansson@arm.comCpuSidePort::CpuSidePort(const std::string &_name, Cache *_cache, 279511051Sandreas.hansson@arm.com const std::string &_label) 279611051Sandreas.hansson@arm.com : BaseCache::CacheSlavePort(_name, _cache, _label), cache(_cache) 279711051Sandreas.hansson@arm.com{ 279811051Sandreas.hansson@arm.com} 279911051Sandreas.hansson@arm.com 280011053Sandreas.hansson@arm.comCache* 280111053Sandreas.hansson@arm.comCacheParams::create() 280211053Sandreas.hansson@arm.com{ 280311053Sandreas.hansson@arm.com assert(tags); 280411053Sandreas.hansson@arm.com 280511053Sandreas.hansson@arm.com return new Cache(this); 280611053Sandreas.hansson@arm.com} 280711051Sandreas.hansson@arm.com/////////////// 280811051Sandreas.hansson@arm.com// 280911051Sandreas.hansson@arm.com// MemSidePort 281011051Sandreas.hansson@arm.com// 281111051Sandreas.hansson@arm.com/////////////// 281211051Sandreas.hansson@arm.com 281311051Sandreas.hansson@arm.combool 281411051Sandreas.hansson@arm.comCache::MemSidePort::recvTimingResp(PacketPtr pkt) 281511051Sandreas.hansson@arm.com{ 281611051Sandreas.hansson@arm.com cache->recvTimingResp(pkt); 281711051Sandreas.hansson@arm.com return true; 281811051Sandreas.hansson@arm.com} 281911051Sandreas.hansson@arm.com 282011051Sandreas.hansson@arm.com// Express snooping requests to memside port 282111051Sandreas.hansson@arm.comvoid 282211051Sandreas.hansson@arm.comCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt) 282311051Sandreas.hansson@arm.com{ 282411051Sandreas.hansson@arm.com // handle snooping requests 282511051Sandreas.hansson@arm.com cache->recvTimingSnoopReq(pkt); 282611051Sandreas.hansson@arm.com} 282711051Sandreas.hansson@arm.com 282811051Sandreas.hansson@arm.comTick 282911051Sandreas.hansson@arm.comCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt) 283011051Sandreas.hansson@arm.com{ 283111051Sandreas.hansson@arm.com return cache->recvAtomicSnoop(pkt); 283211051Sandreas.hansson@arm.com} 283311051Sandreas.hansson@arm.com 283411051Sandreas.hansson@arm.comvoid 283511051Sandreas.hansson@arm.comCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt) 283611051Sandreas.hansson@arm.com{ 283711051Sandreas.hansson@arm.com // functional snoop (note that in contrast to atomic we don't have 283811051Sandreas.hansson@arm.com // a specific functionalSnoop method, as they have the same 283911051Sandreas.hansson@arm.com // behaviour regardless) 284011051Sandreas.hansson@arm.com cache->functionalAccess(pkt, false); 284111051Sandreas.hansson@arm.com} 284211051Sandreas.hansson@arm.com 284311051Sandreas.hansson@arm.comvoid 284411051Sandreas.hansson@arm.comCache::CacheReqPacketQueue::sendDeferredPacket() 284511051Sandreas.hansson@arm.com{ 284611051Sandreas.hansson@arm.com // sanity check 284711051Sandreas.hansson@arm.com assert(!waitingOnRetry); 284811051Sandreas.hansson@arm.com 284911051Sandreas.hansson@arm.com // there should never be any deferred request packets in the 285011051Sandreas.hansson@arm.com // queue, instead we resly on the cache to provide the packets 285111051Sandreas.hansson@arm.com // from the MSHR queue or write queue 285211051Sandreas.hansson@arm.com assert(deferredPacketReadyTime() == MaxTick); 285311051Sandreas.hansson@arm.com 285411051Sandreas.hansson@arm.com // check for request packets (requests & writebacks) 285511375Sandreas.hansson@arm.com QueueEntry* entry = cache.getNextQueueEntry(); 285611375Sandreas.hansson@arm.com 285711375Sandreas.hansson@arm.com if (!entry) { 285811051Sandreas.hansson@arm.com // can happen if e.g. we attempt a writeback and fail, but 285911051Sandreas.hansson@arm.com // before the retry, the writeback is eliminated because 286011051Sandreas.hansson@arm.com // we snoop another cache's ReadEx. 286111051Sandreas.hansson@arm.com } else { 286211051Sandreas.hansson@arm.com // let our snoop responses go first if there are responses to 286311375Sandreas.hansson@arm.com // the same addresses 286411375Sandreas.hansson@arm.com if (checkConflictingSnoop(entry->blkAddr)) { 286511051Sandreas.hansson@arm.com return; 286611051Sandreas.hansson@arm.com } 286711375Sandreas.hansson@arm.com waitingOnRetry = entry->sendPacket(cache); 286811051Sandreas.hansson@arm.com } 286911051Sandreas.hansson@arm.com 287011051Sandreas.hansson@arm.com // if we succeeded and are not waiting for a retry, schedule the 287111375Sandreas.hansson@arm.com // next send considering when the next queue is ready, note that 287211051Sandreas.hansson@arm.com // snoop responses have their own packet queue and thus schedule 287311051Sandreas.hansson@arm.com // their own events 287411051Sandreas.hansson@arm.com if (!waitingOnRetry) { 287511375Sandreas.hansson@arm.com schedSendEvent(cache.nextQueueReadyTime()); 287611051Sandreas.hansson@arm.com } 287711051Sandreas.hansson@arm.com} 287811051Sandreas.hansson@arm.com 287911051Sandreas.hansson@arm.comCache:: 288011051Sandreas.hansson@arm.comMemSidePort::MemSidePort(const std::string &_name, Cache *_cache, 288111051Sandreas.hansson@arm.com const std::string &_label) 288211051Sandreas.hansson@arm.com : BaseCache::CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue), 288311051Sandreas.hansson@arm.com _reqQueue(*_cache, *this, _snoopRespQueue, _label), 288411051Sandreas.hansson@arm.com _snoopRespQueue(*_cache, *this, _label), cache(_cache) 288511051Sandreas.hansson@arm.com{ 288611051Sandreas.hansson@arm.com} 2887