base.hh revision 9850
12SN/A/* 21762SN/A * Copyright (c) 2012 ARM Limited 32SN/A * All rights reserved. 42SN/A * 52SN/A * The license below extends only to copyright in the software and shall 62SN/A * not be construed as granting a license to any other intellectual 72SN/A * property including but not limited to intellectual property relating 82SN/A * to a hardware implementation of the functionality of the software 92SN/A * licensed hereunder. You may use the software subject to the license 102SN/A * terms below provided that you ensure that this notice is replicated 112SN/A * unmodified and in its entirety in all distributions of the software, 122SN/A * modified or unmodified, in source code or in binary form. 132SN/A * 142SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292665Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321717SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331717SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37707SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381858SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3956SN/A * 402856Srdreslin@umich.edu * Authors: Erik Hallnor 412109SN/A * Steve Reinhardt 422SN/A * Ron Dreslinski 433520Sgblack@eecs.umich.edu */ 443520Sgblack@eecs.umich.edu 453520Sgblack@eecs.umich.edu/** 463520Sgblack@eecs.umich.edu * @file 472190SN/A * Declares a basic cache interface BaseCache. 482315SN/A */ 492680Sktlim@umich.edu 502SN/A#ifndef __BASE_CACHE_HH__ 512856Srdreslin@umich.edu#define __BASE_CACHE_HH__ 522SN/A 532356SN/A#include <algorithm> 542356SN/A#include <list> 552356SN/A#include <string> 562356SN/A#include <vector> 572356SN/A 582356SN/A#include "base/misc.hh" 592356SN/A#include "base/statistics.hh" 602356SN/A#include "base/trace.hh" 613126Sktlim@umich.edu#include "base/types.hh" 622356SN/A#include "debug/Cache.hh" 632356SN/A#include "debug/CachePort.hh" 642356SN/A#include "mem/cache/mshr_queue.hh" 652356SN/A#include "mem/mem_object.hh" 662356SN/A#include "mem/packet.hh" 672356SN/A#include "mem/qport.hh" 682856Srdreslin@umich.edu#include "mem/request.hh" 692SN/A#include "params/BaseCache.hh" 701634SN/A#include "sim/eventq.hh" 711634SN/A#include "sim/full_system.hh" 721695SN/A#include "sim/sim_exit.hh" 731634SN/A#include "sim/system.hh" 741634SN/A 752359SN/Aclass MSHR; 761695SN/A/** 771695SN/A * A basic cache interface. Implements some common functions for speed. 781695SN/A */ 791634SN/Aclass BaseCache : public MemObject 803495Sktlim@umich.edu{ 813495Sktlim@umich.edu /** 823495Sktlim@umich.edu * Indexes to enumerate the MSHR queues. 833495Sktlim@umich.edu */ 843495Sktlim@umich.edu enum MSHRQueueIndex { 853495Sktlim@umich.edu MSHRQueue_MSHRs, 863495Sktlim@umich.edu MSHRQueue_WriteBuffer 873495Sktlim@umich.edu }; 883495Sktlim@umich.edu 893495Sktlim@umich.edu public: 903495Sktlim@umich.edu /** 913495Sktlim@umich.edu * Reasons for caches to be blocked. 923495Sktlim@umich.edu */ 933495Sktlim@umich.edu enum BlockedCause { 941858SN/A Blocked_NoMSHRs = MSHRQueue_MSHRs, 952SN/A Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, 963520Sgblack@eecs.umich.edu Blocked_NoTargets, 973520Sgblack@eecs.umich.edu NUM_BLOCKED_CAUSES 983520Sgblack@eecs.umich.edu }; 992SN/A 1002SN/A /** 1012SN/A * Reasons for cache to request a bus. 1022SN/A */ 1032SN/A enum RequestCause { 1041133SN/A Request_MSHR = MSHRQueue_MSHRs, 1052SN/A Request_WB = MSHRQueue_WriteBuffer, 1063521Sgblack@eecs.umich.edu Request_PF, 1073521Sgblack@eecs.umich.edu NUM_REQUEST_CAUSES 1081917SN/A }; 1091917SN/A 1101917SN/A protected: 1111917SN/A 1121917SN/A /** 1131917SN/A * A cache master port is used for the memory-side port of the 1141917SN/A * cache, and in addition to the basic timing port that only sends 1151917SN/A * response packets through a transmit list, it also offers the 1161917SN/A * ability to schedule and send request packets (requests & 1171917SN/A * writebacks). The send event is scheduled through requestBus, 1181917SN/A * and the sendDeferredPacket of the timing port is modified to 1191917SN/A * consider both the transmit list and the requests from the MSHR. 1202SN/A */ 1212SN/A class CacheMasterPort : public QueuedMasterPort 1222SN/A { 1232680Sktlim@umich.edu 1242SN/A public: 1252SN/A 126393SN/A /** 127393SN/A * Schedule a send of a request packet (from the MSHR). Note 128393SN/A * that we could already have a retry or a transmit list of 129393SN/A * responses outstanding. 130393SN/A */ 131393SN/A void requestBus(RequestCause cause, Tick time) 132393SN/A { 133393SN/A DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause); 134393SN/A queue.schedSendEvent(time); 135393SN/A } 136393SN/A 137393SN/A protected: 138393SN/A 139393SN/A CacheMasterPort(const std::string &_name, BaseCache *_cache, 1402SN/A MasterPacketQueue &_queue) : 1412SN/A QueuedMasterPort(_name, _cache, _queue) 1421400SN/A { } 1431400SN/A 1441400SN/A /** 1451400SN/A * Memory-side port always snoops. 1461400SN/A * 1471400SN/A * @return always true 1481400SN/A */ 1491400SN/A virtual bool isSnooping() const { return true; } 1501400SN/A }; 1511695SN/A 1521400SN/A /** 1531400SN/A * A cache slave port is used for the CPU-side port of the cache, 1542378SN/A * and it is basically a simple timing port that uses a transmit 1553170Sstever@eecs.umich.edu * list for responses to the CPU (or connected master). In 1563661Srdreslin@umich.edu * addition, it has the functionality to block the port for 1571858SN/A * incoming requests. If blocked, the port will issue a retry once 1581917SN/A * unblocked. 1593617Sbinkertn@umich.edu */ 1603617Sbinkertn@umich.edu class CacheSlavePort : public QueuedSlavePort 1613617Sbinkertn@umich.edu { 1623617Sbinkertn@umich.edu 1631400SN/A public: 1642356SN/A 1652315SN/A /** Do not accept any new requests. */ 1661917SN/A void setBlocked(); 1671917SN/A 1681400SN/A /** Return to normal operation and accept new requests. */ 1692SN/A void clearBlocked(); 1701400SN/A 1712SN/A protected: 1721400SN/A 1731191SN/A CacheSlavePort(const std::string &_name, BaseCache *_cache, 1742SN/A const std::string &_label); 1751129SN/A 1761917SN/A /** A normal packet queue used to store responses. */ 1772SN/A SlavePacketQueue queue; 1782SN/A 1792103SN/A bool blocked; 1802103SN/A 1812680Sktlim@umich.edu bool mustSendRetry; 182180SN/A 1831492SN/A private: 1841492SN/A 1852798Sktlim@umich.edu EventWrapper<SlavePort, &SlavePort::sendRetry> sendRetryEvent; 186180SN/A 187180SN/A }; 188180SN/A 189180SN/A CacheSlavePort *cpuSidePort; 190180SN/A CacheMasterPort *memSidePort; 191124SN/A 192124SN/A protected: 193124SN/A 194124SN/A /** Miss status registers */ 1952SN/A MSHRQueue mshrQueue; 1962SN/A 197124SN/A /** Write/writeback buffer */ 198124SN/A MSHRQueue writeBuffer; 199124SN/A 200124SN/A MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size, 201124SN/A PacketPtr pkt, Tick time, bool requestBus) 202503SN/A { 2032SN/A MSHR *mshr = mq->allocate(addr, size, pkt, time, order++); 204124SN/A 205124SN/A if (mq->isFull()) { 206124SN/A setBlocked((BlockedCause)mq->index); 207124SN/A } 208124SN/A 209124SN/A if (requestBus) { 210124SN/A requestMemSideBus((RequestCause)mq->index, time); 2112SN/A } 212921SN/A 2133661Srdreslin@umich.edu return mshr; 2143661Srdreslin@umich.edu } 2152378SN/A 216921SN/A void markInServiceInternal(MSHR *mshr, PacketPtr pkt) 217921SN/A { 218921SN/A MSHRQueue *mq = mshr->queue; 219921SN/A bool wasFull = mq->isFull(); 220921SN/A mq->markInService(mshr, pkt); 221921SN/A if (wasFull && !mq->isFull()) { 222921SN/A clearBlocked((BlockedCause)mq->index); 223921SN/A } 224921SN/A } 225921SN/A 226921SN/A /** 227921SN/A * Write back dirty blocks in the cache using functional accesses. 228921SN/A */ 2292SN/A virtual void memWriteback() = 0; 2302SN/A /** 231124SN/A * Invalidates all blocks in the cache. 232124SN/A * 233124SN/A * @warn Dirty cache lines will not be written back to 234124SN/A * memory. Make sure to call functionalWriteback() first if you 2352SN/A * want the to write them to memory. 2362SN/A */ 237707SN/A virtual void memInvalidate() = 0; 238707SN/A /** 2391191SN/A * Determine if there are any dirty blocks in the cache. 2401191SN/A * 2411191SN/A * \return true if at least one block is dirty, false otherwise. 2421191SN/A */ 2431191SN/A virtual bool isDirty() const = 0; 2441191SN/A 2451191SN/A /** Block size of this cache */ 2461191SN/A const unsigned blkSize; 2471191SN/A 2481191SN/A /** 2491191SN/A * The latency of a hit in this device. 2501191SN/A */ 2511191SN/A const Cycles hitLatency; 2521191SN/A 2531191SN/A /** 2541191SN/A * The latency of sending reponse to its upper level cache/core on a 2551191SN/A * linefill. In most contemporary processors, the return path on a cache 2562SN/A * miss is much quicker that the hit latency. The responseLatency parameter 2572SN/A * tries to capture this latency. 2582SN/A */ 2592SN/A const Cycles responseLatency; 2602SN/A 261707SN/A /** The number of targets for each MSHR. */ 262707SN/A const int numTarget; 263707SN/A 264707SN/A /** Do we forward snoops from mem side port through to cpu side port? */ 265707SN/A const bool forwardSnoops; 266707SN/A 267707SN/A /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should 268707SN/A * never try to forward ownership and similar optimizations to the cpu 269707SN/A * side */ 270707SN/A const bool isTopLevel; 271707SN/A 272707SN/A /** 273707SN/A * Bit vector of the blocking reasons for the access path. 274729SN/A * @sa #BlockedCause 2752SN/A */ 2762SN/A uint8_t blocked; 2771717SN/A 278 /** Increasing order number assigned to each incoming request. */ 279 uint64_t order; 280 281 /** Stores time the cache blocked for statistics. */ 282 Cycles blockedCycle; 283 284 /** Pointer to the MSHR that has no targets. */ 285 MSHR *noTargetMSHR; 286 287 /** The number of misses to trigger an exit event. */ 288 Counter missCount; 289 290 /** 291 * The address range to which the cache responds on the CPU side. 292 * Normally this is all possible memory addresses. */ 293 const AddrRangeList addrRanges; 294 295 public: 296 /** System we are currently operating in. */ 297 System *system; 298 299 // Statistics 300 /** 301 * @addtogroup CacheStatistics 302 * @{ 303 */ 304 305 /** Number of hits per thread for each type of command. @sa Packet::Command */ 306 Stats::Vector hits[MemCmd::NUM_MEM_CMDS]; 307 /** Number of hits for demand accesses. */ 308 Stats::Formula demandHits; 309 /** Number of hit for all accesses. */ 310 Stats::Formula overallHits; 311 312 /** Number of misses per thread for each type of command. @sa Packet::Command */ 313 Stats::Vector misses[MemCmd::NUM_MEM_CMDS]; 314 /** Number of misses for demand accesses. */ 315 Stats::Formula demandMisses; 316 /** Number of misses for all accesses. */ 317 Stats::Formula overallMisses; 318 319 /** 320 * Total number of cycles per thread/command spent waiting for a miss. 321 * Used to calculate the average miss latency. 322 */ 323 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS]; 324 /** Total number of cycles spent waiting for demand misses. */ 325 Stats::Formula demandMissLatency; 326 /** Total number of cycles spent waiting for all misses. */ 327 Stats::Formula overallMissLatency; 328 329 /** The number of accesses per command and thread. */ 330 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS]; 331 /** The number of demand accesses. */ 332 Stats::Formula demandAccesses; 333 /** The number of overall accesses. */ 334 Stats::Formula overallAccesses; 335 336 /** The miss rate per command and thread. */ 337 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS]; 338 /** The miss rate of all demand accesses. */ 339 Stats::Formula demandMissRate; 340 /** The miss rate for all accesses. */ 341 Stats::Formula overallMissRate; 342 343 /** The average miss latency per command and thread. */ 344 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS]; 345 /** The average miss latency for demand misses. */ 346 Stats::Formula demandAvgMissLatency; 347 /** The average miss latency for all misses. */ 348 Stats::Formula overallAvgMissLatency; 349 350 /** The total number of cycles blocked for each blocked cause. */ 351 Stats::Vector blocked_cycles; 352 /** The number of times this cache blocked for each blocked cause. */ 353 Stats::Vector blocked_causes; 354 355 /** The average number of cycles blocked for each blocked cause. */ 356 Stats::Formula avg_blocked; 357 358 /** The number of fast writes (WH64) performed. */ 359 Stats::Scalar fastWrites; 360 361 /** The number of cache copies performed. */ 362 Stats::Scalar cacheCopies; 363 364 /** Number of blocks written back per thread. */ 365 Stats::Vector writebacks; 366 367 /** Number of misses that hit in the MSHRs per command and thread. */ 368 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS]; 369 /** Demand misses that hit in the MSHRs. */ 370 Stats::Formula demandMshrHits; 371 /** Total number of misses that hit in the MSHRs. */ 372 Stats::Formula overallMshrHits; 373 374 /** Number of misses that miss in the MSHRs, per command and thread. */ 375 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS]; 376 /** Demand misses that miss in the MSHRs. */ 377 Stats::Formula demandMshrMisses; 378 /** Total number of misses that miss in the MSHRs. */ 379 Stats::Formula overallMshrMisses; 380 381 /** Number of misses that miss in the MSHRs, per command and thread. */ 382 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS]; 383 /** Total number of misses that miss in the MSHRs. */ 384 Stats::Formula overallMshrUncacheable; 385 386 /** Total cycle latency of each MSHR miss, per command and thread. */ 387 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS]; 388 /** Total cycle latency of demand MSHR misses. */ 389 Stats::Formula demandMshrMissLatency; 390 /** Total cycle latency of overall MSHR misses. */ 391 Stats::Formula overallMshrMissLatency; 392 393 /** Total cycle latency of each MSHR miss, per command and thread. */ 394 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; 395 /** Total cycle latency of overall MSHR misses. */ 396 Stats::Formula overallMshrUncacheableLatency; 397 398#if 0 399 /** The total number of MSHR accesses per command and thread. */ 400 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; 401 /** The total number of demand MSHR accesses. */ 402 Stats::Formula demandMshrAccesses; 403 /** The total number of MSHR accesses. */ 404 Stats::Formula overallMshrAccesses; 405#endif 406 407 /** The miss rate in the MSHRs pre command and thread. */ 408 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; 409 /** The demand miss rate in the MSHRs. */ 410 Stats::Formula demandMshrMissRate; 411 /** The overall miss rate in the MSHRs. */ 412 Stats::Formula overallMshrMissRate; 413 414 /** The average latency of an MSHR miss, per command and thread. */ 415 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS]; 416 /** The average latency of a demand MSHR miss. */ 417 Stats::Formula demandAvgMshrMissLatency; 418 /** The average overall latency of an MSHR miss. */ 419 Stats::Formula overallAvgMshrMissLatency; 420 421 /** The average latency of an MSHR miss, per command and thread. */ 422 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; 423 /** The average overall latency of an MSHR miss. */ 424 Stats::Formula overallAvgMshrUncacheableLatency; 425 426 /** The number of times a thread hit its MSHR cap. */ 427 Stats::Vector mshr_cap_events; 428 /** The number of times software prefetches caused the MSHR to block. */ 429 Stats::Vector soft_prefetch_mshr_full; 430 431 Stats::Scalar mshr_no_allocate_misses; 432 433 /** 434 * @} 435 */ 436 437 /** 438 * Register stats for this object. 439 */ 440 virtual void regStats(); 441 442 public: 443 typedef BaseCacheParams Params; 444 BaseCache(const Params *p); 445 ~BaseCache() {} 446 447 virtual void init(); 448 449 virtual BaseMasterPort &getMasterPort(const std::string &if_name, 450 PortID idx = InvalidPortID); 451 virtual BaseSlavePort &getSlavePort(const std::string &if_name, 452 PortID idx = InvalidPortID); 453 454 /** 455 * Query block size of a cache. 456 * @return The block size 457 */ 458 unsigned 459 getBlockSize() const 460 { 461 return blkSize; 462 } 463 464 465 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); } 466 467 468 const AddrRangeList &getAddrRanges() const { return addrRanges; } 469 470 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus) 471 { 472 assert(!pkt->req->isUncacheable()); 473 return allocateBufferInternal(&mshrQueue, 474 blockAlign(pkt->getAddr()), blkSize, 475 pkt, time, requestBus); 476 } 477 478 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus) 479 { 480 assert(pkt->isWrite() && !pkt->isRead()); 481 return allocateBufferInternal(&writeBuffer, 482 pkt->getAddr(), pkt->getSize(), 483 pkt, time, requestBus); 484 } 485 486 MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus) 487 { 488 assert(pkt->req->isUncacheable()); 489 assert(pkt->isRead()); 490 return allocateBufferInternal(&mshrQueue, 491 pkt->getAddr(), pkt->getSize(), 492 pkt, time, requestBus); 493 } 494 495 /** 496 * Returns true if the cache is blocked for accesses. 497 */ 498 bool isBlocked() const 499 { 500 return blocked != 0; 501 } 502 503 /** 504 * Marks the access path of the cache as blocked for the given cause. This 505 * also sets the blocked flag in the slave interface. 506 * @param cause The reason for the cache blocking. 507 */ 508 void setBlocked(BlockedCause cause) 509 { 510 uint8_t flag = 1 << cause; 511 if (blocked == 0) { 512 blocked_causes[cause]++; 513 blockedCycle = curCycle(); 514 cpuSidePort->setBlocked(); 515 } 516 blocked |= flag; 517 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked); 518 } 519 520 /** 521 * Marks the cache as unblocked for the given cause. This also clears the 522 * blocked flags in the appropriate interfaces. 523 * @param cause The newly unblocked cause. 524 * @warning Calling this function can cause a blocked request on the bus to 525 * access the cache. The cache must be in a state to handle that request. 526 */ 527 void clearBlocked(BlockedCause cause) 528 { 529 uint8_t flag = 1 << cause; 530 blocked &= ~flag; 531 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked); 532 if (blocked == 0) { 533 blocked_cycles[cause] += curCycle() - blockedCycle; 534 cpuSidePort->clearBlocked(); 535 } 536 } 537 538 /** 539 * Request the master bus for the given cause and time. 540 * @param cause The reason for the request. 541 * @param time The time to make the request. 542 */ 543 void requestMemSideBus(RequestCause cause, Tick time) 544 { 545 memSidePort->requestBus(cause, time); 546 } 547 548 /** 549 * Clear the master bus request for the given cause. 550 * @param cause The request reason to clear. 551 */ 552 void deassertMemSideBusRequest(RequestCause cause) 553 { 554 // Obsolete... we no longer signal bus requests explicitly so 555 // we can't deassert them. Leaving this in as a no-op since 556 // the prefetcher calls it to indicate that it no longer wants 557 // to request a prefetch, and someday that might be 558 // interesting again. 559 } 560 561 virtual unsigned int drain(DrainManager *dm); 562 563 virtual bool inCache(Addr addr) const = 0; 564 565 virtual bool inMissQueue(Addr addr) const = 0; 566 567 void incMissCount(PacketPtr pkt) 568 { 569 assert(pkt->req->masterId() < system->maxMasters()); 570 misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 571 572 if (missCount) { 573 --missCount; 574 if (missCount == 0) 575 exitSimLoop("A cache reached the maximum miss count"); 576 } 577 } 578 void incHitCount(PacketPtr pkt) 579 { 580 assert(pkt->req->masterId() < system->maxMasters()); 581 hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 582 583 } 584 585}; 586 587#endif //__BASE_CACHE_HH__ 588