base.hh revision 9448
111731Sjason@lowepower.com/* 211731Sjason@lowepower.com * Copyright (c) 2012 ARM Limited 312062Sar4jc@virginia.edu * All rights reserved. 412062Sar4jc@virginia.edu * 512062Sar4jc@virginia.edu * The license below extends only to copyright in the software and shall 612062Sar4jc@virginia.edu * not be construed as granting a license to any other intellectual 712062Sar4jc@virginia.edu * property including but not limited to intellectual property relating 812062Sar4jc@virginia.edu * to a hardware implementation of the functionality of the software 912062Sar4jc@virginia.edu * licensed hereunder. You may use the software subject to the license 1012062Sar4jc@virginia.edu * terms below provided that you ensure that this notice is replicated 1112062Sar4jc@virginia.edu * unmodified and in its entirety in all distributions of the software, 1212062Sar4jc@virginia.edu * modified or unmodified, in source code or in binary form. 1312062Sar4jc@virginia.edu * 1412062Sar4jc@virginia.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 1512062Sar4jc@virginia.edu * All rights reserved. 1612062Sar4jc@virginia.edu * 1712062Sar4jc@virginia.edu * Redistribution and use in source and binary forms, with or without 1812062Sar4jc@virginia.edu * modification, are permitted provided that the following conditions are 1912062Sar4jc@virginia.edu * met: redistributions of source code must retain the above copyright 2012062Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer; 2112062Sar4jc@virginia.edu * redistributions in binary form must reproduce the above copyright 2212062Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer in the 2312062Sar4jc@virginia.edu * documentation and/or other materials provided with the distribution; 2412062Sar4jc@virginia.edu * neither the name of the copyright holders nor the names of its 2512062Sar4jc@virginia.edu * contributors may be used to endorse or promote products derived from 2612062Sar4jc@virginia.edu * this software without specific prior written permission. 2712062Sar4jc@virginia.edu * 2812062Sar4jc@virginia.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2912062Sar4jc@virginia.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3012062Sar4jc@virginia.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3112062Sar4jc@virginia.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3212062Sar4jc@virginia.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3312062Sar4jc@virginia.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3412062Sar4jc@virginia.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3512062Sar4jc@virginia.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3612062Sar4jc@virginia.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3712062Sar4jc@virginia.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3812062Sar4jc@virginia.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3912062Sar4jc@virginia.edu * 4012062Sar4jc@virginia.edu * Authors: Erik Hallnor 4112062Sar4jc@virginia.edu * Steve Reinhardt 4212062Sar4jc@virginia.edu * Ron Dreslinski 4312062Sar4jc@virginia.edu */ 4412062Sar4jc@virginia.edu 4512062Sar4jc@virginia.edu/** 4612062Sar4jc@virginia.edu * @file 4712062Sar4jc@virginia.edu * Declares a basic cache interface BaseCache. 4812062Sar4jc@virginia.edu */ 4912062Sar4jc@virginia.edu 5012062Sar4jc@virginia.edu#ifndef __BASE_CACHE_HH__ 5112062Sar4jc@virginia.edu#define __BASE_CACHE_HH__ 5212062Sar4jc@virginia.edu 5312062Sar4jc@virginia.edu#include <algorithm> 5412062Sar4jc@virginia.edu#include <list> 5512062Sar4jc@virginia.edu#include <string> 5612062Sar4jc@virginia.edu#include <vector> 5712062Sar4jc@virginia.edu 5812062Sar4jc@virginia.edu#include "base/misc.hh" 5912062Sar4jc@virginia.edu#include "base/statistics.hh" 6012062Sar4jc@virginia.edu#include "base/trace.hh" 6112062Sar4jc@virginia.edu#include "base/types.hh" 6212062Sar4jc@virginia.edu#include "debug/Cache.hh" 6312062Sar4jc@virginia.edu#include "debug/CachePort.hh" 6412062Sar4jc@virginia.edu#include "mem/cache/mshr_queue.hh" 6512062Sar4jc@virginia.edu#include "mem/mem_object.hh" 6612062Sar4jc@virginia.edu#include "mem/packet.hh" 6712062Sar4jc@virginia.edu#include "mem/qport.hh" 6812062Sar4jc@virginia.edu#include "mem/request.hh" 6912062Sar4jc@virginia.edu#include "params/BaseCache.hh" 7012062Sar4jc@virginia.edu#include "sim/eventq.hh" 7112062Sar4jc@virginia.edu#include "sim/full_system.hh" 7212062Sar4jc@virginia.edu#include "sim/sim_exit.hh" 7312062Sar4jc@virginia.edu#include "sim/system.hh" 7412062Sar4jc@virginia.edu 7512062Sar4jc@virginia.educlass MSHR; 7612062Sar4jc@virginia.edu/** 7712062Sar4jc@virginia.edu * A basic cache interface. Implements some common functions for speed. 7812062Sar4jc@virginia.edu */ 7912062Sar4jc@virginia.educlass BaseCache : public MemObject 8012062Sar4jc@virginia.edu{ 8112062Sar4jc@virginia.edu /** 8212062Sar4jc@virginia.edu * Indexes to enumerate the MSHR queues. 8312062Sar4jc@virginia.edu */ 8412062Sar4jc@virginia.edu enum MSHRQueueIndex { 8512062Sar4jc@virginia.edu MSHRQueue_MSHRs, 8612062Sar4jc@virginia.edu MSHRQueue_WriteBuffer 8712062Sar4jc@virginia.edu }; 8812062Sar4jc@virginia.edu 8912062Sar4jc@virginia.edu public: 9012062Sar4jc@virginia.edu /** 9112062Sar4jc@virginia.edu * Reasons for caches to be blocked. 9212062Sar4jc@virginia.edu */ 9312062Sar4jc@virginia.edu enum BlockedCause { 9412062Sar4jc@virginia.edu Blocked_NoMSHRs = MSHRQueue_MSHRs, 9512062Sar4jc@virginia.edu Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, 9612062Sar4jc@virginia.edu Blocked_NoTargets, 9712062Sar4jc@virginia.edu NUM_BLOCKED_CAUSES 9812062Sar4jc@virginia.edu }; 9912062Sar4jc@virginia.edu 10012062Sar4jc@virginia.edu /** 10112062Sar4jc@virginia.edu * Reasons for cache to request a bus. 10212062Sar4jc@virginia.edu */ 10312062Sar4jc@virginia.edu enum RequestCause { 10412062Sar4jc@virginia.edu Request_MSHR = MSHRQueue_MSHRs, 10512062Sar4jc@virginia.edu Request_WB = MSHRQueue_WriteBuffer, 10612062Sar4jc@virginia.edu Request_PF, 10712062Sar4jc@virginia.edu NUM_REQUEST_CAUSES 10812062Sar4jc@virginia.edu }; 10912062Sar4jc@virginia.edu 11012062Sar4jc@virginia.edu protected: 11112062Sar4jc@virginia.edu 11212062Sar4jc@virginia.edu /** 11312062Sar4jc@virginia.edu * A cache master port is used for the memory-side port of the 11412062Sar4jc@virginia.edu * cache, and in addition to the basic timing port that only sends 11512062Sar4jc@virginia.edu * response packets through a transmit list, it also offers the 11612062Sar4jc@virginia.edu * ability to schedule and send request packets (requests & 11712062Sar4jc@virginia.edu * writebacks). The send event is scheduled through requestBus, 11812062Sar4jc@virginia.edu * and the sendDeferredPacket of the timing port is modified to 11912062Sar4jc@virginia.edu * consider both the transmit list and the requests from the MSHR. 12012062Sar4jc@virginia.edu */ 12112062Sar4jc@virginia.edu class CacheMasterPort : public QueuedMasterPort 12212062Sar4jc@virginia.edu { 12312062Sar4jc@virginia.edu 12412062Sar4jc@virginia.edu public: 12512062Sar4jc@virginia.edu 12612062Sar4jc@virginia.edu /** 12712062Sar4jc@virginia.edu * Schedule a send of a request packet (from the MSHR). Note 12812062Sar4jc@virginia.edu * that we could already have a retry or a transmit list of 12912062Sar4jc@virginia.edu * responses outstanding. 13012062Sar4jc@virginia.edu */ 13112062Sar4jc@virginia.edu void requestBus(RequestCause cause, Tick time) 13212062Sar4jc@virginia.edu { 13312062Sar4jc@virginia.edu DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause); 13412062Sar4jc@virginia.edu queue.schedSendEvent(time); 13512062Sar4jc@virginia.edu } 13612062Sar4jc@virginia.edu 13712062Sar4jc@virginia.edu protected: 13812062Sar4jc@virginia.edu 13912062Sar4jc@virginia.edu CacheMasterPort(const std::string &_name, BaseCache *_cache, 14012062Sar4jc@virginia.edu MasterPacketQueue &_queue) : 14112062Sar4jc@virginia.edu QueuedMasterPort(_name, _cache, _queue) 14212062Sar4jc@virginia.edu { } 14312062Sar4jc@virginia.edu 14412062Sar4jc@virginia.edu /** 14512062Sar4jc@virginia.edu * Memory-side port always snoops. 14612062Sar4jc@virginia.edu * 14712062Sar4jc@virginia.edu * @return always true 14812062Sar4jc@virginia.edu */ 14912062Sar4jc@virginia.edu virtual bool isSnooping() const { return true; } 15012062Sar4jc@virginia.edu }; 15112062Sar4jc@virginia.edu 15212062Sar4jc@virginia.edu /** 15312062Sar4jc@virginia.edu * A cache slave port is used for the CPU-side port of the cache, 15412062Sar4jc@virginia.edu * and it is basically a simple timing port that uses a transmit 15512062Sar4jc@virginia.edu * list for responses to the CPU (or connected master). In 15612062Sar4jc@virginia.edu * addition, it has the functionality to block the port for 15712062Sar4jc@virginia.edu * incoming requests. If blocked, the port will issue a retry once 15812062Sar4jc@virginia.edu * unblocked. 15912062Sar4jc@virginia.edu */ 16012062Sar4jc@virginia.edu class CacheSlavePort : public QueuedSlavePort 16112062Sar4jc@virginia.edu { 16212062Sar4jc@virginia.edu 16312062Sar4jc@virginia.edu public: 16412062Sar4jc@virginia.edu 16512062Sar4jc@virginia.edu /** Do not accept any new requests. */ 16612062Sar4jc@virginia.edu void setBlocked(); 16712062Sar4jc@virginia.edu 16812062Sar4jc@virginia.edu /** Return to normal operation and accept new requests. */ 16912062Sar4jc@virginia.edu void clearBlocked(); 17012062Sar4jc@virginia.edu 17112062Sar4jc@virginia.edu protected: 17212062Sar4jc@virginia.edu 17312062Sar4jc@virginia.edu CacheSlavePort(const std::string &_name, BaseCache *_cache, 17412062Sar4jc@virginia.edu const std::string &_label); 17512062Sar4jc@virginia.edu 17612062Sar4jc@virginia.edu /** A normal packet queue used to store responses. */ 17712062Sar4jc@virginia.edu SlavePacketQueue queue; 17812062Sar4jc@virginia.edu 17912062Sar4jc@virginia.edu bool blocked; 18012062Sar4jc@virginia.edu 18112062Sar4jc@virginia.edu bool mustSendRetry; 18212062Sar4jc@virginia.edu 18312062Sar4jc@virginia.edu private: 18412062Sar4jc@virginia.edu 18512062Sar4jc@virginia.edu EventWrapper<SlavePort, &SlavePort::sendRetry> sendRetryEvent; 18612062Sar4jc@virginia.edu 18712062Sar4jc@virginia.edu }; 18812062Sar4jc@virginia.edu 18912062Sar4jc@virginia.edu CacheSlavePort *cpuSidePort; 19012062Sar4jc@virginia.edu CacheMasterPort *memSidePort; 19112062Sar4jc@virginia.edu 19212062Sar4jc@virginia.edu protected: 19312062Sar4jc@virginia.edu 19412062Sar4jc@virginia.edu /** Miss status registers */ 19512062Sar4jc@virginia.edu MSHRQueue mshrQueue; 19612062Sar4jc@virginia.edu 19712062Sar4jc@virginia.edu /** Write/writeback buffer */ 19812062Sar4jc@virginia.edu MSHRQueue writeBuffer; 19912062Sar4jc@virginia.edu 20012062Sar4jc@virginia.edu MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size, 20112062Sar4jc@virginia.edu PacketPtr pkt, Tick time, bool requestBus) 20212062Sar4jc@virginia.edu { 20312062Sar4jc@virginia.edu MSHR *mshr = mq->allocate(addr, size, pkt, time, order++); 20412062Sar4jc@virginia.edu 20512062Sar4jc@virginia.edu if (mq->isFull()) { 20612062Sar4jc@virginia.edu setBlocked((BlockedCause)mq->index); 20712062Sar4jc@virginia.edu } 20812062Sar4jc@virginia.edu 20912062Sar4jc@virginia.edu if (requestBus) { 21012062Sar4jc@virginia.edu requestMemSideBus((RequestCause)mq->index, time); 21112062Sar4jc@virginia.edu } 21212062Sar4jc@virginia.edu 21312062Sar4jc@virginia.edu return mshr; 21412062Sar4jc@virginia.edu } 21512062Sar4jc@virginia.edu 21612062Sar4jc@virginia.edu void markInServiceInternal(MSHR *mshr, PacketPtr pkt) 21712062Sar4jc@virginia.edu { 21812062Sar4jc@virginia.edu MSHRQueue *mq = mshr->queue; 21912062Sar4jc@virginia.edu bool wasFull = mq->isFull(); 22012062Sar4jc@virginia.edu mq->markInService(mshr, pkt); 22112062Sar4jc@virginia.edu if (wasFull && !mq->isFull()) { 22212062Sar4jc@virginia.edu clearBlocked((BlockedCause)mq->index); 22312062Sar4jc@virginia.edu } 22412062Sar4jc@virginia.edu } 22512062Sar4jc@virginia.edu 22612062Sar4jc@virginia.edu /** 22712062Sar4jc@virginia.edu * Write back dirty blocks in the cache using functional accesses. 22812062Sar4jc@virginia.edu */ 22912062Sar4jc@virginia.edu virtual void memWriteback() = 0; 23012062Sar4jc@virginia.edu /** 23112062Sar4jc@virginia.edu * Invalidates all blocks in the cache. 23212062Sar4jc@virginia.edu * 23312062Sar4jc@virginia.edu * @warn Dirty cache lines will not be written back to 23412062Sar4jc@virginia.edu * memory. Make sure to call functionalWriteback() first if you 23512062Sar4jc@virginia.edu * want the to write them to memory. 23612062Sar4jc@virginia.edu */ 23712062Sar4jc@virginia.edu virtual void memInvalidate() = 0; 23812062Sar4jc@virginia.edu /** 23912062Sar4jc@virginia.edu * Determine if there are any dirty blocks in the cache. 24012062Sar4jc@virginia.edu * 24112062Sar4jc@virginia.edu * \return true if at least one block is dirty, false otherwise. 24212062Sar4jc@virginia.edu */ 24312062Sar4jc@virginia.edu virtual bool isDirty() const = 0; 24412062Sar4jc@virginia.edu 24512062Sar4jc@virginia.edu /** Block size of this cache */ 24612062Sar4jc@virginia.edu const unsigned blkSize; 24712062Sar4jc@virginia.edu 24812062Sar4jc@virginia.edu /** 24912062Sar4jc@virginia.edu * The latency of a hit in this device. 25012062Sar4jc@virginia.edu */ 25112062Sar4jc@virginia.edu const Cycles hitLatency; 25212062Sar4jc@virginia.edu 25312062Sar4jc@virginia.edu /** 25412062Sar4jc@virginia.edu * The latency of sending reponse to its upper level cache/core on a 25512062Sar4jc@virginia.edu * linefill. In most contemporary processors, the return path on a cache 25612062Sar4jc@virginia.edu * miss is much quicker that the hit latency. The responseLatency parameter 25712062Sar4jc@virginia.edu * tries to capture this latency. 25812062Sar4jc@virginia.edu */ 25912062Sar4jc@virginia.edu const Cycles responseLatency; 26012062Sar4jc@virginia.edu 26112062Sar4jc@virginia.edu /** The number of targets for each MSHR. */ 26212062Sar4jc@virginia.edu const int numTarget; 26312062Sar4jc@virginia.edu 26412062Sar4jc@virginia.edu /** Do we forward snoops from mem side port through to cpu side port? */ 26512062Sar4jc@virginia.edu bool forwardSnoops; 26612062Sar4jc@virginia.edu 26712062Sar4jc@virginia.edu /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should 26812062Sar4jc@virginia.edu * never try to forward ownership and similar optimizations to the cpu 26912062Sar4jc@virginia.edu * side */ 27012062Sar4jc@virginia.edu bool isTopLevel; 27112062Sar4jc@virginia.edu 27212062Sar4jc@virginia.edu /** 27312062Sar4jc@virginia.edu * Bit vector of the blocking reasons for the access path. 27412062Sar4jc@virginia.edu * @sa #BlockedCause 27512062Sar4jc@virginia.edu */ 27612062Sar4jc@virginia.edu uint8_t blocked; 27712062Sar4jc@virginia.edu 27812062Sar4jc@virginia.edu /** Increasing order number assigned to each incoming request. */ 27912062Sar4jc@virginia.edu uint64_t order; 28012062Sar4jc@virginia.edu 28112062Sar4jc@virginia.edu /** Stores time the cache blocked for statistics. */ 28212062Sar4jc@virginia.edu Cycles blockedCycle; 28312062Sar4jc@virginia.edu 28412062Sar4jc@virginia.edu /** Pointer to the MSHR that has no targets. */ 28512062Sar4jc@virginia.edu MSHR *noTargetMSHR; 28612062Sar4jc@virginia.edu 28712062Sar4jc@virginia.edu /** The number of misses to trigger an exit event. */ 28812062Sar4jc@virginia.edu Counter missCount; 28912062Sar4jc@virginia.edu 29012062Sar4jc@virginia.edu /** The drain event. */ 29112062Sar4jc@virginia.edu DrainManager *drainManager; 29212062Sar4jc@virginia.edu 29312062Sar4jc@virginia.edu /** 29412062Sar4jc@virginia.edu * The address range to which the cache responds on the CPU side. 29512062Sar4jc@virginia.edu * Normally this is all possible memory addresses. */ 29612062Sar4jc@virginia.edu AddrRangeList addrRanges; 29712062Sar4jc@virginia.edu 29812062Sar4jc@virginia.edu public: 29912062Sar4jc@virginia.edu /** System we are currently operating in. */ 30012062Sar4jc@virginia.edu System *system; 30112062Sar4jc@virginia.edu 30212062Sar4jc@virginia.edu // Statistics 30312062Sar4jc@virginia.edu /** 30412062Sar4jc@virginia.edu * @addtogroup CacheStatistics 30512062Sar4jc@virginia.edu * @{ 30612062Sar4jc@virginia.edu */ 30712062Sar4jc@virginia.edu 30812062Sar4jc@virginia.edu /** Number of hits per thread for each type of command. @sa Packet::Command */ 30912062Sar4jc@virginia.edu Stats::Vector hits[MemCmd::NUM_MEM_CMDS]; 31012062Sar4jc@virginia.edu /** Number of hits for demand accesses. */ 31112062Sar4jc@virginia.edu Stats::Formula demandHits; 31212062Sar4jc@virginia.edu /** Number of hit for all accesses. */ 31312062Sar4jc@virginia.edu Stats::Formula overallHits; 31412062Sar4jc@virginia.edu 31512062Sar4jc@virginia.edu /** Number of misses per thread for each type of command. @sa Packet::Command */ 31612062Sar4jc@virginia.edu Stats::Vector misses[MemCmd::NUM_MEM_CMDS]; 31712062Sar4jc@virginia.edu /** Number of misses for demand accesses. */ 31812062Sar4jc@virginia.edu Stats::Formula demandMisses; 31912062Sar4jc@virginia.edu /** Number of misses for all accesses. */ 32012062Sar4jc@virginia.edu Stats::Formula overallMisses; 32112062Sar4jc@virginia.edu 32212062Sar4jc@virginia.edu /** 32312062Sar4jc@virginia.edu * Total number of cycles per thread/command spent waiting for a miss. 32412062Sar4jc@virginia.edu * Used to calculate the average miss latency. 32512062Sar4jc@virginia.edu */ 32612062Sar4jc@virginia.edu Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS]; 32712062Sar4jc@virginia.edu /** Total number of cycles spent waiting for demand misses. */ 32812062Sar4jc@virginia.edu Stats::Formula demandMissLatency; 32912062Sar4jc@virginia.edu /** Total number of cycles spent waiting for all misses. */ 33012062Sar4jc@virginia.edu Stats::Formula overallMissLatency; 33112062Sar4jc@virginia.edu 33212062Sar4jc@virginia.edu /** The number of accesses per command and thread. */ 33312062Sar4jc@virginia.edu Stats::Formula accesses[MemCmd::NUM_MEM_CMDS]; 33412062Sar4jc@virginia.edu /** The number of demand accesses. */ 33512062Sar4jc@virginia.edu Stats::Formula demandAccesses; 33612062Sar4jc@virginia.edu /** The number of overall accesses. */ 33712062Sar4jc@virginia.edu Stats::Formula overallAccesses; 33812062Sar4jc@virginia.edu 33912062Sar4jc@virginia.edu /** The miss rate per command and thread. */ 34012062Sar4jc@virginia.edu Stats::Formula missRate[MemCmd::NUM_MEM_CMDS]; 34112062Sar4jc@virginia.edu /** The miss rate of all demand accesses. */ 34212062Sar4jc@virginia.edu Stats::Formula demandMissRate; 34312062Sar4jc@virginia.edu /** The miss rate for all accesses. */ 34412062Sar4jc@virginia.edu Stats::Formula overallMissRate; 34512062Sar4jc@virginia.edu 34612062Sar4jc@virginia.edu /** The average miss latency per command and thread. */ 34712062Sar4jc@virginia.edu Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS]; 34812062Sar4jc@virginia.edu /** The average miss latency for demand misses. */ 34912062Sar4jc@virginia.edu Stats::Formula demandAvgMissLatency; 35012062Sar4jc@virginia.edu /** The average miss latency for all misses. */ 35112062Sar4jc@virginia.edu Stats::Formula overallAvgMissLatency; 35212062Sar4jc@virginia.edu 35312062Sar4jc@virginia.edu /** The total number of cycles blocked for each blocked cause. */ 35412062Sar4jc@virginia.edu Stats::Vector blocked_cycles; 35512062Sar4jc@virginia.edu /** The number of times this cache blocked for each blocked cause. */ 35612062Sar4jc@virginia.edu Stats::Vector blocked_causes; 35712062Sar4jc@virginia.edu 35812062Sar4jc@virginia.edu /** The average number of cycles blocked for each blocked cause. */ 35912062Sar4jc@virginia.edu Stats::Formula avg_blocked; 36012062Sar4jc@virginia.edu 36112062Sar4jc@virginia.edu /** The number of fast writes (WH64) performed. */ 36212062Sar4jc@virginia.edu Stats::Scalar fastWrites; 36312062Sar4jc@virginia.edu 36412062Sar4jc@virginia.edu /** The number of cache copies performed. */ 36512062Sar4jc@virginia.edu Stats::Scalar cacheCopies; 36612062Sar4jc@virginia.edu 36712062Sar4jc@virginia.edu /** Number of blocks written back per thread. */ 36812062Sar4jc@virginia.edu Stats::Vector writebacks; 36912062Sar4jc@virginia.edu 37012062Sar4jc@virginia.edu /** Number of misses that hit in the MSHRs per command and thread. */ 37112062Sar4jc@virginia.edu Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS]; 37212062Sar4jc@virginia.edu /** Demand misses that hit in the MSHRs. */ 37312062Sar4jc@virginia.edu Stats::Formula demandMshrHits; 37412062Sar4jc@virginia.edu /** Total number of misses that hit in the MSHRs. */ 37512062Sar4jc@virginia.edu Stats::Formula overallMshrHits; 37612062Sar4jc@virginia.edu 37712062Sar4jc@virginia.edu /** Number of misses that miss in the MSHRs, per command and thread. */ 37812062Sar4jc@virginia.edu Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS]; 37912062Sar4jc@virginia.edu /** Demand misses that miss in the MSHRs. */ 38012062Sar4jc@virginia.edu Stats::Formula demandMshrMisses; 38112062Sar4jc@virginia.edu /** Total number of misses that miss in the MSHRs. */ 38212062Sar4jc@virginia.edu Stats::Formula overallMshrMisses; 38312062Sar4jc@virginia.edu 38412062Sar4jc@virginia.edu /** Number of misses that miss in the MSHRs, per command and thread. */ 38512062Sar4jc@virginia.edu Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS]; 38612062Sar4jc@virginia.edu /** Total number of misses that miss in the MSHRs. */ 38712062Sar4jc@virginia.edu Stats::Formula overallMshrUncacheable; 38812062Sar4jc@virginia.edu 38912062Sar4jc@virginia.edu /** Total cycle latency of each MSHR miss, per command and thread. */ 39012062Sar4jc@virginia.edu Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS]; 39112062Sar4jc@virginia.edu /** Total cycle latency of demand MSHR misses. */ 39212062Sar4jc@virginia.edu Stats::Formula demandMshrMissLatency; 39312062Sar4jc@virginia.edu /** Total cycle latency of overall MSHR misses. */ 39412062Sar4jc@virginia.edu Stats::Formula overallMshrMissLatency; 39512062Sar4jc@virginia.edu 39612062Sar4jc@virginia.edu /** Total cycle latency of each MSHR miss, per command and thread. */ 39712062Sar4jc@virginia.edu Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; 39812062Sar4jc@virginia.edu /** Total cycle latency of overall MSHR misses. */ 39912062Sar4jc@virginia.edu Stats::Formula overallMshrUncacheableLatency; 40012062Sar4jc@virginia.edu 40112062Sar4jc@virginia.edu#if 0 40212062Sar4jc@virginia.edu /** The total number of MSHR accesses per command and thread. */ 40312062Sar4jc@virginia.edu Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; 40412062Sar4jc@virginia.edu /** The total number of demand MSHR accesses. */ 40512062Sar4jc@virginia.edu Stats::Formula demandMshrAccesses; 40612062Sar4jc@virginia.edu /** The total number of MSHR accesses. */ 40712062Sar4jc@virginia.edu Stats::Formula overallMshrAccesses; 40812062Sar4jc@virginia.edu#endif 40912062Sar4jc@virginia.edu 41012062Sar4jc@virginia.edu /** The miss rate in the MSHRs pre command and thread. */ 41112062Sar4jc@virginia.edu Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; 41212062Sar4jc@virginia.edu /** The demand miss rate in the MSHRs. */ 41312062Sar4jc@virginia.edu Stats::Formula demandMshrMissRate; 41412062Sar4jc@virginia.edu /** The overall miss rate in the MSHRs. */ 41512062Sar4jc@virginia.edu Stats::Formula overallMshrMissRate; 41612062Sar4jc@virginia.edu 41712062Sar4jc@virginia.edu /** The average latency of an MSHR miss, per command and thread. */ 41812062Sar4jc@virginia.edu Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS]; 41912062Sar4jc@virginia.edu /** The average latency of a demand MSHR miss. */ 42012062Sar4jc@virginia.edu Stats::Formula demandAvgMshrMissLatency; 42112062Sar4jc@virginia.edu /** The average overall latency of an MSHR miss. */ 42212062Sar4jc@virginia.edu Stats::Formula overallAvgMshrMissLatency; 42312062Sar4jc@virginia.edu 42412062Sar4jc@virginia.edu /** The average latency of an MSHR miss, per command and thread. */ 42512062Sar4jc@virginia.edu Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; 42612062Sar4jc@virginia.edu /** The average overall latency of an MSHR miss. */ 42712062Sar4jc@virginia.edu Stats::Formula overallAvgMshrUncacheableLatency; 42812062Sar4jc@virginia.edu 42912062Sar4jc@virginia.edu /** The number of times a thread hit its MSHR cap. */ 43012062Sar4jc@virginia.edu Stats::Vector mshr_cap_events; 43112062Sar4jc@virginia.edu /** The number of times software prefetches caused the MSHR to block. */ 43212062Sar4jc@virginia.edu Stats::Vector soft_prefetch_mshr_full; 43312062Sar4jc@virginia.edu 43412062Sar4jc@virginia.edu Stats::Scalar mshr_no_allocate_misses; 43512062Sar4jc@virginia.edu 43612062Sar4jc@virginia.edu /** 43712062Sar4jc@virginia.edu * @} 43812062Sar4jc@virginia.edu */ 43912062Sar4jc@virginia.edu 44012062Sar4jc@virginia.edu /** 44112062Sar4jc@virginia.edu * Register stats for this object. 44212062Sar4jc@virginia.edu */ 44312062Sar4jc@virginia.edu virtual void regStats(); 44412062Sar4jc@virginia.edu 44512062Sar4jc@virginia.edu public: 44612062Sar4jc@virginia.edu typedef BaseCacheParams Params; 44712062Sar4jc@virginia.edu BaseCache(const Params *p); 44812062Sar4jc@virginia.edu ~BaseCache() {} 44912062Sar4jc@virginia.edu 45012062Sar4jc@virginia.edu virtual void init(); 45112062Sar4jc@virginia.edu 45212062Sar4jc@virginia.edu virtual BaseMasterPort &getMasterPort(const std::string &if_name, 45312062Sar4jc@virginia.edu PortID idx = InvalidPortID); 45412062Sar4jc@virginia.edu virtual BaseSlavePort &getSlavePort(const std::string &if_name, 45512062Sar4jc@virginia.edu PortID idx = InvalidPortID); 45612062Sar4jc@virginia.edu 45712062Sar4jc@virginia.edu /** 45812062Sar4jc@virginia.edu * Query block size of a cache. 45912062Sar4jc@virginia.edu * @return The block size 46012062Sar4jc@virginia.edu */ 46112062Sar4jc@virginia.edu unsigned 46212062Sar4jc@virginia.edu getBlockSize() const 46312062Sar4jc@virginia.edu { 46412062Sar4jc@virginia.edu return blkSize; 46512062Sar4jc@virginia.edu } 46612062Sar4jc@virginia.edu 46712062Sar4jc@virginia.edu 46812062Sar4jc@virginia.edu Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); } 46912062Sar4jc@virginia.edu 47012062Sar4jc@virginia.edu 47112062Sar4jc@virginia.edu const AddrRangeList &getAddrRanges() const { return addrRanges; } 47212062Sar4jc@virginia.edu 47312062Sar4jc@virginia.edu MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus) 47412062Sar4jc@virginia.edu { 47512062Sar4jc@virginia.edu assert(!pkt->req->isUncacheable()); 47612062Sar4jc@virginia.edu return allocateBufferInternal(&mshrQueue, 47712062Sar4jc@virginia.edu blockAlign(pkt->getAddr()), blkSize, 47812062Sar4jc@virginia.edu pkt, time, requestBus); 47912062Sar4jc@virginia.edu } 48012062Sar4jc@virginia.edu 48112062Sar4jc@virginia.edu MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus) 48212062Sar4jc@virginia.edu { 48312062Sar4jc@virginia.edu assert(pkt->isWrite() && !pkt->isRead()); 48412062Sar4jc@virginia.edu return allocateBufferInternal(&writeBuffer, 48512062Sar4jc@virginia.edu pkt->getAddr(), pkt->getSize(), 48612062Sar4jc@virginia.edu pkt, time, requestBus); 48712062Sar4jc@virginia.edu } 48812062Sar4jc@virginia.edu 48912062Sar4jc@virginia.edu MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus) 49012062Sar4jc@virginia.edu { 49112062Sar4jc@virginia.edu assert(pkt->req->isUncacheable()); 49212062Sar4jc@virginia.edu assert(pkt->isRead()); 49312062Sar4jc@virginia.edu return allocateBufferInternal(&mshrQueue, 49412062Sar4jc@virginia.edu pkt->getAddr(), pkt->getSize(), 49512062Sar4jc@virginia.edu pkt, time, requestBus); 49612062Sar4jc@virginia.edu } 49712062Sar4jc@virginia.edu 49812062Sar4jc@virginia.edu /** 49912062Sar4jc@virginia.edu * Returns true if the cache is blocked for accesses. 50012062Sar4jc@virginia.edu */ 50112062Sar4jc@virginia.edu bool isBlocked() 50212062Sar4jc@virginia.edu { 50312062Sar4jc@virginia.edu return blocked != 0; 50412062Sar4jc@virginia.edu } 50512062Sar4jc@virginia.edu 50612062Sar4jc@virginia.edu /** 50712062Sar4jc@virginia.edu * Marks the access path of the cache as blocked for the given cause. This 50812062Sar4jc@virginia.edu * also sets the blocked flag in the slave interface. 50912062Sar4jc@virginia.edu * @param cause The reason for the cache blocking. 51012062Sar4jc@virginia.edu */ 51112062Sar4jc@virginia.edu void setBlocked(BlockedCause cause) 51212062Sar4jc@virginia.edu { 51312062Sar4jc@virginia.edu uint8_t flag = 1 << cause; 51412062Sar4jc@virginia.edu if (blocked == 0) { 51512062Sar4jc@virginia.edu blocked_causes[cause]++; 51612062Sar4jc@virginia.edu blockedCycle = curCycle(); 51712062Sar4jc@virginia.edu cpuSidePort->setBlocked(); 51812062Sar4jc@virginia.edu } 51912062Sar4jc@virginia.edu blocked |= flag; 52012062Sar4jc@virginia.edu DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked); 52112062Sar4jc@virginia.edu } 52212062Sar4jc@virginia.edu 52312062Sar4jc@virginia.edu /** 52412062Sar4jc@virginia.edu * Marks the cache as unblocked for the given cause. This also clears the 52512062Sar4jc@virginia.edu * blocked flags in the appropriate interfaces. 52612062Sar4jc@virginia.edu * @param cause The newly unblocked cause. 52712062Sar4jc@virginia.edu * @warning Calling this function can cause a blocked request on the bus to 52812062Sar4jc@virginia.edu * access the cache. The cache must be in a state to handle that request. 52912062Sar4jc@virginia.edu */ 53012062Sar4jc@virginia.edu void clearBlocked(BlockedCause cause) 53112062Sar4jc@virginia.edu { 53212062Sar4jc@virginia.edu uint8_t flag = 1 << cause; 53312062Sar4jc@virginia.edu blocked &= ~flag; 53412062Sar4jc@virginia.edu DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked); 53512062Sar4jc@virginia.edu if (blocked == 0) { 53612062Sar4jc@virginia.edu blocked_cycles[cause] += curCycle() - blockedCycle; 53712062Sar4jc@virginia.edu cpuSidePort->clearBlocked(); 53812062Sar4jc@virginia.edu } 53912062Sar4jc@virginia.edu } 54012062Sar4jc@virginia.edu 54112062Sar4jc@virginia.edu /** 54212062Sar4jc@virginia.edu * Request the master bus for the given cause and time. 54312062Sar4jc@virginia.edu * @param cause The reason for the request. 54412062Sar4jc@virginia.edu * @param time The time to make the request. 54512062Sar4jc@virginia.edu */ 54612062Sar4jc@virginia.edu void requestMemSideBus(RequestCause cause, Tick time) 54712062Sar4jc@virginia.edu { 54812062Sar4jc@virginia.edu memSidePort->requestBus(cause, time); 54912062Sar4jc@virginia.edu } 55012062Sar4jc@virginia.edu 55112062Sar4jc@virginia.edu /** 55212062Sar4jc@virginia.edu * Clear the master bus request for the given cause. 55312062Sar4jc@virginia.edu * @param cause The request reason to clear. 55412062Sar4jc@virginia.edu */ 55512062Sar4jc@virginia.edu void deassertMemSideBusRequest(RequestCause cause) 55612062Sar4jc@virginia.edu { 55712062Sar4jc@virginia.edu // Obsolete... we no longer signal bus requests explicitly so 55812062Sar4jc@virginia.edu // we can't deassert them. Leaving this in as a no-op since 55912062Sar4jc@virginia.edu // the prefetcher calls it to indicate that it no longer wants 56012062Sar4jc@virginia.edu // to request a prefetch, and someday that might be 56112062Sar4jc@virginia.edu // interesting again. 56212062Sar4jc@virginia.edu } 56312062Sar4jc@virginia.edu 56412062Sar4jc@virginia.edu virtual unsigned int drain(DrainManager *dm); 56512062Sar4jc@virginia.edu 56612062Sar4jc@virginia.edu virtual bool inCache(Addr addr) = 0; 56712062Sar4jc@virginia.edu 56812062Sar4jc@virginia.edu virtual bool inMissQueue(Addr addr) = 0; 56912062Sar4jc@virginia.edu 57012062Sar4jc@virginia.edu void incMissCount(PacketPtr pkt) 57112062Sar4jc@virginia.edu { 57212062Sar4jc@virginia.edu assert(pkt->req->masterId() < system->maxMasters()); 57312062Sar4jc@virginia.edu misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 57412062Sar4jc@virginia.edu 57512062Sar4jc@virginia.edu if (missCount) { 57612062Sar4jc@virginia.edu --missCount; 57712062Sar4jc@virginia.edu if (missCount == 0) 57812062Sar4jc@virginia.edu exitSimLoop("A cache reached the maximum miss count"); 57912062Sar4jc@virginia.edu } 58012062Sar4jc@virginia.edu } 58112062Sar4jc@virginia.edu void incHitCount(PacketPtr pkt) 58212062Sar4jc@virginia.edu { 58312062Sar4jc@virginia.edu assert(pkt->req->masterId() < system->maxMasters()); 58412062Sar4jc@virginia.edu hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 58512062Sar4jc@virginia.edu 58612062Sar4jc@virginia.edu } 58712062Sar4jc@virginia.edu 58812062Sar4jc@virginia.edu}; 58912062Sar4jc@virginia.edu 59012062Sar4jc@virginia.edu#endif //__BASE_CACHE_HH__ 59112062Sar4jc@virginia.edu