base.hh revision 8662
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Erik Hallnor 29 * Steve Reinhardt 30 * Ron Dreslinski 31 */ 32 33/** 34 * @file 35 * Declares a basic cache interface BaseCache. 36 */ 37 38#ifndef __BASE_CACHE_HH__ 39#define __BASE_CACHE_HH__ 40 41#include <algorithm> 42#include <list> 43#include <string> 44#include <vector> 45 46#include "base/misc.hh" 47#include "base/statistics.hh" 48#include "base/trace.hh" 49#include "base/types.hh" 50#include "config/full_system.hh" 51#include "debug/Cache.hh" 52#include "debug/CachePort.hh" 53#include "mem/cache/mshr_queue.hh" 54#include "mem/mem_object.hh" 55#include "mem/packet.hh" 56#include "mem/request.hh" 57#include "mem/tport.hh" 58#include "params/BaseCache.hh" 59#include "sim/eventq.hh" 60#include "sim/sim_exit.hh" 61 62class MSHR; 63/** 64 * A basic cache interface. Implements some common functions for speed. 65 */ 66class BaseCache : public MemObject 67{ 68 /** 69 * Indexes to enumerate the MSHR queues. 70 */ 71 enum MSHRQueueIndex { 72 MSHRQueue_MSHRs, 73 MSHRQueue_WriteBuffer 74 }; 75 76 /** 77 * Reasons for caches to be blocked. 78 */ 79 enum BlockedCause { 80 Blocked_NoMSHRs = MSHRQueue_MSHRs, 81 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, 82 Blocked_NoTargets, 83 NUM_BLOCKED_CAUSES 84 }; 85 86 public: 87 /** 88 * Reasons for cache to request a bus. 89 */ 90 enum RequestCause { 91 Request_MSHR = MSHRQueue_MSHRs, 92 Request_WB = MSHRQueue_WriteBuffer, 93 Request_PF, 94 NUM_REQUEST_CAUSES 95 }; 96 97 private: 98 99 class CachePort : public SimpleTimingPort 100 { 101 public: 102 BaseCache *cache; 103 104 protected: 105 CachePort(const std::string &_name, BaseCache *_cache, 106 const std::string &_label); 107 108 virtual void recvStatusChange(Status status); 109 110 virtual unsigned deviceBlockSize() const; 111 112 bool recvRetryCommon(); 113 114 typedef EventWrapper<Port, &Port::sendRetry> 115 SendRetryEvent; 116 117 const std::string label; 118 119 public: 120 void setOtherPort(CachePort *_otherPort) { otherPort = _otherPort; } 121 122 void setBlocked(); 123 124 void clearBlocked(); 125 126 bool checkFunctional(PacketPtr pkt); 127 128 CachePort *otherPort; 129 130 bool blocked; 131 132 bool mustSendRetry; 133 134 void requestBus(RequestCause cause, Tick time) 135 { 136 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause); 137 if (!waitingOnRetry) { 138 schedSendEvent(time); 139 } 140 } 141 142 void respond(PacketPtr pkt, Tick time) { 143 schedSendTiming(pkt, time); 144 } 145 }; 146 147 public: //Made public so coherence can get at it. 148 CachePort *cpuSidePort; 149 CachePort *memSidePort; 150 151 protected: 152 153 /** Miss status registers */ 154 MSHRQueue mshrQueue; 155 156 /** Write/writeback buffer */ 157 MSHRQueue writeBuffer; 158 159 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size, 160 PacketPtr pkt, Tick time, bool requestBus) 161 { 162 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++); 163 164 if (mq->isFull()) { 165 setBlocked((BlockedCause)mq->index); 166 } 167 168 if (requestBus) { 169 requestMemSideBus((RequestCause)mq->index, time); 170 } 171 172 return mshr; 173 } 174 175 void markInServiceInternal(MSHR *mshr, PacketPtr pkt) 176 { 177 MSHRQueue *mq = mshr->queue; 178 bool wasFull = mq->isFull(); 179 mq->markInService(mshr, pkt); 180 if (wasFull && !mq->isFull()) { 181 clearBlocked((BlockedCause)mq->index); 182 } 183 } 184 185 /** Block size of this cache */ 186 const unsigned blkSize; 187 188 /** 189 * The latency of a hit in this device. 190 */ 191 int hitLatency; 192 193 /** The number of targets for each MSHR. */ 194 const int numTarget; 195 196 /** Do we forward snoops from mem side port through to cpu side port? */ 197 bool forwardSnoops; 198 199 /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should 200 * never try to forward ownership and similar optimizations to the cpu 201 * side */ 202 bool isTopLevel; 203 204 /** 205 * Bit vector of the blocking reasons for the access path. 206 * @sa #BlockedCause 207 */ 208 uint8_t blocked; 209 210 /** Increasing order number assigned to each incoming request. */ 211 uint64_t order; 212 213 /** Stores time the cache blocked for statistics. */ 214 Tick blockedCycle; 215 216 /** Pointer to the MSHR that has no targets. */ 217 MSHR *noTargetMSHR; 218 219 /** The number of misses to trigger an exit event. */ 220 Counter missCount; 221 222 /** The drain event. */ 223 Event *drainEvent; 224 225 /** 226 * The address range to which the cache responds on the CPU side. 227 * Normally this is all possible memory addresses. */ 228 Range<Addr> addrRange; 229 230 /** number of cpus sharing this cache - from config file */ 231 int _numCpus; 232 233 public: 234 int numCpus() { return _numCpus; } 235 // Statistics 236 /** 237 * @addtogroup CacheStatistics 238 * @{ 239 */ 240 241 /** Number of hits per thread for each type of command. @sa Packet::Command */ 242 Stats::Vector hits[MemCmd::NUM_MEM_CMDS]; 243 /** Number of hits for demand accesses. */ 244 Stats::Formula demandHits; 245 /** Number of hit for all accesses. */ 246 Stats::Formula overallHits; 247 248 /** Number of misses per thread for each type of command. @sa Packet::Command */ 249 Stats::Vector misses[MemCmd::NUM_MEM_CMDS]; 250 /** Number of misses for demand accesses. */ 251 Stats::Formula demandMisses; 252 /** Number of misses for all accesses. */ 253 Stats::Formula overallMisses; 254 255 /** 256 * Total number of cycles per thread/command spent waiting for a miss. 257 * Used to calculate the average miss latency. 258 */ 259 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS]; 260 /** Total number of cycles spent waiting for demand misses. */ 261 Stats::Formula demandMissLatency; 262 /** Total number of cycles spent waiting for all misses. */ 263 Stats::Formula overallMissLatency; 264 265 /** The number of accesses per command and thread. */ 266 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS]; 267 /** The number of demand accesses. */ 268 Stats::Formula demandAccesses; 269 /** The number of overall accesses. */ 270 Stats::Formula overallAccesses; 271 272 /** The miss rate per command and thread. */ 273 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS]; 274 /** The miss rate of all demand accesses. */ 275 Stats::Formula demandMissRate; 276 /** The miss rate for all accesses. */ 277 Stats::Formula overallMissRate; 278 279 /** The average miss latency per command and thread. */ 280 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS]; 281 /** The average miss latency for demand misses. */ 282 Stats::Formula demandAvgMissLatency; 283 /** The average miss latency for all misses. */ 284 Stats::Formula overallAvgMissLatency; 285 286 /** The total number of cycles blocked for each blocked cause. */ 287 Stats::Vector blocked_cycles; 288 /** The number of times this cache blocked for each blocked cause. */ 289 Stats::Vector blocked_causes; 290 291 /** The average number of cycles blocked for each blocked cause. */ 292 Stats::Formula avg_blocked; 293 294 /** The number of fast writes (WH64) performed. */ 295 Stats::Scalar fastWrites; 296 297 /** The number of cache copies performed. */ 298 Stats::Scalar cacheCopies; 299 300 /** Number of blocks written back per thread. */ 301 Stats::Vector writebacks; 302 303 /** Number of misses that hit in the MSHRs per command and thread. */ 304 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS]; 305 /** Demand misses that hit in the MSHRs. */ 306 Stats::Formula demandMshrHits; 307 /** Total number of misses that hit in the MSHRs. */ 308 Stats::Formula overallMshrHits; 309 310 /** Number of misses that miss in the MSHRs, per command and thread. */ 311 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS]; 312 /** Demand misses that miss in the MSHRs. */ 313 Stats::Formula demandMshrMisses; 314 /** Total number of misses that miss in the MSHRs. */ 315 Stats::Formula overallMshrMisses; 316 317 /** Number of misses that miss in the MSHRs, per command and thread. */ 318 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS]; 319 /** Total number of misses that miss in the MSHRs. */ 320 Stats::Formula overallMshrUncacheable; 321 322 /** Total cycle latency of each MSHR miss, per command and thread. */ 323 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS]; 324 /** Total cycle latency of demand MSHR misses. */ 325 Stats::Formula demandMshrMissLatency; 326 /** Total cycle latency of overall MSHR misses. */ 327 Stats::Formula overallMshrMissLatency; 328 329 /** Total cycle latency of each MSHR miss, per command and thread. */ 330 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; 331 /** Total cycle latency of overall MSHR misses. */ 332 Stats::Formula overallMshrUncacheableLatency; 333 334#if 0 335 /** The total number of MSHR accesses per command and thread. */ 336 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; 337 /** The total number of demand MSHR accesses. */ 338 Stats::Formula demandMshrAccesses; 339 /** The total number of MSHR accesses. */ 340 Stats::Formula overallMshrAccesses; 341#endif 342 343 /** The miss rate in the MSHRs pre command and thread. */ 344 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; 345 /** The demand miss rate in the MSHRs. */ 346 Stats::Formula demandMshrMissRate; 347 /** The overall miss rate in the MSHRs. */ 348 Stats::Formula overallMshrMissRate; 349 350 /** The average latency of an MSHR miss, per command and thread. */ 351 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS]; 352 /** The average latency of a demand MSHR miss. */ 353 Stats::Formula demandAvgMshrMissLatency; 354 /** The average overall latency of an MSHR miss. */ 355 Stats::Formula overallAvgMshrMissLatency; 356 357 /** The average latency of an MSHR miss, per command and thread. */ 358 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; 359 /** The average overall latency of an MSHR miss. */ 360 Stats::Formula overallAvgMshrUncacheableLatency; 361 362 /** The number of times a thread hit its MSHR cap. */ 363 Stats::Vector mshr_cap_events; 364 /** The number of times software prefetches caused the MSHR to block. */ 365 Stats::Vector soft_prefetch_mshr_full; 366 367 Stats::Scalar mshr_no_allocate_misses; 368 369 /** 370 * @} 371 */ 372 373 /** 374 * Register stats for this object. 375 */ 376 virtual void regStats(); 377 378 public: 379 typedef BaseCacheParams Params; 380 BaseCache(const Params *p); 381 ~BaseCache() {} 382 383 virtual void init(); 384 385 /** 386 * Query block size of a cache. 387 * @return The block size 388 */ 389 unsigned 390 getBlockSize() const 391 { 392 return blkSize; 393 } 394 395 396 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); } 397 398 399 const Range<Addr> &getAddrRange() const { return addrRange; } 400 401 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus) 402 { 403 assert(!pkt->req->isUncacheable()); 404 return allocateBufferInternal(&mshrQueue, 405 blockAlign(pkt->getAddr()), blkSize, 406 pkt, time, requestBus); 407 } 408 409 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus) 410 { 411 assert(pkt->isWrite() && !pkt->isRead()); 412 return allocateBufferInternal(&writeBuffer, 413 pkt->getAddr(), pkt->getSize(), 414 pkt, time, requestBus); 415 } 416 417 MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus) 418 { 419 assert(pkt->req->isUncacheable()); 420 assert(pkt->isRead()); 421 return allocateBufferInternal(&mshrQueue, 422 pkt->getAddr(), pkt->getSize(), 423 pkt, time, requestBus); 424 } 425 426 /** 427 * Returns true if the cache is blocked for accesses. 428 */ 429 bool isBlocked() 430 { 431 return blocked != 0; 432 } 433 434 /** 435 * Marks the access path of the cache as blocked for the given cause. This 436 * also sets the blocked flag in the slave interface. 437 * @param cause The reason for the cache blocking. 438 */ 439 void setBlocked(BlockedCause cause) 440 { 441 uint8_t flag = 1 << cause; 442 if (blocked == 0) { 443 blocked_causes[cause]++; 444 blockedCycle = curTick(); 445 cpuSidePort->setBlocked(); 446 } 447 blocked |= flag; 448 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked); 449 } 450 451 /** 452 * Marks the cache as unblocked for the given cause. This also clears the 453 * blocked flags in the appropriate interfaces. 454 * @param cause The newly unblocked cause. 455 * @warning Calling this function can cause a blocked request on the bus to 456 * access the cache. The cache must be in a state to handle that request. 457 */ 458 void clearBlocked(BlockedCause cause) 459 { 460 uint8_t flag = 1 << cause; 461 blocked &= ~flag; 462 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked); 463 if (blocked == 0) { 464 blocked_cycles[cause] += curTick() - blockedCycle; 465 cpuSidePort->clearBlocked(); 466 } 467 } 468 469 /** 470 * Request the master bus for the given cause and time. 471 * @param cause The reason for the request. 472 * @param time The time to make the request. 473 */ 474 void requestMemSideBus(RequestCause cause, Tick time) 475 { 476 memSidePort->requestBus(cause, time); 477 } 478 479 /** 480 * Clear the master bus request for the given cause. 481 * @param cause The request reason to clear. 482 */ 483 void deassertMemSideBusRequest(RequestCause cause) 484 { 485 // Obsolete... we no longer signal bus requests explicitly so 486 // we can't deassert them. Leaving this in as a no-op since 487 // the prefetcher calls it to indicate that it no longer wants 488 // to request a prefetch, and someday that might be 489 // interesting again. 490 } 491 492 virtual unsigned int drain(Event *de); 493 494 virtual bool inCache(Addr addr) = 0; 495 496 virtual bool inMissQueue(Addr addr) = 0; 497 498 void incMissCount(PacketPtr pkt, int id) 499 { 500 501 if (pkt->cmd == MemCmd::Writeback) { 502 assert(id == -1); 503 misses[pkt->cmdToIndex()][0]++; 504 /* same thing for writeback hits as misses - no context id 505 * available, meanwhile writeback hit/miss stats are not used 506 * in any aggregate hit/miss calculations, so just lump them all 507 * in bucket 0 */ 508#if FULL_SYSTEM 509 } else if (id == -1) { 510 // Device accesses have id -1 511 // lump device accesses into their own bucket 512 misses[pkt->cmdToIndex()][_numCpus]++; 513#endif 514 } else { 515 misses[pkt->cmdToIndex()][id % _numCpus]++; 516 } 517 518 if (missCount) { 519 --missCount; 520 if (missCount == 0) 521 exitSimLoop("A cache reached the maximum miss count"); 522 } 523 } 524 void incHitCount(PacketPtr pkt, int id) 525 { 526 527 /* Writeback requests don't have a context id associated with 528 * them, so attributing a hit to a -1 context id is obviously a 529 * problem. I've noticed in the stats that hits are split into 530 * demand and non-demand hits - neither of which include writeback 531 * hits, so here, I'll just put the writeback hits into bucket 0 532 * since it won't mess with any other stats -hsul */ 533 if (pkt->cmd == MemCmd::Writeback) { 534 assert(id == -1); 535 hits[pkt->cmdToIndex()][0]++; 536#if FULL_SYSTEM 537 } else if (id == -1) { 538 // Device accesses have id -1 539 // lump device accesses into their own bucket 540 hits[pkt->cmdToIndex()][_numCpus]++; 541#endif 542 } else { 543 /* the % is necessary in case there are switch cpus */ 544 hits[pkt->cmdToIndex()][id % _numCpus]++; 545 } 546 } 547 548}; 549 550#endif //__BASE_CACHE_HH__ 551