base.hh revision 6666:3199397fd905
11917SN/A/* 21917SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 31917SN/A * All rights reserved. 41917SN/A * 51917SN/A * Redistribution and use in source and binary forms, with or without 61917SN/A * modification, are permitted provided that the following conditions are 71917SN/A * met: redistributions of source code must retain the above copyright 81917SN/A * notice, this list of conditions and the following disclaimer; 91917SN/A * redistributions in binary form must reproduce the above copyright 101917SN/A * notice, this list of conditions and the following disclaimer in the 111917SN/A * documentation and/or other materials provided with the distribution; 121917SN/A * neither the name of the copyright holders nor the names of its 131917SN/A * contributors may be used to endorse or promote products derived from 141917SN/A * this software without specific prior written permission. 151917SN/A * 161917SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171917SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181917SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191917SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201917SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211917SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221917SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231917SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241917SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251917SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261917SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Erik Hallnor 291917SN/A * Steve Reinhardt 301917SN/A * Ron Dreslinski 311917SN/A */ 321917SN/A 331917SN/A/** 341981SN/A * @file 351981SN/A * Declares a basic cache interface BaseCache. 361917SN/A */ 372235SN/A 381917SN/A#ifndef __BASE_CACHE_HH__ 392680Sktlim@umich.edu#define __BASE_CACHE_HH__ 401917SN/A 411917SN/A#include <vector> 421917SN/A#include <string> 431917SN/A#include <list> 441917SN/A#include <algorithm> 451917SN/A 461917SN/A#include "base/misc.hh" 471917SN/A#include "base/statistics.hh" 481917SN/A#include "base/trace.hh" 491917SN/A#include "base/types.hh" 501917SN/A#include "mem/cache/mshr_queue.hh" 511917SN/A#include "mem/mem_object.hh" 521917SN/A#include "mem/packet.hh" 531917SN/A#include "mem/tport.hh" 541917SN/A#include "mem/request.hh" 551977SN/A#include "params/BaseCache.hh" 561977SN/A#include "sim/eventq.hh" 571917SN/A#include "sim/sim_exit.hh" 581917SN/A 591917SN/Aclass MSHR; 601917SN/A/** 611917SN/A * A basic cache interface. Implements some common functions for speed. 621917SN/A */ 631917SN/Aclass BaseCache : public MemObject 641917SN/A{ 651917SN/A /** 661917SN/A * Indexes to enumerate the MSHR queues. 671917SN/A */ 681917SN/A enum MSHRQueueIndex { 691917SN/A MSHRQueue_MSHRs, 701917SN/A MSHRQueue_WriteBuffer 711917SN/A }; 721917SN/A 731977SN/A /** 741977SN/A * Reasons for caches to be blocked. 751917SN/A */ 761917SN/A enum BlockedCause { 771917SN/A Blocked_NoMSHRs = MSHRQueue_MSHRs, 781917SN/A Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, 791917SN/A Blocked_NoTargets, 801917SN/A NUM_BLOCKED_CAUSES 811917SN/A }; 821917SN/A 831977SN/A public: 841977SN/A /** 851917SN/A * Reasons for cache to request a bus. 861917SN/A */ 871917SN/A enum RequestCause { 881981SN/A Request_MSHR = MSHRQueue_MSHRs, 891917SN/A Request_WB = MSHRQueue_WriteBuffer, 901981SN/A Request_PF, 911981SN/A NUM_REQUEST_CAUSES 921917SN/A }; 931917SN/A 941917SN/A private: 951917SN/A 961981SN/A class CachePort : public SimpleTimingPort 971981SN/A { 981917SN/A public: 991917SN/A BaseCache *cache; 1001917SN/A 1011977SN/A protected: 1021917SN/A CachePort(const std::string &_name, BaseCache *_cache, 1031917SN/A const std::string &_label); 1041977SN/A 1051977SN/A virtual void recvStatusChange(Status status); 1061977SN/A 1071977SN/A virtual unsigned deviceBlockSize() const; 1081977SN/A 1091977SN/A bool recvRetryCommon(); 1101977SN/A 1111917SN/A typedef EventWrapper<Port, &Port::sendRetry> 1121917SN/A SendRetryEvent; 1131917SN/A 1141917SN/A const std::string label; 1151917SN/A 1161917SN/A public: 1171917SN/A void setOtherPort(CachePort *_otherPort) { otherPort = _otherPort; } 1181917SN/A 1191917SN/A void setBlocked(); 1201917SN/A 1211917SN/A void clearBlocked(); 1221917SN/A 1232680Sktlim@umich.edu bool checkFunctional(PacketPtr pkt); 1241917SN/A 1251917SN/A CachePort *otherPort; 1261917SN/A 1271917SN/A bool blocked; 1281917SN/A 1291917SN/A bool mustSendRetry; 1301917SN/A 1311917SN/A void requestBus(RequestCause cause, Tick time) 1321917SN/A { 1331917SN/A DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause); 1341917SN/A if (!waitingOnRetry) { 1351917SN/A schedSendEvent(time); 1361917SN/A } 1371917SN/A } 1381917SN/A 1391917SN/A void respond(PacketPtr pkt, Tick time) { 1401917SN/A schedSendTiming(pkt, time); 1411917SN/A } 1421917SN/A }; 1431917SN/A 1441917SN/A public: //Made public so coherence can get at it. 1451917SN/A CachePort *cpuSidePort; 1461917SN/A CachePort *memSidePort; 1471917SN/A 1481917SN/A protected: 1491917SN/A 1501917SN/A /** Miss status registers */ 1511917SN/A MSHRQueue mshrQueue; 1521917SN/A 1531917SN/A /** Write/writeback buffer */ 1541917SN/A MSHRQueue writeBuffer; 1551917SN/A 1561917SN/A MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size, 1571917SN/A PacketPtr pkt, Tick time, bool requestBus) 158 { 159 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++); 160 161 if (mq->isFull()) { 162 setBlocked((BlockedCause)mq->index); 163 } 164 165 if (requestBus) { 166 requestMemSideBus((RequestCause)mq->index, time); 167 } 168 169 return mshr; 170 } 171 172 void markInServiceInternal(MSHR *mshr) 173 { 174 MSHRQueue *mq = mshr->queue; 175 bool wasFull = mq->isFull(); 176 mq->markInService(mshr); 177 if (wasFull && !mq->isFull()) { 178 clearBlocked((BlockedCause)mq->index); 179 } 180 } 181 182 /** Block size of this cache */ 183 const unsigned blkSize; 184 185 /** 186 * The latency of a hit in this device. 187 */ 188 int hitLatency; 189 190 /** The number of targets for each MSHR. */ 191 const int numTarget; 192 193 /** Do we forward snoops from mem side port through to cpu side port? */ 194 bool forwardSnoops; 195 196 /** 197 * Bit vector of the blocking reasons for the access path. 198 * @sa #BlockedCause 199 */ 200 uint8_t blocked; 201 202 /** Increasing order number assigned to each incoming request. */ 203 uint64_t order; 204 205 /** Stores time the cache blocked for statistics. */ 206 Tick blockedCycle; 207 208 /** Pointer to the MSHR that has no targets. */ 209 MSHR *noTargetMSHR; 210 211 /** The number of misses to trigger an exit event. */ 212 Counter missCount; 213 214 /** The drain event. */ 215 Event *drainEvent; 216 217 /** 218 * The address range to which the cache responds on the CPU side. 219 * Normally this is all possible memory addresses. */ 220 Range<Addr> addrRange; 221 222 public: 223 // Statistics 224 /** 225 * @addtogroup CacheStatistics 226 * @{ 227 */ 228 229 /** Number of hits per thread for each type of command. @sa Packet::Command */ 230 Stats::Vector hits[MemCmd::NUM_MEM_CMDS]; 231 /** Number of hits for demand accesses. */ 232 Stats::Formula demandHits; 233 /** Number of hit for all accesses. */ 234 Stats::Formula overallHits; 235 236 /** Number of misses per thread for each type of command. @sa Packet::Command */ 237 Stats::Vector misses[MemCmd::NUM_MEM_CMDS]; 238 /** Number of misses for demand accesses. */ 239 Stats::Formula demandMisses; 240 /** Number of misses for all accesses. */ 241 Stats::Formula overallMisses; 242 243 /** 244 * Total number of cycles per thread/command spent waiting for a miss. 245 * Used to calculate the average miss latency. 246 */ 247 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS]; 248 /** Total number of cycles spent waiting for demand misses. */ 249 Stats::Formula demandMissLatency; 250 /** Total number of cycles spent waiting for all misses. */ 251 Stats::Formula overallMissLatency; 252 253 /** The number of accesses per command and thread. */ 254 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS]; 255 /** The number of demand accesses. */ 256 Stats::Formula demandAccesses; 257 /** The number of overall accesses. */ 258 Stats::Formula overallAccesses; 259 260 /** The miss rate per command and thread. */ 261 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS]; 262 /** The miss rate of all demand accesses. */ 263 Stats::Formula demandMissRate; 264 /** The miss rate for all accesses. */ 265 Stats::Formula overallMissRate; 266 267 /** The average miss latency per command and thread. */ 268 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS]; 269 /** The average miss latency for demand misses. */ 270 Stats::Formula demandAvgMissLatency; 271 /** The average miss latency for all misses. */ 272 Stats::Formula overallAvgMissLatency; 273 274 /** The total number of cycles blocked for each blocked cause. */ 275 Stats::Vector blocked_cycles; 276 /** The number of times this cache blocked for each blocked cause. */ 277 Stats::Vector blocked_causes; 278 279 /** The average number of cycles blocked for each blocked cause. */ 280 Stats::Formula avg_blocked; 281 282 /** The number of fast writes (WH64) performed. */ 283 Stats::Scalar fastWrites; 284 285 /** The number of cache copies performed. */ 286 Stats::Scalar cacheCopies; 287 288 /** Number of blocks written back per thread. */ 289 Stats::Vector writebacks; 290 291 /** Number of misses that hit in the MSHRs per command and thread. */ 292 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS]; 293 /** Demand misses that hit in the MSHRs. */ 294 Stats::Formula demandMshrHits; 295 /** Total number of misses that hit in the MSHRs. */ 296 Stats::Formula overallMshrHits; 297 298 /** Number of misses that miss in the MSHRs, per command and thread. */ 299 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS]; 300 /** Demand misses that miss in the MSHRs. */ 301 Stats::Formula demandMshrMisses; 302 /** Total number of misses that miss in the MSHRs. */ 303 Stats::Formula overallMshrMisses; 304 305 /** Number of misses that miss in the MSHRs, per command and thread. */ 306 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS]; 307 /** Total number of misses that miss in the MSHRs. */ 308 Stats::Formula overallMshrUncacheable; 309 310 /** Total cycle latency of each MSHR miss, per command and thread. */ 311 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS]; 312 /** Total cycle latency of demand MSHR misses. */ 313 Stats::Formula demandMshrMissLatency; 314 /** Total cycle latency of overall MSHR misses. */ 315 Stats::Formula overallMshrMissLatency; 316 317 /** Total cycle latency of each MSHR miss, per command and thread. */ 318 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; 319 /** Total cycle latency of overall MSHR misses. */ 320 Stats::Formula overallMshrUncacheableLatency; 321 322 /** The total number of MSHR accesses per command and thread. */ 323 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; 324 /** The total number of demand MSHR accesses. */ 325 Stats::Formula demandMshrAccesses; 326 /** The total number of MSHR accesses. */ 327 Stats::Formula overallMshrAccesses; 328 329 /** The miss rate in the MSHRs pre command and thread. */ 330 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; 331 /** The demand miss rate in the MSHRs. */ 332 Stats::Formula demandMshrMissRate; 333 /** The overall miss rate in the MSHRs. */ 334 Stats::Formula overallMshrMissRate; 335 336 /** The average latency of an MSHR miss, per command and thread. */ 337 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS]; 338 /** The average latency of a demand MSHR miss. */ 339 Stats::Formula demandAvgMshrMissLatency; 340 /** The average overall latency of an MSHR miss. */ 341 Stats::Formula overallAvgMshrMissLatency; 342 343 /** The average latency of an MSHR miss, per command and thread. */ 344 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; 345 /** The average overall latency of an MSHR miss. */ 346 Stats::Formula overallAvgMshrUncacheableLatency; 347 348 /** The number of times a thread hit its MSHR cap. */ 349 Stats::Vector mshr_cap_events; 350 /** The number of times software prefetches caused the MSHR to block. */ 351 Stats::Vector soft_prefetch_mshr_full; 352 353 Stats::Scalar mshr_no_allocate_misses; 354 355 /** 356 * @} 357 */ 358 359 /** 360 * Register stats for this object. 361 */ 362 virtual void regStats(); 363 364 public: 365 typedef BaseCacheParams Params; 366 BaseCache(const Params *p); 367 ~BaseCache() {} 368 369 virtual void init(); 370 371 /** 372 * Query block size of a cache. 373 * @return The block size 374 */ 375 unsigned 376 getBlockSize() const 377 { 378 return blkSize; 379 } 380 381 382 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); } 383 384 385 const Range<Addr> &getAddrRange() const { return addrRange; } 386 387 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus) 388 { 389 assert(!pkt->req->isUncacheable()); 390 return allocateBufferInternal(&mshrQueue, 391 blockAlign(pkt->getAddr()), blkSize, 392 pkt, time, requestBus); 393 } 394 395 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus) 396 { 397 assert(pkt->isWrite() && !pkt->isRead()); 398 return allocateBufferInternal(&writeBuffer, 399 pkt->getAddr(), pkt->getSize(), 400 pkt, time, requestBus); 401 } 402 403 MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus) 404 { 405 assert(pkt->req->isUncacheable()); 406 assert(pkt->isRead()); 407 return allocateBufferInternal(&mshrQueue, 408 pkt->getAddr(), pkt->getSize(), 409 pkt, time, requestBus); 410 } 411 412 /** 413 * Returns true if the cache is blocked for accesses. 414 */ 415 bool isBlocked() 416 { 417 return blocked != 0; 418 } 419 420 /** 421 * Marks the access path of the cache as blocked for the given cause. This 422 * also sets the blocked flag in the slave interface. 423 * @param cause The reason for the cache blocking. 424 */ 425 void setBlocked(BlockedCause cause) 426 { 427 uint8_t flag = 1 << cause; 428 if (blocked == 0) { 429 blocked_causes[cause]++; 430 blockedCycle = curTick; 431 cpuSidePort->setBlocked(); 432 } 433 blocked |= flag; 434 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked); 435 } 436 437 /** 438 * Marks the cache as unblocked for the given cause. This also clears the 439 * blocked flags in the appropriate interfaces. 440 * @param cause The newly unblocked cause. 441 * @warning Calling this function can cause a blocked request on the bus to 442 * access the cache. The cache must be in a state to handle that request. 443 */ 444 void clearBlocked(BlockedCause cause) 445 { 446 uint8_t flag = 1 << cause; 447 blocked &= ~flag; 448 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked); 449 if (blocked == 0) { 450 blocked_cycles[cause] += curTick - blockedCycle; 451 cpuSidePort->clearBlocked(); 452 } 453 } 454 455 /** 456 * Request the master bus for the given cause and time. 457 * @param cause The reason for the request. 458 * @param time The time to make the request. 459 */ 460 void requestMemSideBus(RequestCause cause, Tick time) 461 { 462 memSidePort->requestBus(cause, time); 463 } 464 465 /** 466 * Clear the master bus request for the given cause. 467 * @param cause The request reason to clear. 468 */ 469 void deassertMemSideBusRequest(RequestCause cause) 470 { 471 // Obsolete... we no longer signal bus requests explicitly so 472 // we can't deassert them. Leaving this in as a no-op since 473 // the prefetcher calls it to indicate that it no longer wants 474 // to request a prefetch, and someday that might be 475 // interesting again. 476 } 477 478 virtual unsigned int drain(Event *de); 479 480 virtual bool inCache(Addr addr) = 0; 481 482 virtual bool inMissQueue(Addr addr) = 0; 483 484 void incMissCount(PacketPtr pkt) 485 { 486 misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++; 487 488 if (missCount) { 489 --missCount; 490 if (missCount == 0) 491 exitSimLoop("A cache reached the maximum miss count"); 492 } 493 } 494 495}; 496 497#endif //__BASE_CACHE_HH__ 498